[PATCH] arm64: dts: imx8mp-phyboard-pollux: add PEB-WLBT-07 expansion board

[PATCH] arm64: dts: imx8mp-phyboard-pollux: add PEB-WLBT-07 expansion board

[Primoz Fiser]

Add support for PEB-WLBT-07 which is an expansion board that provides
WiFi 6 and Bluetooth 5.4 LE functionality. It features the u-blox
MAYA-W2 module with the NXP IW612 chipset.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm64/boot/dts/freescale/Makefile        |  3 +
 .../imx8mp-phyboard-pollux-peb-wlbt-07.dtso   | 76 +++++++++++++++++++
 2 files changed, 79 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-07.dtso

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 95ae85ab4adf..9c9dcf08c96b 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -456,6 +456,8 @@ imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rd
 	imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtbo
 imx8mp-phyboard-pollux-peb-av-10-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
 	imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtbo
+imx8mp-phyboard-pollux-peb-wlbt-07-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
+	imx8mp-phyboard-pollux-peb-wlbt-07.dtbo
 imx8mp-phyboard-pollux-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
 	imx8mp-phyboard-pollux-ph128800t006.dtbo
 imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo
@@ -465,6 +467,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-etml1010g3dra.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-wlbt-07.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-ph128800t006.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-wlbt.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-07.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-07.dtso
new file mode 100644
index 000000000000..008b6f9f46e5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-07.dtso
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+* Copyright (C) 2026 PHYTEC Messtechnik GmbH
+*/
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx8mp-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+	usdhc1_pwrseq: pwr-seq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&iomuxc {
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS	0x140 /* RTS */
+			MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS	0x140 /* CTS */
+			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140 /* RX */
+			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140 /* TX */
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190 /* SDIO_CLK */
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0 /* SDIO_CMD */
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0 /* SDIO_D0 */
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0 /* SDIO_D1 */
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0 /* SDIO_D2 */
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0 /* SDIO_D3 */
+		>;
+	};
+
+	pinctrl_wlbt: wlbtgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x106 /* WAKE_DEV */
+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x106 /* PDn */
+			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09	0x106 /* WAKE_HOST */
+		>;
+	};
+};
+
+&uart3 {
+	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+	pinctrl-0 = <&pinctrl_uart3>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "nxp,88w8987-bt";
+		vcc-supply = <&reg_vcc_3v3_sw>;
+	};
+};
+
+&usdhc1 {
+	bus-width = <4>;
+	keep-power-in-suspend;
+	max-frequency = <50000000>;
+	mmc-pwrseq = <&usdhc1_pwrseq>;
+	non-removable;
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlbt>;
+	pinctrl-names = "default";
+	vmmc-supply = <&reg_vcc_3v3_sw>;
+	wakeup-source;
+	status = "okay";
+};
-- 
2.34.1

Re: [PATCH] arm64: dts: imx8mp-phyboard-pollux: add PEB-WLBT-07 expansion board

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing `post-power-on-delay-ms` in the MMC power sequence for the NXP IW612 Wi-Fi/BT module.
--

commit 60b0b6fcfb75ad1ee4054d84dfea3d70e8467993
Author: Primoz Fiser <primoz.fiser@norik.com>

arm64: dts: imx8mp-phyboard-pollux: add PEB-WLBT-07 expansion board

Add support for PEB-WLBT-07 which is an expansion board that provides WiFi 6
and Bluetooth 5.4 LE functionality. It features the u-blox MAYA-W2 module
with the NXP IW612 chipset.

[ ... ]

> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-07.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-07.dtso
> new file mode 100644
> index 0000000000000..008b6f9f46e59
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-07.dtso
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> +* Copyright (C) 2026 PHYTEC Messtechnik GmbH
> +*/
> +
> +#include <dt-bindings/clock/imx8mp-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include "imx8mp-pinfunc.h"
> +
> +/dts-v1/;
> +/plugin/;
> +
> +&{/} {
> +	usdhc1_pwrseq: pwr-seq {
> +		compatible = "mmc-pwrseq-simple";
> +		reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
> +	};

[Severity: Medium]
Is it possible that the usdhc1_pwrseq node needs a post-power-on-delay-ms
property here?

When the MMC core powers up the SDIO bus, it deasserts the reset GPIO and
immediately proceeds to probe the module with no explicit delay. If the
SDIO host controller probes the IW612 module immediately after the reset
deassertion and the hardware is not yet stabilized, could this cause SDIO
enumeration failures during device boot or resume?

Other in-tree configurations for the IW61x chipset, such as those in
imx8mm-var-som-wifi-bt-iw61x.dtsi, explicitly configure a delay like
post-power-on-delay-ms = <100>. While there might be an on-board hardware
RC delay on the MAYA-W2 module that mitigates the missing software delay,
adding the explicit software delay might be necessary to guarantee stability.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260827075754.2739119-1-primoz.fiser@norik.com?part=1

Re: [PATCH] arm64: dts: imx8mp-phyboard-pollux: add PEB-WLBT-07 expansion board

[Primoz Fiser]

Hi,

On 8/27/26 10:10, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] Missing `post-power-on-delay-ms` in the MMC power sequence for the NXP IW612 Wi-Fi/BT module.
> --
> 
> commit 60b0b6fcfb75ad1ee4054d84dfea3d70e8467993
> Author: Primoz Fiser <primoz.fiser@norik.com>
> 
> arm64: dts: imx8mp-phyboard-pollux: add PEB-WLBT-07 expansion board
> 
> Add support for PEB-WLBT-07 which is an expansion board that provides WiFi 6
> and Bluetooth 5.4 LE functionality. It features the u-blox MAYA-W2 module
> with the NXP IW612 chipset.
> 
> [ ... ]
> 
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-07.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-07.dtso
>> new file mode 100644
>> index 0000000000000..008b6f9f46e59
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-07.dtso
>> @@ -0,0 +1,76 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>> +/*
>> +* Copyright (C) 2026 PHYTEC Messtechnik GmbH
>> +*/
>> +
>> +#include <dt-bindings/clock/imx8mp-clock.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include "imx8mp-pinfunc.h"
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +
>> +&{/} {
>> +	usdhc1_pwrseq: pwr-seq {
>> +		compatible = "mmc-pwrseq-simple";
>> +		reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
>> +	};
> 
> [Severity: Medium]
> Is it possible that the usdhc1_pwrseq node needs a post-power-on-delay-ms
> property here?
> 
> When the MMC core powers up the SDIO bus, it deasserts the reset GPIO and
> immediately proceeds to probe the module with no explicit delay. If the
> SDIO host controller probes the IW612 module immediately after the reset
> deassertion and the hardware is not yet stabilized, could this cause SDIO
> enumeration failures during device boot or resume?
> 
> Other in-tree configurations for the IW61x chipset, such as those in
> imx8mm-var-som-wifi-bt-iw61x.dtsi, explicitly configure a delay like
> post-power-on-delay-ms = <100>. While there might be an on-board hardware
> RC delay on the MAYA-W2 module that mitigates the missing software delay,
> adding the explicit software delay might be necessary to guarantee stability.

The same PEB-WLBT-07 expansion board on i.MX93 also doesn't use
post-power-on-delay-ms property, see
arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso.

So far no issues without post-power-on-delay-ms property.

I would like to avoid adding such properties "just in case" for now.

Thanks,
BR,
Primoz


> 
> [ ... ]
> 

-- 
Primoz Fiser
phone: +386-41-390-545
email: primoz.fiser@norik.com
--
Norik systems d.o.o.
Your embedded software partner
Slovenia, EU
phone: +386-41-540-545
email: info@norik.com