[PATCH 0/2] gpio: tegra186: Add support for Tegra268

[PATCH 0/2] gpio: tegra186: Add support for Tegra268

[Jon Hunter]

Add support for the GPIO controllers on the Tegra268 device. At the
moment there is no device-tree platform/board supported in the mainline
kernel for Tegra268, but we will be working to add this. For now we are
starting to upstream some basic driver support to pave the way for
supporting Tegra268 based platforms.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
Jon Hunter (2):
      dt-bindings: gpio: Add compatible string for Tegra268
      gpio: tegra186: Add support for Tegra268

 .../bindings/gpio/nvidia,tegra186-gpio.yaml        |  9 +++
 drivers/gpio/gpio-tegra186.c                       | 74 ++++++++++++++++++++++
 2 files changed, 83 insertions(+)
---
base-commit: 3d83758432b5e6ed9507500a57efb0f3af41ee7d
change-id: 20260828-tegra-tegra268-gpio-e77cbf459696

Best regards,
--  
Jon Hunter <jonathanh@nvidia.com>

[PATCH 1/2] dt-bindings: gpio: Add compatible string for Tegra268

[Jon Hunter]

Add compatible strings for the GPIO controllers on the Tegra268 device.
The Tegra268 device has the same GPIO controllers as Tegra264, but only
has a subset of the pins and hence, GPIOs.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
index adeb3b3a2902..fac53e65909b 100644
--- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
@@ -91,6 +91,9 @@ properties:
       - nvidia,tegra264-gpio
       - nvidia,tegra264-gpio-uphy
       - nvidia,tegra264-gpio-aon
+      - nvidia,tegra268-gpio
+      - nvidia,tegra268-gpio-uphy
+      - nvidia,tegra268-gpio-aon
 
   reg-names:
     items:
@@ -169,6 +172,8 @@ allOf:
               - nvidia,tegra256-gpio
               - nvidia,tegra264-gpio
               - nvidia,tegra264-gpio-uphy
+              - nvidia,tegra268-gpio
+              - nvidia,tegra268-gpio-uphy
     then:
       properties:
         interrupts:
@@ -185,6 +190,7 @@ allOf:
               - nvidia,tegra234-gpio-aon
               - nvidia,tegra238-gpio-aon
               - nvidia,tegra264-gpio-aon
+              - nvidia,tegra268-gpio-aon
     then:
       properties:
         interrupts:
@@ -201,6 +207,9 @@ allOf:
               - nvidia,tegra264-gpio
               - nvidia,tegra264-gpio-uphy
               - nvidia,tegra264-gpio-aon
+              - nvidia,tegra268-gpio
+              - nvidia,tegra268-gpio-uphy
+              - nvidia,tegra268-gpio-aon
     then:
       required:
         - wakeup-parent

-- 
2.43.0

[PATCH 2/2] gpio: tegra186: Add support for Tegra268

[Jon Hunter]

Add support for the 3 GPIO controllers, main, AON and UPHY, that are
present on the Tegra268 device. Tegra268 has the same 3 GPIO controllers
as Tegra264, but a subset of the GPIOs. Therefore, we can re-use the
Tegra264 device-tree port definitions for Tegra268 and avoid duplicating
these.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/gpio/gpio-tegra186.c | 74 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
index d9a2dedf50ea..34e084c95d7a 100644
--- a/drivers/gpio/gpio-tegra186.c
+++ b/drivers/gpio/gpio-tegra186.c
@@ -1419,6 +1419,71 @@ static const struct tegra_gpio_soc tegra264_uphy_soc = {
 	.has_vm_support = true,
 };
 
+static const struct tegra_gpio_port tegra268_main_ports[] = {
+	TEGRA264_MAIN_GPIO_PORT(F, 3, 0, 8),
+	TEGRA264_MAIN_GPIO_PORT(G, 3, 1, 5),
+	TEGRA264_MAIN_GPIO_PORT(H, 1, 0, 8),
+	TEGRA264_MAIN_GPIO_PORT(J, 1, 1, 8),
+	TEGRA264_MAIN_GPIO_PORT(K, 1, 2, 8),
+	TEGRA264_MAIN_GPIO_PORT(L, 1, 3, 8),
+	TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 2),
+	TEGRA264_MAIN_GPIO_PORT(P, 2, 0, 8),
+	TEGRA264_MAIN_GPIO_PORT(Q, 2, 1, 8),
+	TEGRA264_MAIN_GPIO_PORT(R, 2, 2, 8),
+	TEGRA264_MAIN_GPIO_PORT(S, 2, 3, 2),
+	TEGRA264_MAIN_GPIO_PORT(T, 0, 0, 7),
+	TEGRA264_MAIN_GPIO_PORT(U, 0, 1, 8),
+	TEGRA264_MAIN_GPIO_PORT(V, 0, 2, 8),
+	TEGRA264_MAIN_GPIO_PORT(W, 0, 3, 8),
+	TEGRA264_MAIN_GPIO_PORT(Y, 0, 5, 8),
+	TEGRA264_MAIN_GPIO_PORT(Z, 0, 6, 8),
+	TEGRA264_MAIN_GPIO_PORT(AL, 0, 4, 3),
+};
+
+static const struct tegra_gpio_soc tegra268_main_soc = {
+	.num_ports = ARRAY_SIZE(tegra268_main_ports),
+	.ports = tegra268_main_ports,
+	.name = "tegra268-gpio",
+	.instance = 0,
+	.num_irqs_per_bank = 8,
+	.has_vm_support = true,
+};
+
+static const struct tegra_gpio_port tegra268_aon_ports[] = {
+	TEGRA264_AON_GPIO_PORT(AA, 0, 0, 8),
+	TEGRA264_AON_GPIO_PORT(BB, 0, 1, 2),
+	TEGRA264_AON_GPIO_PORT(CC, 0, 2, 8),
+	TEGRA264_AON_GPIO_PORT(DD, 0, 3, 8),
+	TEGRA264_AON_GPIO_PORT(EE, 0, 4, 2)
+};
+
+static const struct tegra_gpio_soc tegra268_aon_soc = {
+	.num_ports = ARRAY_SIZE(tegra268_aon_ports),
+	.ports = tegra268_aon_ports,
+	.name = "tegra268-gpio-aon",
+	.instance = 1,
+	.num_irqs_per_bank = 8,
+	.has_gte = true,
+	.has_vm_support = true,
+};
+
+static const struct tegra_gpio_port tegra268_uphy_ports[] = {
+	TEGRA264_UPHY_GPIO_PORT(A, 0, 0, 6),
+	TEGRA264_UPHY_GPIO_PORT(B, 0, 1, 8),
+	TEGRA264_UPHY_GPIO_PORT(C, 0, 2, 3),
+	TEGRA264_UPHY_GPIO_PORT(D, 1, 0, 6),
+	TEGRA264_UPHY_GPIO_PORT(E, 1, 1, 4),
+};
+
+static const struct tegra_gpio_soc tegra268_uphy_soc = {
+	.num_ports = ARRAY_SIZE(tegra268_uphy_ports),
+	.ports = tegra268_uphy_ports,
+	.name = "tegra268-gpio-uphy",
+	.instance = 2,
+	.num_irqs_per_bank = 8,
+	.has_vm_support = true,
+};
+
 #define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
 	TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins)
 
@@ -1528,6 +1593,15 @@ static const struct of_device_id tegra186_gpio_of_match[] = {
 	}, {
 		.compatible = "nvidia,tegra264-gpio-uphy",
 		.data = &tegra264_uphy_soc
+	}, {
+		.compatible = "nvidia,tegra268-gpio",
+		.data = &tegra268_main_soc
+	}, {
+		.compatible = "nvidia,tegra268-gpio-aon",
+		.data = &tegra268_aon_soc
+	}, {
+		.compatible = "nvidia,tegra268-gpio-uphy",
+		.data = &tegra268_uphy_soc
 	}, {
 		/* sentinel */
 	}

-- 
2.43.0

Re: [PATCH 2/2] gpio: tegra186: Add support for Tegra268

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Omitting Port X from `tegra268_main_ports` creates a zero-initialized array hole at index 7 that inadvertently overwrites Port T's interrupt routing configuration with zero, disabling its interrupts.
--

commit 8b9bac08700ce95c0c1a37f57510a697c2d7b282
Author: Jon Hunter <jonathanh@nvidia.com>

gpio: tegra186: Add support for Tegra268
    
Add support for the 3 GPIO controllers, main, AON and UPHY, that are
present on the Tegra268 device. Tegra268 has the same 3 GPIO controllers
as Tegra264, but a subset of the GPIOs. Therefore, we can re-use the
Tegra264 device-tree port definitions for Tegra268 and avoid duplicating
these.

> diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
> index d9a2dedf50eae..34e084c95d7a9 100644
> --- a/drivers/gpio/gpio-tegra186.c
> +++ b/drivers/gpio/gpio-tegra186.c
> @@ -1419,6 +1419,71 @@ static const struct tegra_gpio_soc tegra264_uphy_soc = {
>  	.has_vm_support = true,
>  };
>  
> +static const struct tegra_gpio_port tegra268_main_ports[] = {
> +	TEGRA264_MAIN_GPIO_PORT(F, 3, 0, 8),
> +	TEGRA264_MAIN_GPIO_PORT(G, 3, 1, 5),
> +	TEGRA264_MAIN_GPIO_PORT(H, 1, 0, 8),
> +	TEGRA264_MAIN_GPIO_PORT(J, 1, 1, 8),
> +	TEGRA264_MAIN_GPIO_PORT(K, 1, 2, 8),
> +	TEGRA264_MAIN_GPIO_PORT(L, 1, 3, 8),
> +	TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 2),
> +	TEGRA264_MAIN_GPIO_PORT(P, 2, 0, 8),
> +	TEGRA264_MAIN_GPIO_PORT(Q, 2, 1, 8),
> +	TEGRA264_MAIN_GPIO_PORT(R, 2, 2, 8),
> +	TEGRA264_MAIN_GPIO_PORT(S, 2, 3, 2),
> +	TEGRA264_MAIN_GPIO_PORT(T, 0, 0, 7),
> +	TEGRA264_MAIN_GPIO_PORT(U, 0, 1, 8),
> +	TEGRA264_MAIN_GPIO_PORT(V, 0, 2, 8),
> +	TEGRA264_MAIN_GPIO_PORT(W, 0, 3, 8),
> +	TEGRA264_MAIN_GPIO_PORT(Y, 0, 5, 8),
> +	TEGRA264_MAIN_GPIO_PORT(Z, 0, 6, 8),
> +	TEGRA264_MAIN_GPIO_PORT(AL, 0, 4, 3),
> +};

[Severity: High]
Does omitting Port X from tegra268_main_ports[] create a zero-initialized
gap in this sparse array that inadvertently disables Port T's interrupts?

The TEGRA264_MAIN_GPIO_PORT macro uses designated array initializers mapped
to explicit enum indices. By omitting Port X (index 7), the array has a
zero-initialized hole at index 7 with bank=0, port=0, and pins=0.

Later during the driver's probe phase, tegra186_gpio_init_route_mapping()
iterates up to num_ports:

drivers/gpio/gpio-tegra186.c:tegra186_gpio_init_route_mapping() {
    ...
    for (i = 0; i < gpio->soc->num_ports; i++) {
        const struct tegra_gpio_port *port = &gpio->soc->ports[i];
        unsigned int offset, p = port->port;
        ...
        offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);
        ...
        value = readl(base + offset);
        value = BIT(port->pins) - 1;
        writel(value, base + offset);
    }
}

Because the loop iterates without skipping empty entries, when it reaches
index 7, it maps the coordinates to bank 0, port 0. This overlaps exactly
with Port T which was already configured at index 0.

Could this cause the code to calculate BIT(0) - 1, yielding 0, and write
0 to the INT_ROUTE_MAPPING register, overwriting and destroying the valid
configuration previously set for Port T?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260828-tegra-tegra268-gpio-v1-0-317bd91295e2@nvidia.com?part=2

Re: [PATCH 1/2] dt-bindings: gpio: Add compatible string for Tegra268

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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