[PATCH 1/1] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Set ACSPCIe refclk to MAIN_PLL2_HSDIV4 for pcie1

[PATCH 1/1] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Set ACSPCIe refclk to MAIN_PLL2_HSDIV4 for pcie1

[Jared McArthur]

The ACSPCIe buffers provide the PCIe refclk for external
devices. The ACSPCIe reference clock is muxable between multiple
sources: SERDESx_REF_DER_OUT_CLK, MAIN_PLL2_HSDIV4_CLKOUT, and
SERDESx_REF_OUT_CLK [0]. On reset, the refclk is set to the
SERDESx_REF_DER_OUT_CLK. In the J742S2 and J784S4, "the SerDes PCIe
Reference Clock Output will be temporarily disabled when changing Data
Rates to or from 8.0 GT/s in Derived Refclk mode". Some external PCIe
devices cannot tolerate the reference clock being disabled and will
therefore fail to link.

This advisory is described in more detail as: i2242 of the J784S4
Silicon Revision 1.0 (Rev. B) document [1].

The refclk for devices connected to PCIe1 is provided by the ACSPCIe
buffers in the J742S2XH01EVM [2] and J784S4XEVM [3]. Work around
the advisory by setting the ACSPCIe reference clock source to
MAIN_PLL2_HSDIV4_CLKOUT. Use the TI SCI clock controller to assign the
clock's source [4].

[0] https://www.ti.com/lit/zip/spruj52
[1] https://www.ti.com/lit/er/sprz536b/sprz536b.pdf
[2] https://www.ti.com/lit/zip/SPAC001
[3] https://www.ti.com/lit/zip/SPRR458
[4] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html

Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
index ff3a85cbc524a..7c085663c8880 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
@@ -1206,6 +1206,8 @@ &pcie1_rc {
 	status = "okay";
 	clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
 	clock-names = "fck", "pcie_refclk";
+	assigned-clocks = <&k3_clks 415 0>;
+	assigned-clock-parents = <&k3_clks 415 2>;
 	num-lanes = <2>;
 	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
 	phys = <&serdes0_pcie1_link>;
-- 
2.34.1

Re: [PATCH 1/1] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Set ACSPCIe refclk to MAIN_PLL2_HSDIV4 for pcie1

[Siddharth Vadapalli]

On 29/08/26 01:21, Jared McArthur wrote:
> The ACSPCIe buffers provide the PCIe refclk for external
> devices. The ACSPCIe reference clock is muxable between multiple
> sources: SERDESx_REF_DER_OUT_CLK, MAIN_PLL2_HSDIV4_CLKOUT, and
> SERDESx_REF_OUT_CLK [0]. On reset, the refclk is set to the
> SERDESx_REF_DER_OUT_CLK. In the J742S2 and J784S4, "the SerDes PCIe
> Reference Clock Output will be temporarily disabled when changing Data
> Rates to or from 8.0 GT/s in Derived Refclk mode". Some external PCIe
> devices cannot tolerate the reference clock being disabled and will
> therefore fail to link.
> 
> This advisory is described in more detail as: i2242 of the J784S4
> Silicon Revision 1.0 (Rev. B) document [1].
> 
> The refclk for devices connected to PCIe1 is provided by the ACSPCIe
> buffers in the J742S2XH01EVM [2] and J784S4XEVM [3]. Work around
> the advisory by setting the ACSPCIe reference clock source to
> MAIN_PLL2_HSDIV4_CLKOUT. Use the TI SCI clock controller to assign the
> clock's source [4].
> 
> [0] https://www.ti.com/lit/zip/spruj52
> [1] https://www.ti.com/lit/er/sprz536b/sprz536b.pdf
> [2] https://www.ti.com/lit/zip/SPAC001
> [3] https://www.ti.com/lit/zip/SPRR458
> [4] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html
> 
> Signed-off-by: Jared McArthur <j-mcarthur@ti.com>

Since this seems to be a 'Fix', adding a 'Fixes tag' and copying 
'stable@vger.kernel.org' will get the fix backported to all LTS kernels.

Rest of the patch however looks good to me.

Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Regards,
Siddharth.

> ---
>   arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
> index ff3a85cbc524a..7c085663c8880 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
> @@ -1206,6 +1206,8 @@ &pcie1_rc {
>   	status = "okay";
>   	clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
>   	clock-names = "fck", "pcie_refclk";
> +	assigned-clocks = <&k3_clks 415 0>;
> +	assigned-clock-parents = <&k3_clks 415 2>;
>   	num-lanes = <2>;
>   	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
>   	phys = <&serdes0_pcie1_link>;

Re: [PATCH 1/1] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Set ACSPCIe refclk to MAIN_PLL2_HSDIV4 for pcie1

[Jared McArthur]

On 9/6/26 23:54, Siddharth Vadapalli wrote:
> On 29/08/26 01:21, Jared McArthur wrote:
>> The ACSPCIe buffers provide the PCIe refclk for external
>> devices. The ACSPCIe reference clock is muxable between multiple
>> sources: SERDESx_REF_DER_OUT_CLK, MAIN_PLL2_HSDIV4_CLKOUT, and
>> SERDESx_REF_OUT_CLK [0]. On reset, the refclk is set to the
>> SERDESx_REF_DER_OUT_CLK. In the J742S2 and J784S4, "the SerDes PCIe
>> Reference Clock Output will be temporarily disabled when changing Data
>> Rates to or from 8.0 GT/s in Derived Refclk mode". Some external PCIe
>> devices cannot tolerate the reference clock being disabled and will
>> therefore fail to link.
>>
>> This advisory is described in more detail as: i2242 of the J784S4
>> Silicon Revision 1.0 (Rev. B) document [1].
>>
>> The refclk for devices connected to PCIe1 is provided by the ACSPCIe
>> buffers in the J742S2XH01EVM [2] and J784S4XEVM [3]. Work around
>> the advisory by setting the ACSPCIe reference clock source to
>> MAIN_PLL2_HSDIV4_CLKOUT. Use the TI SCI clock controller to assign the
>> clock's source [4].
>>
>> [0] https://www.ti.com/lit/zip/spruj52
>> [1] https://www.ti.com/lit/er/sprz536b/sprz536b.pdf
>> [2] https://www.ti.com/lit/zip/SPAC001
>> [3] https://www.ti.com/lit/zip/SPRR458
>> [4] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html
>>
>> Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
> 
> Since this seems to be a 'Fix', adding a 'Fixes tag' and copying 'stable@vger.kernel.org' will get the fix backported to all LTS kernels.
> 
> Rest of the patch however looks good to me.
> 
> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> 
> Regards,
> Siddharth.
> 

Thank you for the comments. I have added a "Fixes" tag and your "reviewed-by" and sent a v2 with "stable@vger.kernel.org" cc'd.

>> ---
>>   arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
>> index ff3a85cbc524a..7c085663c8880 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
>> @@ -1206,6 +1206,8 @@ &pcie1_rc {
>>       status = "okay";
>>       clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
>>       clock-names = "fck", "pcie_refclk";
>> +    assigned-clocks = <&k3_clks 415 0>;
>> +    assigned-clock-parents = <&k3_clks 415 2>;
>>       num-lanes = <2>;
>>       reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
>>       phys = <&serdes0_pcie1_link>;
> 

-- 
Best,
Jared McArthur