[PATCH 0/2] ARM: dts: qcom: ipq4019: migrate USB to qcom,snps-dwc3

[PATCH 0/2] ARM: dts: qcom: ipq4019: migrate USB to qcom,snps-dwc3

[Matt Eaton via B4 Relay]

The ipq4019 USB nodes still use the legacy qcom,dwc3 glue, which
describes the DWC3 core as a child node. qcom,snps-dwc3 embeds it in the
glue device instead, so the two nodes collapse into one.

Patch 1 relaxes the interrupt requirements for qcom,ipq4019-dwc3. The
binding groups it with platforms supplying five or six named interrupts,
but neither mainline nor Qualcomm's own vendor devicetree specifies wakeup
interrupts for this SoC, so the migrated devicetree fails dtbs_check
without it.

Patch 2 does the migration, and moves the ap120c-ac SS phy override up to
the parent node since the child's label goes away with it.

Patch 1 is for the USB tree, patch 2 for the qcom tree.

This is a prerequisite for setting per-SoC properties from the qcom glue,
which the legacy path has no mechanism for.

Tested on a Ubiquiti UniFi Travel Router.

Signed-off-by: Matt Eaton <linux@divinehawk.com>
---
Matt Eaton (2):
      dt-bindings: usb: qcom,snps-dwc3: relax interrupt requirements for ipq4019
      ARM: dts: qcom: ipq4019: migrate USB to the qcom,snps-dwc3 glue

 .../devicetree/bindings/usb/qcom,snps-dwc3.yaml    | 23 ++++++++++-
 arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi |  4 --
 arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi           | 46 ++++++++--------------
 3 files changed, 37 insertions(+), 36 deletions(-)
---
base-commit: 18f7fcd5e69a04df57b563360b88be72471d6b62
change-id: 20260829-ipq4019-dwc3-migration-c5e09686a9ad

Best regards,
--  
Matt Eaton <linux@divinehawk.com>

[PATCH 1/2] dt-bindings: usb: qcom,snps-dwc3: relax interrupt requirements for ipq4019

[Matt Eaton via B4 Relay]

From: Matt Eaton <linux@divinehawk.com>

qcom,ipq4019-dwc3 is grouped with the platforms that must supply five or
six named interrupts, but neither mainline nor Qualcomm's own IPQ4019
vendor devicetree specifies any wakeup interrupts for this SoC. Both
describe only the core dwc_usb3 interrupt: GIC_SPI 132 for the usb3
instance and GIC_SPI 136 for the usb2 instance.

commit dd566faebe9f ("dt-bindings: usb: qcom,dwc3: refine interrupt
requirements") listed ipq4019 among the compatibles in this position and
chose to keep the schema warnings for the time being.

Migrating the ipq4019 devicetree onto this binding otherwise fails
dtbs_check:

usb@8a00000 (qcom,ipq4019-dwc3): interrupts: [[0, 132, 4]] is too short
usb@8a00000 (qcom,ipq4019-dwc3): interrupt-names: ['dwc_usb3'] is too short

Give ipq4019 its own clause allowing a single interrupt, and lower the
top-level minimum to match. The per-SoC clause cannot loosen the
top-level constraint on its own, since allOf intersects.

dwc3-qcom.c looks all four wakeup interrupts up with
platform_get_irq_byname_optional(), so nothing in the driver depends on
their presence. If the wakeup interrupt numbers are established later
they can be added without another binding change.

Note that qcom,ipq9574-dwc3, qcom,qcm2290-dwc3, qcom,sar2130p-dwc3 and
qcom,sm6375-dwc3 have no per-SoC interrupt clause and relied on the
top-level minimum, so they are left unconstrained at the low end by this
change.

Signed-off-by: Matt Eaton <linux@divinehawk.com>
---
 .../devicetree/bindings/usb/qcom,snps-dwc3.yaml    | 23 ++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
index 7d784a648b7d..28e78302b814 100644
--- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
@@ -137,11 +137,11 @@ properties:
                                only on SoCs with non-QUSB2 targets with
                                exception of SDM670/SDM845/SM6350.
         - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
-    minItems: 3
+    minItems: 1
     maxItems: 19
 
   interrupt-names:
-    minItems: 3
+    minItems: 1
     maxItems: 19
 
   qcom,select-utmi-as-pipe-clk:
@@ -508,6 +508,25 @@ allOf:
           contains:
             enum:
               - qcom,ipq4019-dwc3
+    then:
+      properties:
+        interrupts:
+          minItems: 1
+          maxItems: 6
+        interrupt-names:
+          minItems: 1
+          items:
+            - const: dwc_usb3
+            - const: pwr_event
+            - const: hs_phy_irq
+            - const: dp_hs_phy_irq
+            - const: dm_hs_phy_irq
+            - const: ss_phy_irq
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
               - qcom,ipq8064-dwc3
               - qcom,kaanapali-dwc3
               - qcom,qcs615-dwc3

-- 
2.43.0

[PATCH 2/2] ARM: dts: qcom: ipq4019: migrate USB to the qcom,snps-dwc3 glue

[Matt Eaton via B4 Relay]

From: Matt Eaton <linux@divinehawk.com>

The legacy qcom,dwc3 glue describes the DWC3 core as a child node and
populates it with of_platform_populate(). qcom,snps-dwc3 embeds the core
in the glue device instead, so the two nodes collapse into one and the
unit address moves to the core base.

The QSCRATCH register block sits at a fixed 0xf8800 from the core base on
this SoC, which is what dwc3-qcom.c already assumes, so no driver change
is needed:

  usb3: 0x8a00000 + 0xf8800 = 0x8af8800
  usb2: 0x6000000 + 0xf8800 = 0x60f8800

Both match the addresses the wrapper nodes used before.

The usb3_dwc label goes away with the child node, so the ap120c-ac
override of the SS phy moves up to the parent.

Signed-off-by: Matt Eaton <linux@divinehawk.com>
---
 arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi |  4 --
 arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi           | 46 ++++++++--------------
 2 files changed, 16 insertions(+), 34 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi
index be76bc39ac27..49c8ce80ac14 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi
@@ -260,10 +260,6 @@ &usb3_hs_phy {
 
 &usb3 {
 	status = "okay";
-
-	};
-
-&usb3_dwc {
 	phys = <&usb3_hs_phy>;
 	phy-names = "usb2-phy";
 };
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index 8eeaab1c0be1..18c386ae9af7 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -654,26 +654,19 @@ usb3_hs_phy: usb-phy@a6000 {
 			status = "disabled";
 		};
 
-		usb3: usb@8af8800 {
-			compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
-			reg = <0x8af8800 0x100>;
-			#address-cells = <1>;
-			#size-cells = <1>;
+		usb3: usb@8a00000 {
+			compatible = "qcom,ipq4019-dwc3", "qcom,snps-dwc3";
+			reg = <0x8a00000 0xf8c00>;
+			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dwc_usb3";
 			clocks = <&gcc GCC_USB3_MASTER_CLK>,
 				 <&gcc GCC_USB3_SLEEP_CLK>,
 				 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
 			clock-names = "core", "sleep", "mock_utmi";
-			ranges;
+			phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+			phy-names = "usb2-phy", "usb3-phy";
+			dr_mode = "host";
 			status = "disabled";
-
-			usb3_dwc: usb@8a00000 {
-				compatible = "snps,dwc3";
-				reg = <0x8a00000 0xf8000>;
-				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
-				phy-names = "usb2-phy", "usb3-phy";
-				dr_mode = "host";
-			};
 		};
 
 		usb2_hs_phy: usb-phy@a8000 {
@@ -686,26 +679,19 @@ usb2_hs_phy: usb-phy@a8000 {
 			status = "disabled";
 		};
 
-		usb2: usb@60f8800 {
-			compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
-			reg = <0x60f8800 0x100>;
-			#address-cells = <1>;
-			#size-cells = <1>;
+		usb2: usb@6000000 {
+			compatible = "qcom,ipq4019-dwc3", "qcom,snps-dwc3";
+			reg = <0x6000000 0xf8c00>;
+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dwc_usb3";
 			clocks = <&gcc GCC_USB2_MASTER_CLK>,
 				 <&gcc GCC_USB2_SLEEP_CLK>,
 				 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
 			clock-names = "core", "sleep", "mock_utmi";
-			ranges;
+			phys = <&usb2_hs_phy>;
+			phy-names = "usb2-phy";
+			dr_mode = "host";
 			status = "disabled";
-
-			usb@6000000 {
-				compatible = "snps,dwc3";
-				reg = <0x6000000 0xf8000>;
-				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&usb2_hs_phy>;
-				phy-names = "usb2-phy";
-				dr_mode = "host";
-			};
 		};
 	};
 };

-- 
2.43.0

Re: [PATCH 1/2] dt-bindings: usb: qcom,snps-dwc3: relax interrupt requirements for ipq4019

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Relaxing the global minimum constraints for 'interrupts' and 'interrupt-names' unintentionally leaves multiple SoCs underconstrained, allowing invalid DT configurations to pass validation.
--

commit 245becf7a38f613732404251842cf1f13abb06d5
Author: Matt Eaton <linux@divinehawk.com>
dt-bindings: usb: qcom,snps-dwc3: relax interrupt requirements for ipq4019

This commit lowers the global minimum interrupt count for qcom,snps-dwc3 to 1
to accommodate qcom,ipq4019-dwc3, adding a dedicated if-then block for it.
It also notes that several other SoCs relied on the top-level minimum and
are subsequently left unconstrained at the low end.

> diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> index 7d784a648b7d9..28e78302b814d 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> @@ -137,11 +137,11 @@ properties:
>                                 only on SoCs with non-QUSB2 targets with
>                                 exception of SDM670/SDM845/SM6350.
>          - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
> -    minItems: 3
> +    minItems: 1
>      maxItems: 19
>  
>    interrupt-names:
> -    minItems: 3
> +    minItems: 1

[Severity: Medium]
Does lowering the global minimum here unintentionally break validation for
SoCs that relied on the global minimum? For example, device trees defining
qcom,ipq5018-dwc3 or qcom,ipq5332-dwc3 with an incomplete interrupt
specification (like 1 interrupt instead of the required 3 or 4) will no
longer report an error during dtbs_check.

[ ... ]

> @@ -508,6 +508,25 @@ allOf:
>            contains:
>              enum:
>                - qcom,ipq4019-dwc3
> +    then:
> +      properties:
> +        interrupts:
> +          minItems: 1
> +          maxItems: 6
> +        interrupt-names:
> +          minItems: 1
> +          items:
> +            - const: dwc_usb3
> +            - const: pwr_event
> +            - const: hs_phy_irq
> +            - const: dp_hs_phy_irq
> +            - const: dm_hs_phy_irq
> +            - const: ss_phy_irq

[Severity: Medium]
The commit message explicitly notes that qcom,ipq9574-dwc3,
qcom,qcm2290-dwc3, qcom,sar2130p-dwc3 and qcom,sm6375-dwc3 are left
unconstrained at the low end by this change. Should new if-then
conditional blocks be added here for these SoCs to properly enforce their
original interrupt minimum counts? Without them, invalid configurations for
these variants will silently pass validation.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260829-ipq4019-dwc3-migration-v1-0-cc66b54ce21c@divinehawk.com?part=1

Re: [PATCH 1/2] dt-bindings: usb: qcom,snps-dwc3: relax interrupt requirements for ipq4019

[Matt Eaton]

On Sat, Aug 29, 2026 at 9:41 PM <sashiko-bot@kernel.org> wrote:
>
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] Relaxing the global minimum constraints for 'interrupts' and 'interrupt-names' unintentionally leaves multiple SoCs underconstrained, allowing invalid DT configurations to pass validation.
> --
>
> commit 245becf7a38f613732404251842cf1f13abb06d5
> Author: Matt Eaton <linux@divinehawk.com>
> dt-bindings: usb: qcom,snps-dwc3: relax interrupt requirements for ipq4019
>
> This commit lowers the global minimum interrupt count for qcom,snps-dwc3 to 1
> to accommodate qcom,ipq4019-dwc3, adding a dedicated if-then block for it.
> It also notes that several other SoCs relied on the top-level minimum and
> are subsequently left unconstrained at the low end.
>
> > diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> > index 7d784a648b7d9..28e78302b814d 100644
> > --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> > +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> > @@ -137,11 +137,11 @@ properties:
> >                                 only on SoCs with non-QUSB2 targets with
> >                                 exception of SDM670/SDM845/SM6350.
> >          - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
> > -    minItems: 3
> > +    minItems: 1
> >      maxItems: 19
> >
> >    interrupt-names:
> > -    minItems: 3
> > +    minItems: 1
>
> [Severity: Medium]
> Does lowering the global minimum here unintentionally break validation for
> SoCs that relied on the global minimum? For example, device trees defining
> qcom,ipq5018-dwc3 or qcom,ipq5332-dwc3 with an incomplete interrupt
> specification (like 1 interrupt instead of the required 3 or 4) will no
> longer report an error during dtbs_check.
>
> [ ... ]
>
> > @@ -508,6 +508,25 @@ allOf:
> >            contains:
> >              enum:
> >                - qcom,ipq4019-dwc3
> > +    then:
> > +      properties:
> > +        interrupts:
> > +          minItems: 1
> > +          maxItems: 6
> > +        interrupt-names:
> > +          minItems: 1
> > +          items:
> > +            - const: dwc_usb3
> > +            - const: pwr_event
> > +            - const: hs_phy_irq
> > +            - const: dp_hs_phy_irq
> > +            - const: dm_hs_phy_irq
> > +            - const: ss_phy_irq
>
> [Severity: Medium]
> The commit message explicitly notes that qcom,ipq9574-dwc3,
> qcom,qcm2290-dwc3, qcom,sar2130p-dwc3 and qcom,sm6375-dwc3 are left
> unconstrained at the low end by this change. Should new if-then
> conditional blocks be added here for these SoCs to properly enforce their
> original interrupt minimum counts? Without them, invalid configurations for
> these variants will silently pass validation.
>
I have a fix prepped for v2. Standing by for any other feedback.

Much appreciated,
Matt Eaton

Re: [PATCH 2/2] ARM: dts: qcom: ipq4019: migrate USB to the qcom,snps-dwc3 glue

[Konrad Dybcio]

On 8/29/26 9:31 PM, Matt Eaton via B4 Relay wrote:
> From: Matt Eaton <linux@divinehawk.com>
> 
> The legacy qcom,dwc3 glue describes the DWC3 core as a child node and
> populates it with of_platform_populate(). qcom,snps-dwc3 embeds the core
> in the glue device instead, so the two nodes collapse into one and the
> unit address moves to the core base.
> 
> The QSCRATCH register block sits at a fixed 0xf8800 from the core base on
> this SoC, which is what dwc3-qcom.c already assumes, so no driver change
> is needed:
> 
>   usb3: 0x8a00000 + 0xf8800 = 0x8af8800
>   usb2: 0x6000000 + 0xf8800 = 0x60f8800
> 
> Both match the addresses the wrapper nodes used before.
> 
> The usb3_dwc label goes away with the child node, so the ap120c-ac
> override of the SS phy moves up to the parent.
> 
> Signed-off-by: Matt Eaton <linux@divinehawk.com>
> ---

I can also see:

	     usb2 | usb3
pwr_event  | 135  | 131

Konrad