Re: [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The `ranges` property in `tegra_ahub` has an incorrect number of cells, causing device tree translation failure.
- [High] Syntax error and malformed cell count in the `reg` property of `tegra_sfc2`.
--

commit e1dacd52fef2161b800fe722394a96baeac1b62f
Author: Thierry Reding <treding@nvidia.com>

arm64: tegra: Clean up AHUB on Tegra264

This commit updates the device tree properties for the AHUB and related
components on Tegra264, changing #address-cells and #size-cells to 1.
It also adjusts the ranges property and simplifies the register offsets
throughout the audio subsystem.

> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index 6b2e3a6ab810f..4ed7dabafee5d 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
[ ... ]
> @@ -209,22 +209,22 @@ adma: dma-controller@9440000 {
>  
>  			tegra_ahub: ahub@9630000 {
>  				compatible = "nvidia,tegra264-ahub";
> -				reg = <0x0 0x9630000 0x0 0x10000>;
> +				reg = <0x9630000 0x10000>;
>  				clocks = <&bpmp TEGRA264_CLK_AHUB>;
>  				clock-names = "ahub";
>  				assigned-clocks = <&bpmp TEGRA264_CLK_AHUB>;
>  				assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON_APE>;
>  				status = "disabled";
>  
> -				#address-cells = <2>;
> -				#size-cells = <2>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
>  				/* ADMA is under AHUB range, its excluded in the defined range */
> -				ranges = <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>,
> -					<0x0 0x9510000 0x0 0x9510000 0x0 0x370000>;
> +				ranges = <0x9280000 0x0 0x9280000 0x1c0000>,
> +					 <0x9510000 0x0 0x9510000 0x370000>;

[Severity: High]
Since tegra_ahub and its parent aconnect both define #address-cells = <1>
and #size-cells = <1>, shouldn't the ranges property have exactly 3 cells
per entry (child-address, parent-address, length)?

The updated values still contain 4 cells per entry, which looks like it
failed to remove the stale 32-bit 0x0 from the previous 64-bit parent
address layout. Will this malformed cell count cause dtc to fail validation
and prevent MMIO address mapping for audio peripherals on the AHUB?

>  
>  				tegra_i2s1: i2s@9280000 {
[ ... ]
> @@ -1584,7 +1584,7 @@ sfc1_cif_out: endpoint {
>  				tegra_sfc2: sfc@9710000 {
>  					compatible = "nvidia,tegra264-sfc",
>  							"nvidia,tegra210-sfc";
> -					reg = <0x0 0x9710000 0x0 0x10000>;
> +					reg = <0x9710000 x0 0x10000>;

[Severity: High]
Does this introduce a syntax error in the device tree? The x0 token appears
to be a typo, which would cause dtc compilation to abort.

Additionally, even if parsed as zero, wouldn't this result in 3 cells
instead of the 2 cells expected by the #address-cells = <1> and
#size-cells = <1> configuration?

>  					sound-name-prefix = "SFC2";
>  
>  					ports {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com?part=7