Re: [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264

[Thierry Reding <thierry.reding@kernel.org>]

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On Thu, Sep 10, 2026 at 05:36:41PM +0100, Jon Hunter wrote:
> 
> 
> On 02/09/2026 11:17, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > Use #address-cells = <1> and #size-cells = <1> because we don't need
> > 64-bit register addressing for this hardware. While at it, also adjust
> > the ranges property to encompass the entire AHUB range as per the TRM.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >   arch/arm64/boot/dts/nvidia/tegra264.dtsi | 118 +++++++++++++++----------------
> >   1 file changed, 59 insertions(+), 59 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> > index 6b2e3a6ab810..4ed7dabafee5 100644
> > --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> > +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> > @@ -129,13 +129,13 @@ aconnect@9000000 {
> >   			power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>;
> >   			status = "disabled";
> 
> ...
> 
> >   					ports {
> > @@ -1584,7 +1584,7 @@ sfc1_cif_out: endpoint {
> >   				tegra_sfc2: sfc@9710000 {
> >   					compatible = "nvidia,tegra264-sfc",
> >   							"nvidia,tegra210-sfc";
> > -					reg = <0x0 0x9710000 0x0 0x10000>;
> > +					reg = <0x9710000 x0 0x10000>;
> 
> 
> Looks like a typo crept in here 'x0' which is what kernelci is
> complaining about [0].

Ugh... I had fixed this up in a local branch but then applied the
patches from the list instead... fixed now.

Thierry

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