* [PATCH 0/2] arm64: dts: broadcom: bcm2712: Enable SPI
@ 2026-08-11 16:04 Gregor Herburger
2026-08-11 16:04 ` [PATCH 1/2] arm64: dts: broadcom: rp1: add spi controller Gregor Herburger
2026-08-11 16:04 ` [PATCH 2/2] arm64: dts: broadcom: bcm2712-rpi-5-b: add spi0 interface Gregor Herburger
0 siblings, 2 replies; 6+ messages in thread
From: Gregor Herburger @ 2026-08-11 16:04 UTC (permalink / raw)
To: Andrea della Porta, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list
Cc: devicetree, linux-kernel, linux-rpi-kernel, linux-arm-kernel,
Gregor Herburger
The RP1 chip, found on the raspberry Pi 5, has nine spi controllers. The
spi0 is routed to the pin header. Add the rp1 nodes and enable it for
the Raspberry Pi 5.
---
Gregor Herburger (2):
arm64: dts: broadcom: rp1: add spi controller
arm64: dts: broadcom: bcm2712-rpi-5-b: add spi0 interface
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 16 +++
arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 119 +++++++++++++++++++++++
2 files changed, 135 insertions(+)
---
base-commit: db2ddb87143519e20a95aa36c60b36107b736a58
change-id: 20260811-bcm2712-spi-644b70fee3bf
Best regards,
--
Gregor Herburger <gregor.herburger@linutronix.de>
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/2] arm64: dts: broadcom: rp1: add spi controller
2026-08-11 16:04 [PATCH 0/2] arm64: dts: broadcom: bcm2712: Enable SPI Gregor Herburger
@ 2026-08-11 16:04 ` Gregor Herburger
2026-09-03 19:46 ` Florian Fainelli
2026-08-11 16:04 ` [PATCH 2/2] arm64: dts: broadcom: bcm2712-rpi-5-b: add spi0 interface Gregor Herburger
1 sibling, 1 reply; 6+ messages in thread
From: Gregor Herburger @ 2026-08-11 16:04 UTC (permalink / raw)
To: Andrea della Porta, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list
Cc: devicetree, linux-kernel, linux-rpi-kernel, linux-arm-kernel,
Gregor Herburger
The rp1 processor found on the Raspberry Pi 5 has nine Synchronous
Serial Interfaces.
Add the relevant nodes to the devicetree.
Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
---
arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 119 +++++++++++++++++++++++++++
1 file changed, 119 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
index 16f5359395835..8d9de71efdba9 100644
--- a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
+++ b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
@@ -26,6 +26,125 @@ rp1_clocks: clocks@40018000 {
<200000000>; // RP1_CLK_SYS
};
+ rp1_spi8: spi@4004c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x00 0x4004c000 0x0 0x130>;
+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rp1_clocks RP1_CLK_SYS>;
+ clock-names = "ssi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <2>;
+
+ status = "disabled";
+ };
+
+ rp1_spi0: spi@40050000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x00 0x40050000 0x0 0x130>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rp1_clocks RP1_CLK_SYS>;
+ clock-names = "ssi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <4>;
+
+ status = "disabled";
+ };
+
+ rp1_spi1: spi@40054000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x00 0x40054000 0x0 0x130>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rp1_clocks RP1_CLK_SYS>;
+ clock-names = "ssi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <3>;
+
+ status = "disabled";
+ };
+
+ rp1_spi2: spi@40058000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x00 0x40058000 0x0 0x130>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rp1_clocks RP1_CLK_SYS>;
+ clock-names = "ssi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <2>;
+
+ status = "disabled";
+ };
+
+ rp1_spi3: spi@4005c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x00 0x4005c000 0x0 0x130>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rp1_clocks RP1_CLK_SYS>;
+ clock-names = "ssi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <2>;
+
+ status = "disabled";
+ };
+
+ rp1_spi4: spi@40060000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x00 0x40060000 0x0 0x130>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rp1_clocks RP1_CLK_SYS>;
+ clock-names = "ssi_clk";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ spi-slave;
+
+ status = "disabled";
+ };
+
+ rp1_spi5: spi@40064000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x00 0x40064000 0x0 0x130>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rp1_clocks RP1_CLK_SYS>;
+ clock-names = "ssi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <2>;
+
+ status = "disabled";
+ };
+
+ rp1_spi6: spi@40068000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x00 0x40068000 0x0 0x130>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rp1_clocks RP1_CLK_SYS>;
+ clock-names = "ssi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <3>;
+
+ status = "disabled";
+ };
+
+ rp1_spi7: spi@4006c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x00 0x4006c000 0x0 0x130>;
+ interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rp1_clocks RP1_CLK_SYS>;
+ clock-names = "ssi_clk";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ spi-slave;
+
+ status = "disabled";
+ };
+
rp1_i2c0: i2c@40070000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x40070000 0x0 0x1000>;
--
2.47.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 1/2] arm64: dts: broadcom: rp1: add spi controller
2026-08-11 16:04 ` [PATCH 1/2] arm64: dts: broadcom: rp1: add spi controller Gregor Herburger
@ 2026-09-03 19:46 ` Florian Fainelli
0 siblings, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2026-09-03 19:46 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Gregor Herburger, Andrea della Porta,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Florian Fainelli
Cc: Florian Fainelli, devicetree, linux-kernel, linux-rpi-kernel,
linux-arm-kernel
From: Florian Fainelli <f.fainelli@gmail.com>
On Tue, 11 Aug 2026 18:04:15 +0200, Gregor Herburger <gregor.herburger@linutronix.de> wrote:
> The rp1 processor found on the Raspberry Pi 5 has nine Synchronous
> Serial Interfaces.
>
> Add the relevant nodes to the devicetree.
>
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] arm64: dts: broadcom: bcm2712-rpi-5-b: add spi0 interface
2026-08-11 16:04 [PATCH 0/2] arm64: dts: broadcom: bcm2712: Enable SPI Gregor Herburger
2026-08-11 16:04 ` [PATCH 1/2] arm64: dts: broadcom: rp1: add spi controller Gregor Herburger
@ 2026-08-11 16:04 ` Gregor Herburger
2026-09-03 16:26 ` Andrea della Porta
1 sibling, 1 reply; 6+ messages in thread
From: Gregor Herburger @ 2026-08-11 16:04 UTC (permalink / raw)
To: Andrea della Porta, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list
Cc: devicetree, linux-kernel, linux-rpi-kernel, linux-arm-kernel,
Gregor Herburger
The Raspberry Pi 5 routes the spi0 of the rp1 chip to the pin header.
Add the rp1_spi0 node and its pinctrl node to the devicetree to enable
the spi interface.
Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
---
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
index 0fc57e72632ed..81aec81c5ce12 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
@@ -69,6 +69,14 @@ usb_vbus_default_state: usb-vbus-default-state {
groups = "vbus1";
};
+ rp1_spi0_default_state: rp1-spi0-default-state {
+ function = "spi0";
+ groups = "spi0";
+ bias-disable;
+ drive-strength = <12>;
+ slew-rate = <1>;
+ };
+
rp1_i2c4_default_state: rp1-i2c4-default-state {
function = "i2c4";
groups = "i2c4_2";
@@ -94,6 +102,14 @@ &rp1_i2c6 {
pinctrl-names = "default";
};
+&rp1_spi0 {
+ pinctrl-0 = <&rp1_spi0_default_state>;
+ pinctrl-names = "default";
+
+ num-cs = <2>;
+ cs-gpios = <&rp1_gpio 8 GPIO_ACTIVE_LOW &rp1_gpio 7 GPIO_ACTIVE_LOW>;
+};
+
&rp1_usb0 {
pinctrl-0 = <&usb_vbus_default_state>;
pinctrl-names = "default";
--
2.47.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] arm64: dts: broadcom: bcm2712-rpi-5-b: add spi0 interface
2026-08-11 16:04 ` [PATCH 2/2] arm64: dts: broadcom: bcm2712-rpi-5-b: add spi0 interface Gregor Herburger
@ 2026-09-03 16:26 ` Andrea della Porta
2026-09-03 20:58 ` Gregor Herburger
0 siblings, 1 reply; 6+ messages in thread
From: Andrea della Porta @ 2026-09-03 16:26 UTC (permalink / raw)
To: Gregor Herburger
Cc: Andrea della Porta, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, devicetree, linux-kernel,
linux-rpi-kernel, linux-arm-kernel
Hi Gregor,
On 18:04 Tue 11 Aug , Gregor Herburger wrote:
> The Raspberry Pi 5 routes the spi0 of the rp1 chip to the pin header.
> Add the rp1_spi0 node and its pinctrl node to the devicetree to enable
> the spi interface.
>
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
> ---
> arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> index 0fc57e72632ed..81aec81c5ce12 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> @@ -69,6 +69,14 @@ usb_vbus_default_state: usb-vbus-default-state {
> groups = "vbus1";
> };
>
> + rp1_spi0_default_state: rp1-spi0-default-state {
> + function = "spi0";
> + groups = "spi0";
> + bias-disable;
> + drive-strength = <12>;
> + slew-rate = <1>;
> + };
> +
> rp1_i2c4_default_state: rp1-i2c4-default-state {
> function = "i2c4";
> groups = "i2c4_2";
> @@ -94,6 +102,14 @@ &rp1_i2c6 {
> pinctrl-names = "default";
> };
>
> +&rp1_spi0 {
> + pinctrl-0 = <&rp1_spi0_default_state>;
Is there any reason to avoid defining the CS pins as pulled-up gpios
in the rp1_gpio node and then referencing it in pinctrl-0?
Something like thie following:
rp1_spi0_cs_default_state: rp1-spi0-cs-default-state {
function = "gpio";
pins = "gpio7", "gpio8";
bias-pull-up;
};
&rp1_spi0 {
...
pinctrl-0 = <&rp1_spi0_default_state &rp1_spi0_cs_default_state>;
...
};
Many thanks,
Andrea
> + pinctrl-names = "default";
> +
> + num-cs = <2>;
> + cs-gpios = <&rp1_gpio 8 GPIO_ACTIVE_LOW &rp1_gpio 7 GPIO_ACTIVE_LOW>;
> +};
> +
> &rp1_usb0 {
> pinctrl-0 = <&usb_vbus_default_state>;
> pinctrl-names = "default";
>
> --
> 2.47.3
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] arm64: dts: broadcom: bcm2712-rpi-5-b: add spi0 interface
2026-09-03 16:26 ` Andrea della Porta
@ 2026-09-03 20:58 ` Gregor Herburger
0 siblings, 0 replies; 6+ messages in thread
From: Gregor Herburger @ 2026-09-03 20:58 UTC (permalink / raw)
To: Andrea della Porta
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list, devicetree, linux-kernel,
linux-rpi-kernel, linux-arm-kernel
On Thu, Sep 03, 2026 at 06:26:19PM +0200, Andrea della Porta wrote:
> Hi Gregor,
>
> On 18:04 Tue 11 Aug , Gregor Herburger wrote:
> > The Raspberry Pi 5 routes the spi0 of the rp1 chip to the pin header.
> > Add the rp1_spi0 node and its pinctrl node to the devicetree to enable
> > the spi interface.
> >
> > Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
> > ---
> > arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> > index 0fc57e72632ed..81aec81c5ce12 100644
> > --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> > +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
> > @@ -69,6 +69,14 @@ usb_vbus_default_state: usb-vbus-default-state {
> > groups = "vbus1";
> > };
> >
> > + rp1_spi0_default_state: rp1-spi0-default-state {
> > + function = "spi0";
> > + groups = "spi0";
> > + bias-disable;
> > + drive-strength = <12>;
> > + slew-rate = <1>;
> > + };
> > +
> > rp1_i2c4_default_state: rp1-i2c4-default-state {
> > function = "i2c4";
> > groups = "i2c4_2";
> > @@ -94,6 +102,14 @@ &rp1_i2c6 {
> > pinctrl-names = "default";
> > };
> >
> > +&rp1_spi0 {
> > + pinctrl-0 = <&rp1_spi0_default_state>;
>
> Is there any reason to avoid defining the CS pins as pulled-up gpios
> in the rp1_gpio node and then referencing it in pinctrl-0?
No there is no reason for this. I will try it and send a new version.
> Something like thie following:
>
> rp1_spi0_cs_default_state: rp1-spi0-cs-default-state {
> function = "gpio";
> pins = "gpio7", "gpio8";
> bias-pull-up;
> };
>
> &rp1_spi0 {
> ...
> pinctrl-0 = <&rp1_spi0_default_state &rp1_spi0_cs_default_state>;
> ...
> };
>
>
> Many thanks,
> Andrea
>
> > + pinctrl-names = "default";
> > +
> > + num-cs = <2>;
> > + cs-gpios = <&rp1_gpio 8 GPIO_ACTIVE_LOW &rp1_gpio 7 GPIO_ACTIVE_LOW>;
> > +};
> > +
> > &rp1_usb0 {
> > pinctrl-0 = <&usb_vbus_default_state>;
> > pinctrl-names = "default";
> >
> > --
> > 2.47.3
> >
--
Gregor Herburger
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^ permalink raw reply [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2026-08-11 16:04 [PATCH 0/2] arm64: dts: broadcom: bcm2712: Enable SPI Gregor Herburger
2026-08-11 16:04 ` [PATCH 1/2] arm64: dts: broadcom: rp1: add spi controller Gregor Herburger
2026-09-03 19:46 ` Florian Fainelli
2026-08-11 16:04 ` [PATCH 2/2] arm64: dts: broadcom: bcm2712-rpi-5-b: add spi0 interface Gregor Herburger
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