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From: Conor Dooley <conor@kernel.org>
To: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Thinh Nguyen <Thinh.Nguyen@synopsys.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Dinh Nguyen <dinguyen@kernel.org>,
	linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 1/4] dt-bindings: usb: add Altera Agilex5 DWC3 controller
Date: Fri, 4 Sep 2026 16:19:14 +0100	[thread overview]
Message-ID: <20260904-survive-kindred-420cac7236f7@spud> (raw)
In-Reply-To: <56c7cb879f6c1b8e835a34522a02f55b9178c3c2.1788503540.git.adrian.ho.yin.ng@altera.com>

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On Fri, Sep 04, 2026 at 04:46:10PM +0800, Adrian Ng Ho Yin wrote:
> Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3
> USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets,
> PHYs, and optional IOMMU support.
> 
> Clock names follow the snps,dwc3.yaml example order (bus_early, ref,
> suspend). Reset names use core/ecc. On this SoC ref and suspend are the
> same hardware source, so the example reuses AGILEX5_USB31_SUSPEND_CLK.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> ---
>  .../bindings/usb/altr,agilex5-dwc3.yaml       | 100 ++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> new file mode 100644
> index 000000000000..e172706474f5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera Agilex5 DWC3 USB SoC Controller
> +
> +maintainers:
> +  - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> +
> +description:
> +  The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3)
> +  controller that supports host, device and DRD modes.
> +
> +allOf:
> +  - $ref: snps,dwc3-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: altr,agilex5-dwc3
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Master/Core bus clock
> +      - description: Controller reference clock
> +      - description: Controller suspend clock
> +
> +  clock-names:
> +    items:
> +      - const: bus_early
> +      - const: ref
> +      - const: suspend
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  phys:
> +    minItems: 2
> +    maxItems: 2
> +
> +  phy-names:
> +    items:
> +      - const: usb2-phy
> +      - const: usb3-phy
> +
> +  iommus:
> +    maxItems: 1
> +
> +  resets:
> +    items:
> +      - description: DWC3 core reset
> +      - description: DWC3 ECC reset
> +
> +  reset-names:
> +    items:
> +      - const: core
> +      - const: ecc
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - phys
> +  - phy-names
> +  - resets
> +  - reset-names
> +
> +unevaluatedProperties: false

I'm never keen on unevaluatedProperties for dwc3 stuff, cos there are
lots of properties in there that I do not believe should be used in
general.
Could you instead use "additionalProperties: false" and add "foo: true"
for any properties (other than the ones you've already got) that you
need?

Otherwise, this looks good to me.
pw-bot: changes-requested

Thanks,
Conor.

> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/reset/altr,rst-mgr-s10.h>
> +    #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
> +
> +    soc {
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +
> +        usb@11000000 {
> +            compatible = "altr,agilex5-dwc3";
> +            reg = <0x11000000 0x100000>;
> +            interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +            clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>,
> +                     <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
> +                     <&clkmgr AGILEX5_USB31_SUSPEND_CLK>;
> +            clock-names = "bus_early", "ref", "suspend";
> +            phys = <&usbphy0>, <&usbphy1>;
> +            phy-names = "usb2-phy", "usb3-phy";
> +            resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
> +            reset-names = "core", "ecc";
> +            iommus = <&smmu 7>;
> +        };
> +    };
> -- 
> 2.49.GIT
> 

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  reply	other threads:[~2026-09-04 15:19 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-04  8:46 [PATCH v4 0/4] Add USB3.1 support for Agilex5 Adrian Ng Ho Yin
2026-09-04  8:46 ` [PATCH v4 1/4] dt-bindings: usb: add Altera Agilex5 DWC3 controller Adrian Ng Ho Yin
2026-09-04 15:19   ` Conor Dooley [this message]
2026-09-04  8:46 ` [PATCH v4 2/4] arm64: dts: intel: agilex5: add USB3.1 controller node Adrian Ng Ho Yin
2026-09-04  9:06   ` sashiko-bot
2026-09-04  8:46 ` [PATCH v4 3/4] arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK Adrian Ng Ho Yin
2026-09-04  8:46 ` [PATCH v4 4/4] usb: dwc3: add Altera Agilex5 support to generic platform driver Adrian Ng Ho Yin

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