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From: sashiko-bot@kernel.org
To: "Louis-Alexis Eyraud" <louisalexis.eyraud@collabora.com>
Cc: linux-clk@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v6 06/27] dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186
Date: Fri, 04 Sep 2026 16:11:41 +0000	[thread overview]
Message-ID: <20260904161141.F26661F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260904-mt8189-clocks-system-base-v6-6-5df247f56938@collabora.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [Medium] Missing required constraint for `#reset-cells` on reset providers.
--

commit 0550a18e08e9f8b8ca4e5f412e6e70a0779197aa
Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>

dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186
    
This commit regroups the MT8192 functional and system clock dt-bindings into
the MT8186 bindings to improve maintainability. It removes the MT8192-specific
binding files and adds their compatible strings to the shared MT8186 yaml
schemas.

> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
> index 199eac2034f22..41b8c61132e22 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
> @@ -35,6 +35,10 @@ properties:
>            - mediatek,mt8188-infracfg-ao
>            - mediatek,mt8188-pericfg-ao
>            - mediatek,mt8188-topckgen
> +          - mediatek,mt8192-apmixedsys
> +          - mediatek,mt8192-infracfg
> +          - mediatek,mt8192-pericfg
> +          - mediatek,mt8192-topckgen

[Severity: Medium]
This is a pre-existing issue, but should the reset-cells property be
explicitly required for compatible strings that act as reset providers,
such as mediatek,mt8192-infracfg?

Currently, the properties section in mt8186-sys-clock.yaml specifies
reset-cells as an optional property globally. Since mediatek,mt8192-infracfg
functions as a reset provider, is an allOf conditional block needed to make
reset-cells explicitly required for it?

Without this constraint, an incomplete device tree node omitting reset-cells
for a reset provider will incorrectly pass schema validation silently.

>        - const: syscon
>  
>    reg:

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com?part=6

  reply	other threads:[~2026-09-04 16:11 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-04 15:58 [PATCH v6 00/27] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 01/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 02/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 03/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 04/27] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 05/27] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 06/27] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-09-04 16:11   ` sashiko-bot [this message]
2026-09-04 15:58 ` [PATCH v6 07/27] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 08/27] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 09/27] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 10/27] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 11/27] clk: mediatek: pll: Factorise pll power on/off sequences Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 12/27] clk: mediatek: pll: Add PLL stabilization delay definition Louis-Alexis Eyraud
2026-09-04 16:11   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 13/27] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 14/27] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 15/27] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 16/27] clk: mediatek: Move fhctl_parse_dt call into mtk_clk_register_pllfhs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 17/27] clk: mediatek: pllfh: clear state data in mtk_clk_cleanup_pllfhs Louis-Alexis Eyraud
2026-09-04 16:18   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 18/27] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-09-04 16:17   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 19/27] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-09-04 16:20   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 20/27] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 21/27] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 22/27] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 23/27] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 24/27] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 25/27] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 26/27] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-09-04 16:28   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 27/27] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-09-04 16:27   ` sashiko-bot

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