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From: sashiko-bot@kernel.org
To: "Louis-Alexis Eyraud" <louisalexis.eyraud@collabora.com>
Cc: linux-clk@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v6 19/27] clk: mediatek: Add MT8189 topckgen clock support
Date: Fri, 04 Sep 2026 16:20:36 +0000	[thread overview]
Message-ID: <20260904162037.599B51F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260904-mt8189-clocks-system-base-v6-19-5df247f56938@collabora.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Use-after-free of `struct clk` and `struct clk_core` due to mismatched devres unregistration order during device remove or probe error.
--

commit c9fccf00f7b65c99304902dc0b7804332954da0c
Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>

clk: mediatek: Add MT8189 topckgen clock support

Add support for the MT8189 topckgen clock controller, which provides
muxes and dividers for clock selection in other IP blocks.

> diff --git a/drivers/clk/mediatek/clk-mt8189-topckgen.c b/drivers/clk/mediatek/clk-mt8189-topckgen.c
> new file mode 100644
> index 0000000000000..6ed7661119b82
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8189-topckgen.c
[ ... ]
> +/* Register mux notifier for MFG mux */
> +static int clk_mt8189_reg_mfg_mux_notifier(struct device *dev,
> +					   struct clk *clk)
> +{
> +	struct mtk_mux_nb *mfg_mux_nb;
> +
> +	mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
> +	if (!mfg_mux_nb)
> +		return -ENOMEM;
> +
> +	mfg_mux_nb->ops = &mtk_mux_clr_set_upd_ops;
> +	mfg_mux_nb->bypass_index = 0; /* Bypass to CLK_TOP_MFG_REF_SEL */
> +
> +	return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);

[Severity: High]
This isn't a bug introduced by this patch, but does this devres registration
cause a use-after-free during device removal?

The clock notifier is registered using devres via
devm_mtk_clk_mux_notifier_register(). During device unbind (e.g., via sysfs or
rmmod) or when probe fails after the notifier is registered, the driver
manually unregisters the clock via mtk_clk_unregister_muxes(), which
internally calls clk_hw_unregister(). This unconditionally frees the struct
clk instance.

Afterward, the devres framework automatically runs cleanup callbacks and
invokes devm_clk_notifier_release(). This devres callback passes the
already-freed clk pointer to clk_notifier_unregister(), which dereferences
the freed memory to access clk->core->notifier_count.

> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com?part=19

  reply	other threads:[~2026-09-04 16:20 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-04 15:58 [PATCH v6 00/27] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 01/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 02/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 03/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 04/27] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 05/27] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 06/27] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-09-04 16:11   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 07/27] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 08/27] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 09/27] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 10/27] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 11/27] clk: mediatek: pll: Factorise pll power on/off sequences Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 12/27] clk: mediatek: pll: Add PLL stabilization delay definition Louis-Alexis Eyraud
2026-09-04 16:11   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 13/27] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 14/27] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 15/27] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 16/27] clk: mediatek: Move fhctl_parse_dt call into mtk_clk_register_pllfhs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 17/27] clk: mediatek: pllfh: clear state data in mtk_clk_cleanup_pllfhs Louis-Alexis Eyraud
2026-09-04 16:18   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 18/27] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-09-04 16:17   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 19/27] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-09-04 16:20   ` sashiko-bot [this message]
2026-09-04 15:58 ` [PATCH v6 20/27] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 21/27] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 22/27] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 23/27] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 24/27] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 25/27] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 26/27] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-09-04 16:28   ` sashiko-bot
2026-09-04 15:58 ` [PATCH v6 27/27] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-09-04 16:27   ` sashiko-bot

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