* [PATCH v3 1/4] arm64: dts: renesas: r9a08g046: Add USB2.0 host/phy device nodes
2026-09-09 8:54 [PATCH v3 0/4] Add USB2.0 support for RZ/G3E Tommaso Merciai
@ 2026-09-09 8:54 ` Tommaso Merciai
2026-09-09 9:08 ` sashiko-bot
2026-09-09 8:54 ` [PATCH v3 2/4] arm64: dts: renesas: r9a08g046: Add USB2.0 function " Tommaso Merciai
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Tommaso Merciai @ 2026-09-09 8:54 UTC (permalink / raw)
To: tomm.merciai, prabhakar.mahadev-lad.rj
Cc: linux-renesas-soc, biju.das.jz, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree,
linux-kernel, Tommaso Merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
Add USB2.0 device nodes to the RZ/G3L (r9a08g046) SoC DTSI, covering
the USB PHY controller, OHCI/EHCI host controllers, and USB2 PHYs for
both ports.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v2->v3:
- No changes just rebased on top of next-20260908.
v1->v2:
- Cherry picked from "Add RZ/G3L USB2.0 host support" v7.
v7: https://lore.kernel.org/all/20260812141940.246223-7-biju.das.jz@bp.renesas.com/
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 104 +++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 608ba1f9e2f8..10123281c53c 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -1127,6 +1127,110 @@ queue3 {
};
};
+ phyrst: usbphy-ctrl@11e00000 {
+ compatible = "renesas,r9a08g046-usbphy-ctrl";
+ reg = <0 0x11e00000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>;
+ resets = <&cpg R9A08G046_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ status = "disabled";
+
+ regulators {
+ usb0_vbus_otg: vbus0 {
+ regulator-name = "usb0_vbus";
+ };
+
+ usb1_vbus_otg: vbus1 {
+ regulator-name = "usb1_vbus";
+ };
+ };
+ };
+
+ ohci0: usb@11e10000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11e10000 0 0x100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G046_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A08G046_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@11e90000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11e90000 0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G046_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A08G046_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@11e10100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11e10100 0 0x100>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G046_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A08G046_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@11e90100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11e90100 0 0x100>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G046_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A08G046_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@11e10200 {
+ compatible = "renesas,usb2-phy-r9a08g046";
+ reg = <0 0x11e10200 0 0x700>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G046_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A08G046_USB_U2H0_HRESETN>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@11e90200 {
+ compatible = "renesas,usb2-phy-r9a08g046";
+ reg = <0 0x11e90200 0 0x700>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G046_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A08G046_USB_U2H1_HRESETN>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
pcie: pcie@11e40000 {
reg = <0 0x11e40000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
--
2.54.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v3 1/4] arm64: dts: renesas: r9a08g046: Add USB2.0 host/phy device nodes
2026-09-09 8:54 ` [PATCH v3 1/4] arm64: dts: renesas: r9a08g046: Add USB2.0 host/phy device nodes Tommaso Merciai
@ 2026-09-09 9:08 ` sashiko-bot
0 siblings, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-09-09 9:08 UTC (permalink / raw)
To: Tommaso Merciai; +Cc: devicetree, conor+dt, robh, wsa+renesas
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The device tree node `phyrst: usbphy-ctrl@11e00000` specifies `compatible = "renesas,r9a08g046-usbphy-ctrl"` without any fallback compatible string, and this specific string is not supported by any reset driver in the tree.
- [High] The VBUS regulators are defined inside a generic `regulators` wrapper node, which violates the device tree schema and causes a probe failure in the regulator driver.
- [Low] The newly introduced compatible strings `renesas,r9a08g046-usbphy-ctrl` and `renesas,usb2-phy-r9a08g046` are not documented in the YAML device tree bindings.
--
commit 2f4cbd3dd8ab4b32e48fa0090fc979178999df6f
Author: Biju Das <biju.das.jz@bp.renesas.com>
arm64: dts: renesas: r9a08g046: Add USB2.0 host/phy device nodes
This commit adds USB2.0 device nodes to the RZ/G3L (r9a08g046) SoC DTSI.
It covers the USB PHY controller, OHCI/EHCI host controllers, and USB2 PHYs
for both ports.
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index 608ba1f9e2f8c..10123281c53c4 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -1127,6 +1127,110 @@ queue3 {
> };
> };
>
> + phyrst: usbphy-ctrl@11e00000 {
> + compatible = "renesas,r9a08g046-usbphy-ctrl";
[Severity: Low]
Is this compatible string documented? It appears to be missing from the schema
definition in Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml.
[Severity: High]
Does this node need a fallback compatible string?
Since "renesas,r9a08g046-usbphy-ctrl" is not supported by any reset driver in
the tree, the reset-rzg2l-usbphy-ctrl driver will not probe for this device node.
This will cause dependent USB nodes that request resets from this node to fail
with -EPROBE_DEFER indefinitely.
> + reg = <0 0x11e00000 0 0x10000>;
> + clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>;
> + resets = <&cpg R9A08G046_USB_PRESETN>;
> + power-domains = <&cpg>;
> + #reset-cells = <1>;
> + status = "disabled";
> +
> + regulators {
> + usb0_vbus_otg: vbus0 {
> + regulator-name = "usb0_vbus";
> + };
> +
> + usb1_vbus_otg: vbus1 {
> + regulator-name = "usb1_vbus";
> + };
> + };
[Severity: High]
Will the renesas-usb-vbus-regulator driver be able to probe this structure?
The driver expects exactly one child node named "regulator-vbus":
of_get_child_by_name(dev->parent->of_node, "regulator-vbus")
Because the child node is named "regulators", the driver will return -ENODEV.
The driver is also hardcoded to register only a single regulator instance via
enable_mask = BIT(0), so it cannot support the two separate regulators declared
here.
Additionally, does this violate the renesas,rzg2l-usbphy-ctrl.yaml device tree
schema which forbids the "regulators" wrapper?
> + };
> +
> + ohci0: usb@11e10000 {
> + compatible = "generic-ohci";
> + reg = <0 0x11e10000 0 0x100>;
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
> + <&cpg CPG_MOD R9A08G046_USB_U2H0_HCLK>;
> + resets = <&phyrst 0>,
[Severity: High]
Since this controller strictly depends on the "phyrst" reset controller, will it
fail to probe due to the missing fallback compatible string in the "phyrst"
node mentioned above?
[ ... ]
> + usb2_phy0: usb-phy@11e10200 {
> + compatible = "renesas,usb2-phy-r9a08g046";
[Severity: Low]
Is this compatible string documented? It appears to be missing from the schema
definition in Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml.
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1788943229.git.tommaso.merciai.xr@bp.renesas.com?part=1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 2/4] arm64: dts: renesas: r9a08g046: Add USB2.0 function device nodes
2026-09-09 8:54 [PATCH v3 0/4] Add USB2.0 support for RZ/G3E Tommaso Merciai
2026-09-09 8:54 ` [PATCH v3 1/4] arm64: dts: renesas: r9a08g046: Add USB2.0 host/phy device nodes Tommaso Merciai
@ 2026-09-09 8:54 ` Tommaso Merciai
2026-09-09 8:55 ` [PATCH v3 3/4] arm64: dts: renesas: r9a09g047: Add USB2.0 support Tommaso Merciai
2026-09-09 8:55 ` [PATCH v3 4/4] arm64: dts: renesas: r9a09g047e57-smarc: Enable " Tommaso Merciai
3 siblings, 0 replies; 6+ messages in thread
From: Tommaso Merciai @ 2026-09-09 8:54 UTC (permalink / raw)
To: tomm.merciai, prabhakar.mahadev-lad.rj
Cc: linux-renesas-soc, biju.das.jz, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree,
linux-kernel, Tommaso Merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
Add USB2.0 function device nodes to the RZ/G3L (r9a08g046) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v2->v3:
- No changes just rebased on top of next-20260908.
v1->v2:
- Cherry picked from "Add RZ/G3L USB2.0 host support" v7.
v7: https://lore.kernel.org/all/20260812141940.246223-8-biju.das.jz@bp.renesas.com/
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 38 ++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 10123281c53c..a2773e813dcd 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -1231,6 +1231,44 @@ usb2_phy1: usb-phy@11e90200 {
status = "disabled";
};
+ hsusb0: usb@11e30000 {
+ compatible = "renesas,usbhs-r9a08g046",
+ "renesas,rzg2l-usbhs";
+ reg = <0 0x11e30000 0 0x10000>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G046_USB_U2P0_EXR_CPUCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A08G046_USB_U2P0_EXL_SYSRST>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ hsusb1: usb@11eb0000 {
+ compatible = "renesas,usbhs-r9a08g046",
+ "renesas,rzg2l-usbhs";
+ reg = <0 0x11eb0000 0 0x10000>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_USB_PCLK>,
+ <&cpg CPG_MOD R9A08G046_USB_U2P1_EXR_CPUCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A08G046_USB_U2P1_EXL_SYSRST>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy1 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
pcie: pcie@11e40000 {
reg = <0 0x11e40000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
--
2.54.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 3/4] arm64: dts: renesas: r9a09g047: Add USB2.0 support
2026-09-09 8:54 [PATCH v3 0/4] Add USB2.0 support for RZ/G3E Tommaso Merciai
2026-09-09 8:54 ` [PATCH v3 1/4] arm64: dts: renesas: r9a08g046: Add USB2.0 host/phy device nodes Tommaso Merciai
2026-09-09 8:54 ` [PATCH v3 2/4] arm64: dts: renesas: r9a08g046: Add USB2.0 function " Tommaso Merciai
@ 2026-09-09 8:55 ` Tommaso Merciai
2026-09-09 8:55 ` [PATCH v3 4/4] arm64: dts: renesas: r9a09g047e57-smarc: Enable " Tommaso Merciai
3 siblings, 0 replies; 6+ messages in thread
From: Tommaso Merciai @ 2026-09-09 8:55 UTC (permalink / raw)
To: tomm.merciai, prabhakar.mahadev-lad.rj
Cc: linux-renesas-soc, biju.das.jz, Tommaso Merciai,
Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, linux-kernel
The Renesas RZ/G3E ("R9A09G047") SoC supports 1x channel with OTG/DRD
and 1x channel with host interface.
Add the EHCI, OHCI, USB2.0 PHY and reset control nodes for USB2.0 channels
in R9A09G047 SoC DTSI.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v2->v3:
- No changes just rebased on top of next-20260908.
v1->v2:
- No changes.
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 124 +++++++++++++++++++++
1 file changed, 124 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 72120e2abf8b..56ceedfb8ae8 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -1773,6 +1773,130 @@ usb3_phy: usb-phy@15870000 {
status = "disabled";
};
+ ohci0: usb@15800000 {
+ compatible = "generic-ohci";
+ reg = <0 0x15800000 0 0x100>;
+ interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
+ resets = <&usb20phyrst>, <&cpg 0xac>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@15810000 {
+ compatible = "generic-ohci";
+ reg = <0 0x15810000 0 0x100>;
+ interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
+ resets = <&usb21phyrst>, <&cpg 0xad>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@15800100 {
+ compatible = "generic-ehci";
+ reg = <0 0x15800100 0 0x100>;
+ interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
+ resets = <&usb20phyrst>, <&cpg 0xac>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@15810100 {
+ compatible = "generic-ehci";
+ reg = <0 0x15810100 0 0x100>;
+ interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
+ resets = <&usb21phyrst>, <&cpg 0xad>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@15800200 {
+ compatible = "renesas,usb2-phy-r9a09g047",
+ "renesas,usb2-phy-r9a09g057";
+ reg = <0 0x15800200 0 0x700>;
+ interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>,
+ <&cpg CPG_CORE R9A09G047_USB2_0_CLK_CORE0>;
+ clock-names = "fck", "usb_x1";
+ resets = <&usb20phyrst>, <&cpg 0xac>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ mux-states = <&usb20phyrst 1>;
+ status = "disabled";
+
+ usb2_phy0_vbus_otg: vbus-regulator {
+ regulator-name = "USB2PHY0-VBUS-OTG";
+ };
+ };
+
+ usb2_phy1: usb-phy@15810200 {
+ compatible = "renesas,usb2-phy-r9a09g047",
+ "renesas,usb2-phy-r9a09g057";
+ reg = <0 0x15810200 0 0x700>;
+ interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb4>,
+ <&cpg CPG_CORE R9A09G047_USB2_0_CLK_CORE1>;
+ clock-names = "fck", "usb_x1";
+ resets = <&usb21phyrst>, <&cpg 0xad>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ mux-states = <&usb21phyrst 0>;
+ status = "disabled";
+ };
+
+ hsusb0: usb@15820000 {
+ compatible = "renesas,usbhs-r9a09g047",
+ "renesas,rzg2l-usbhs";
+ reg = <0 0x15820000 0 0x10000>;
+ interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>;
+ resets = <&usb20phyrst>, <&cpg 0xae>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb20phyrst: reset-controller@15830000 {
+ compatible = "renesas,r9a09g047-usb2phy-reset",
+ "renesas,r9a09g057-usb2phy-reset";
+ reg = <0 0x15830000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb6>;
+ resets = <&cpg 0xaf>;
+ power-domains = <&cpg>;
+ #reset-cells = <0>;
+ #mux-state-cells = <1>;
+ status = "disabled";
+ };
+
+ usb21phyrst: reset-controller@15840000 {
+ compatible = "renesas,r9a09g047-usb2phy-reset",
+ "renesas,r9a09g057-usb2phy-reset";
+ reg = <0 0x15840000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb7>;
+ resets = <&cpg 0xaf>;
+ power-domains = <&cpg>;
+ #reset-cells = <0>;
+ #mux-state-cells = <1>;
+ status = "disabled";
+ };
+
sdhi0: mmc@15c00000 {
compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;
--
2.54.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 4/4] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB2.0 support
2026-09-09 8:54 [PATCH v3 0/4] Add USB2.0 support for RZ/G3E Tommaso Merciai
` (2 preceding siblings ...)
2026-09-09 8:55 ` [PATCH v3 3/4] arm64: dts: renesas: r9a09g047: Add USB2.0 support Tommaso Merciai
@ 2026-09-09 8:55 ` Tommaso Merciai
3 siblings, 0 replies; 6+ messages in thread
From: Tommaso Merciai @ 2026-09-09 8:55 UTC (permalink / raw)
To: tomm.merciai, prabhakar.mahadev-lad.rj
Cc: linux-renesas-soc, biju.das.jz, Tommaso Merciai,
Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, linux-kernel
Enable USB2.0 support on the RZ/G3E EVK board. The USB1B_1A_HOST and
USB5_4_HOST connectors support host operation only, while USB0_OTG
supports both host and peripheral operation.
renesas-smarc2.dtsi is shared by all boards based on the RZ SMARC
Carrier II Board. USB2.0 is not yet supported on the RZ/G3L SMARC
EVK, so disable the common USB2.0 nodes in its board DTS until proper
support is added.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v2->v3:
- No changes just rebased on top of next-20260908.
v1->v2:
- Disabled RZ/G3L common nodes from r9a08g046l48-smarc.dts in this way
we can drop placeholder patch.
- Update commit body.
- Improved usb20_pins, usb21_pins comments.
.../boot/dts/renesas/r9a08g046l48-smarc.dts | 20 +++++++++
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 45 +++++++++++++++++++
.../boot/dts/renesas/renesas-smarc2.dtsi | 25 +++++++++++
3 files changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
index 5289efd1a430..ccd6e6394532 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
@@ -71,6 +71,18 @@ codec_dai: codec {
#endif
};
+&ehci0 {
+ status = "disabled";
+};
+
+&ehci1 {
+ status = "disabled";
+};
+
+&hsusb0 {
+ status = "disabled";
+};
+
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
@@ -122,6 +134,14 @@ &keys {
#endif
};
+&ohci0 {
+ status = "disabled";
+};
+
+&ohci1 {
+ status = "disabled";
+};
+
&pinctrl {
audio_clk_pins: audio-clock {
pinmux = <RZG3L_PORT_PINMUX(H, 4, 6)>, /* AUDIO_CLK_B */
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 469a6282b2a3..36482357c2fc 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -298,6 +298,28 @@ sd1-data {
};
};
+ usb20_pins: usb20 {
+ ovc {
+ pinmux = <RZG3E_PORT_PINMUX(0, 0, 12)>; /* USB20_OVRCURN */
+ bias-pull-up;
+ };
+
+ vbus {
+ pinmux = <RZG3E_PORT_PINMUX(0, 1, 12)>; /* USB20_VBUSEN */
+ };
+ };
+
+ usb21_pins: usb21 {
+ ovc {
+ pinmux = <RZG3E_PORT_PINMUX(G, 6, 12)>; /* USB21_OVRCURN */
+ bias-pull-up;
+ };
+
+ vbus {
+ pinmux = <RZG3E_PORT_PINMUX(K, 3, 12)>; /* USB21_VBUSEN */
+ };
+ };
+
usb3_pins: usb3 {
pinmux = <RZG3E_PORT_PINMUX(4, 1, 12)>, /* USB30_VBUSEN */
<RZG3E_PORT_PINMUX(4, 0, 12)>; /* USB30_OVRCURN */
@@ -394,6 +416,29 @@ &ssi4 {
shared-pin;
};
+&usb20phyrst {
+ status = "okay";
+};
+
+&usb21phyrst {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb20_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&usb2_phy0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb21_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
&usb3_phy {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index 696a933af808..e07fd9396adb 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -91,11 +91,36 @@ &canfd {
status = "okay";
};
+&ehci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ehci1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&hsusb0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
clock-frequency = <400000>;
};
+&ohci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ohci1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&pcie {
status = "okay";
};
--
2.54.0
^ permalink raw reply related [flat|nested] 6+ messages in thread