Re: [PATCH v3 10/13] arm64: dts: qcom: lemans: Add Iris context bank subnodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing IOMMU configuration for child context bank devices causes SMMU translation faults
--

commit a2c4ab829f603d5afbc86327c3483e445b4cefed
Author: Vikash Garodia <vikash.garodia@oss.qualcomm.com>

arm64: dts: qcom: lemans: Add Iris context bank subnodes

This commit moves the iommus property from the parent video-codec node
to specific subnodes (non-pixel and pixel) to restrict the addressable
range for the non-pixel stream. The intent is to prevent unhandled SMMU
page faults by ensuring allocations avoid the low 600MB of IOVA space.

> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 695eae1b72569..afed5e43b4fcd 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
[ ... ]
> @@ -4962,12 +4962,23 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
>  			resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
>  			reset-names = "bus";
>  
> -			iommus = <&apps_smmu 0x0880 0x0400>,
> -				 <&apps_smmu 0x0887 0x0400>;
>  			dma-coherent;
>  
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			dma-ranges = <0x0 0x0 0x0 0xe0000000>;
>  
>  			status = "disabled";
>  
> +			non-pixel {
> +				iommus = <&apps_smmu 0x0880 0x0400>;
> +				iommu-ranges = <0x25800000 0xba800000>;
> +			};
> +
> +			pixel {
> +				iommus = <&apps_smmu 0x0887 0x0400>;
> +			};

[Severity: High]
Because these subnodes lack a compatible string, do they ever bind to a
driver? 

If they don't bind, the driver core's really_probe() is skipped, meaning
platform_dma_configure() and of_dma_configure() are not executed
automatically.

In the iris driver code, iris_create_cb_dev() instantiates these subnodes
dynamically via platform_device_register_full():

drivers/media/platform/qcom/iris/iris_probe.c:iris_create_cb_dev() {
    ...
    pdev = platform_device_register_full(&plat_dev_info);
    of_node_put(child_of_node);
    if (IS_ERR(pdev))
        return ERR_CAST(pdev);
    ...
}

Unlike the venus driver which explicitly calls of_dma_configure() for
driverless firmware nodes, the iris driver appears to omit explicit IOMMU
configuration on these newly created devices. 

When the driver later allocates DMA buffers using core->np_dev or core->p_dev,
will those allocations bypass the IOMMU due to the missing iommu_fwspec
attachment?

Could this result in the DMA memory being allocated using direct physical
addresses instead of IOVAs, triggering the very SMMU translation faults this
patch aims to fix?

> +
>  			iris_opp_table: opp-table {
>  				compatible = "operating-points-v2";
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260909-vpu_iommu_iova_handling-v3-0-2fe43ae45495@oss.qualcomm.com?part=10