Re: [PATCH v3 13/13] arm64: dts: qcom: sm8750: Add Iris context bank subnodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Moving the `iommus` property to subnodes breaks IOMMU configuration for the VPU because the `iris` driver does not configure DMA for these child devices.
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commit 2a638b0a96fbbd027cf960b36f77ad140f56417d
Author: Vikash Garodia <vikash.garodia@oss.qualcomm.com>

arm64: dts: qcom: sm8750: Add Iris context bank subnodes

This patch adds non-pixel and pixel subnodes to the Iris video-codec
node to restrict address ranges for specific VPU streams. It removes
the single iommus property from the main node to resolve unhandled
SMMU page faults caused by non-pixel buffers falling below the 600MB
boundary.

> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index eb3a6990ec30b..206ac22cab2c0 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -3026,8 +3026,6 @@ iris: video-codec@aa00000 {
>  				      "vcodec0_core_freerun";
>  
>  			dma-coherent;
> -			iommus = <&apps_smmu 0x1940 0>,
> -				 <&apps_smmu 0x1947 0>;
>  
>  			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
[ ... ]
> @@ -3067,6 +3069,15 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
>  			 */
>  			status = "disabled";
>  
> +			non-pixel {
> +				iommus = <&apps_smmu 0x1940 0x0>;
> +				iommu-ranges = <0x25800000 0xba800000>;
> +			};
> +
> +			pixel {
> +				iommus = <&apps_smmu 0x1947 0x0>;
> +			};
> +
>  			iris_opp_table: opp-table {

[Severity: High]
Does moving the iommus property to these subnodes break IOMMU configuration
for the VPU?

Since these subnodes lack compatible strings, they will not bind to a
driver. Looking at iris_create_cb_dev() in the driver, it creates
platform devices for the child nodes but doesn't call of_dma_configure()
or attach an IOMMU domain:

drivers/media/platform/qcom/iris/iris_probe.c:iris_create_cb_dev() {
        ...
        pdev = platform_device_register_full(&plat_dev_info);
        of_node_put(child_of_node);
        if (IS_ERR(pdev))
                return ERR_CAST(pdev);

        dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
        dma_set_seg_boundary(&pdev->dev, DMA_BIT_MASK(32));

        return &pdev->dev;
}

Because no driver binds to these sub-devices, the driver core never calls
really_probe() and skips platform_dma_configure(). Since the iris driver
does not manually configure DMA either, does this leave the sub-devices
without IOMMU configuration?

This could cause DMA allocations to bypass the IOMMU and yield raw physical
addresses instead of IOVAs. When the VPU attempts to access these addresses,
the SMMU might generate context faults.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260909-vpu_iommu_iova_handling-v3-0-2fe43ae45495@oss.qualcomm.com?part=13