[PATCH v6 0/4] Add USB3.1 support for Agilex5

[PATCH v6 0/4] Add USB3.1 support for Agilex5

[Adrian Ng Ho Yin]

Agilex5 integrates a Synopsys DesignWare USB3 controller via a
SoC-specific wrapper that requires dedicated clock, reset, PHY, and
optional SMMU integration. The USB DMA path on the interconnect is
limited to a 40-bit address width.

This series adds a device tree binding for the Agilex5 DWC3 controller and
introduces the corresponding USB3.1 node in the Agilex5 SoC and SoCDK
device trees. The controller is placed under a simple-bus with a 40-bit
dma-ranges window so the DMA/IOMMU stack respects the interconnect address
width when SMMU is enabled. As the SoCDK only exposes the USB3.1 interface,
the unused USB0 node is removed.

On this SoC the DWC3 "ref" and "suspend" inputs share the same hardware
clock source, so both clock phandles use the already published
AGILEX5_USB31_SUSPEND_CLK ID (no new clock binding ID).

Finally, the Agilex5 compatible string is added to the dwc3 generic
platform driver so the controller can probe through that glue driver.

Merging:
- Patches 1 and 4 (dt-bindings + dwc3-generic-plat): USB tree
- Patches 2 and 3 (arm64 dts): SoC / arm64 dts tree (or taken with the
  USB series if preferred, with an appropriate Ack)
---
changelog:
v5->v6:
* Make snps,dis_u2_susphy_quirk and snps,dis_u3_susphy_quirk required.
  There is only one DWC3 instance on Agilex5 and both quirks are used
  on that node.

v5 patch link:
https://lore.kernel.org/all/cover.1788757821.git.adrian.ho.yin.ng@altera.com/

v4->v5:
* Binding: replace unevaluatedProperties: false with additionalProperties:
  false, and allow only the extra DWC3 properties used on this SoC via
  "foo: true" (dr_mode, maximum-speed, snps,dis_u2_susphy_quirk,
  snps,dis_u3_susphy_quirk).

v4 patch link:
https://lore.kernel.org/all/cover.1788503540.git.adrian.ho.yin.ng@altera.com/

v3->v4:
* Drop dt-bindings/clock and clk driver patches; do not extend the
  published Agilex5 clock binding. Reuse AGILEX5_USB31_SUSPEND_CLK for
  both "ref" and "suspend" clock inputs.
* Fix usb31_bus dma-ranges cell layout (sashiko comment): use
  #address-cells = <2> and a Stingray-style 40-bit dma-ranges window
  instead of a 32-bit child address space with a truncated 1 TiB size.
* Update altr,agilex5-dwc3.yaml per review: drop obvious reg/resets
  descriptions, order clock-names as bus_early/ref/suspend (matching
  snps,dwc3.yaml), and rename reset-names to core/ecc.
* Limit the series to USB binding, DTS, and dwc3-generic-plat (no clk
  subsystem patches in the same series).
v3 patch link:
https://lore.kernel.org/all/cover.1786518803.git.adrian.ho.yin.ng@altera.com/

v2->v3:
* Add the missing USB3.1 reference clock ID and register usb31_ref_clk
  as a fixed-factor clock in the Agilex5 clock driver.
* Drop dma_addressable_bits core/glue changes; describe the 40-bit DMA
  limit in DT with dma-ranges instead.
* Wrap the USB3.1 node in a simple-bus with a 40-bit dma-ranges window.
* Keep Agilex5 support in dwc3-generic-plat as a compatible match only
  (no platform-specific DMA mask override).

v2 patch link:
https://lore.kernel.org/all/cover.1765249127.git.adrianhoyin.ng@altera.com/

v1->v2:
* Update new binding name to match compatible.
* Update binding to use single node instead of parent child node structure.
* Update binding according to comments from maintainer.
* Split USB3 and USB2 changes in dts into separate commits.
* Update to use flattened model and use dwc3-generic-plat driver instead of
  dwc3-of-simple driver.
* Add dma_addressable_bits as a dwc3 property which is set by the glue driver
  which is used to configure the dma mask in the core driver.

v1 patch link:
https://lore.kernel.org/all/cover.1762839776.git.adrianhoyin.ng@altera.com/
---

Adrian Ng Ho Yin (4):
  dt-bindings: usb: add Altera Agilex5 DWC3 controller
  arm64: dts: intel: agilex5: add USB3.1 controller node
  arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK
  usb: dwc3: add Altera Agilex5 support to generic platform driver

 .../bindings/usb/altr,agilex5-dwc3.yaml       | 112 ++++++++++++++++++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  35 ++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |   4 +-
 drivers/usb/dwc3/dwc3-generic-plat.c          |   1 +
 4 files changed, 150 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml

-- 
2.49.GIT

[PATCH v6 1/4] dt-bindings: usb: add Altera Agilex5 DWC3 controller

[Adrian Ng Ho Yin]

Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3
USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets,
PHYs, and optional IOMMU support.

Clock names follow the snps,dwc3.yaml example order (bus_early, ref,
suspend). Reset names use core/ecc. On this SoC ref and suspend are the
same hardware source, so the example reuses AGILEX5_USB31_SUSPEND_CLK.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 .../bindings/usb/altr,agilex5-dwc3.yaml       | 112 ++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml

diff --git a/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
new file mode 100644
index 000000000000..610ddcb632e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera Agilex5 DWC3 USB SoC Controller
+
+maintainers:
+  - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
+
+description:
+  The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3)
+  controller that supports host, device and DRD modes.
+
+allOf:
+  - $ref: snps,dwc3-common.yaml#
+
+properties:
+  compatible:
+    const: altr,agilex5-dwc3
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Master/Core bus clock
+      - description: Controller reference clock
+      - description: Controller suspend clock
+
+  clock-names:
+    items:
+      - const: bus_early
+      - const: ref
+      - const: suspend
+
+  interrupts:
+    maxItems: 1
+
+  phys:
+    minItems: 2
+    maxItems: 2
+
+  phy-names:
+    items:
+      - const: usb2-phy
+      - const: usb3-phy
+
+  iommus:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: DWC3 core reset
+      - description: DWC3 ECC reset
+
+  reset-names:
+    items:
+      - const: core
+      - const: ecc
+
+  dr_mode: true
+
+  maximum-speed: true
+
+  snps,dis_u2_susphy_quirk: true
+
+  snps,dis_u3_susphy_quirk: true
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - phys
+  - phy-names
+  - resets
+  - reset-names
+  - snps,dis_u2_susphy_quirk
+  - snps,dis_u3_susphy_quirk
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/reset/altr,rst-mgr-s10.h>
+    #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
+
+    soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        usb@11000000 {
+            compatible = "altr,agilex5-dwc3";
+            reg = <0x11000000 0x100000>;
+            interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>,
+                     <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
+                     <&clkmgr AGILEX5_USB31_SUSPEND_CLK>;
+            clock-names = "bus_early", "ref", "suspend";
+            phys = <&usbphy0>, <&usbphy1>;
+            phy-names = "usb2-phy", "usb3-phy";
+            resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+            reset-names = "core", "ecc";
+            iommus = <&smmu 7>;
+            snps,dis_u2_susphy_quirk;
+            snps,dis_u3_susphy_quirk;
+        };
+    };
-- 
2.49.GIT

[PATCH v6 2/4] arm64: dts: intel: agilex5: add USB3.1 controller node

[Adrian Ng Ho Yin]

Add a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC.
Place it under a simple-bus with a 40-bit dma-ranges window (#address-cells
= 2) to match the USB DMA address width of the interconnect. Enable it in
host mode on the SoCDK board.

ref and suspend both use AGILEX5_USB31_SUSPEND_CLK because they share the
same hardware clock source on this SoC.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 35 +++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  5 +++
 2 files changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index f54767d1526e..523f722a2a64 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -493,6 +493,41 @@ usb0: usb@10b00000 {
 			status = "disabled";
 		};
 
+		usb31_bus: usb-bus@11000000 {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x11000000 0x0 0x100000>;
+			/*
+			 * USB interconnect DMA is limited to 40-bit addresses
+			 * (1 TiB window from 0).
+			 */
+			dma-ranges = <0x0 0x0 0x0 0x100 0x0>;
+
+			usb31: usb@0 {
+				compatible = "altr,agilex5-dwc3";
+				reg = <0x0 0x0 0x0 0x100000>;
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				/*
+				 * ref and suspend share the same hardware
+				 * source; reuse the published suspend clock ID.
+				 */
+				clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>,
+					 <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
+					 <&clkmgr AGILEX5_USB31_SUSPEND_CLK>;
+				clock-names = "bus_early", "ref", "suspend";
+				resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+				reset-names = "core", "ecc";
+				iommus = <&smmu 7>;
+				phys = <&usbphy0>, <&usbphy0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				maximum-speed = "super-speed";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				status = "disabled";
+			};
+		};
+
 		watchdog0: watchdog@10d00200 {
 			compatible = "snps,dw-wdt";
 			reg = <0x10d00200 0x100>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 1e9b87d96765..aa9294494421 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -109,6 +109,11 @@ &usb0 {
 	disable-over-current;
 };
 
+&usb31 {
+	dr_mode = "host";
+	status = "okay";
+};
+
 &watchdog0 {
 	status = "okay";
 };
-- 
2.49.GIT

[PATCH v6 3/4] arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK

[Adrian Ng Ho Yin]

The Agilex5 SoCDK daughter card only provides a USB3.1 interface (USB1).
USB0 is not connected or used on this board. Remove the USB0 node to avoid
unnecessary initialization and potential resource conflicts.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index aa9294494421..c48867cc3043 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -104,11 +104,6 @@ &uart0 {
 	status = "okay";
 };
 
-&usb0 {
-	status = "okay";
-	disable-over-current;
-};
-
 &usb31 {
 	dr_mode = "host";
 	status = "okay";
-- 
2.49.GIT

[PATCH v6 4/4] usb: dwc3: add Altera Agilex5 support to generic platform driver

[Adrian Ng Ho Yin]

Add the "altr,agilex5-dwc3" compatible string to dwc3-generic-plat so the
Agilex5 USB3.1 DWC3 controller can probe through the generic DWC3 platform
glue.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
---
 drivers/usb/dwc3/dwc3-generic-plat.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
index ca69ac0eb07c..8781d7ec6b9e 100644
--- a/drivers/usb/dwc3/dwc3-generic-plat.c
+++ b/drivers/usb/dwc3/dwc3-generic-plat.c
@@ -232,6 +232,7 @@ static const struct dwc3_generic_config eic7700_dwc3 =  {
 };
 
 static const struct of_device_id dwc3_generic_of_match[] = {
+	{ .compatible = "altr,agilex5-dwc3", },
 	{ .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3},
 	{ .compatible = "spacemit,k3-dwc3", },
 	{ .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3},
-- 
2.49.GIT

Re: [PATCH v6 1/4] dt-bindings: usb: add Altera Agilex5 DWC3 controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The binding uses `additionalProperties: false` alongside an `allOf: - $ref` to a common schema, which breaks inheritance of common properties.
--

commit 6228c1d4fc3d3337f401a374921c27cd7ee4aba2
Author: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

dt-bindings: usb: add Altera Agilex5 DWC3 controller

Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3
USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets,
PHYs, and optional IOMMU support.

> diff --git a/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> new file mode 100644
> index 0000000000000..610ddcb632e28
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml

[ ... ]

> +allOf:
> +  - $ref: snps,dwc3-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: altr,agilex5-dwc3

[ ... ]

> +  reset-names:
> +    items:
> +      - const: core
> +      - const: ecc
> +
> +  dr_mode: true
> +
> +  maximum-speed: true
> +
> +  snps,dis_u2_susphy_quirk: true
> +
> +  snps,dis_u3_susphy_quirk: true

[Severity: Medium]
Are these properties redundantly declared as true to work around the
limitations of additionalProperties being set to false?

[ ... ]

> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - phys
> +  - phy-names
> +  - resets
> +  - reset-names
> +  - snps,dis_u2_susphy_quirk
> +  - snps,dis_u3_susphy_quirk
> +
> +additionalProperties: false

[Severity: Medium]
Does this strict constraint incorrectly reject inherited properties from the
DWC3 common schema?

Since this binding uses an allOf inclusion for snps,dwc3-common.yaml, using
additionalProperties: false breaks the inheritance of common properties. Valid
common properties from generic DWC3 or USB schemas will be wrongly rejected by
dtbs_check unless explicitly duplicated in this file.

Should this be unevaluatedProperties: false instead, which would allow
evaluating properties from the included common schema and remove the need to
redundantly declare the inherited properties above?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1788886615.git.adrian.ho.yin.ng@altera.com?part=1

Re: [PATCH v6 2/4] arm64: dts: intel: agilex5: add USB3.1 controller node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The `usb31_bus` node defines a 1 TiB (40-bit) `dma-ranges` window that structurally overflows its parent bus (`soc`) which only has a 32-bit address space.
- [Medium] The `phys` property points to a `usb-nop-xceiv` node, but this is rejected by the generic PHY framework and ignored by the DWC3 legacy PHY fallback, making the property dead code.
--

commit ea5388a5a6d3ab6b2ff68927da6ac8bb6e1fe941
Author: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

arm64: dts: intel: agilex5: add USB3.1 controller node

This commit adds a DTS node for the Synopsys DWC3 USB3.1 controller on the
Agilex5 SoC. It places it under a simple-bus with a 40-bit dma-ranges window
to match the interconnect's USB DMA address width. The controller is also
enabled in host mode on the SoCDK board.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index f54767d1526e1..523f722a2a642 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi

[ ... ]

> @@ -493,6 +493,41 @@ usb0: usb@10b00000 {
>  			status = "disabled";
>  		};
>  
> +		usb31_bus: usb-bus@11000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges = <0x0 0x0 0x11000000 0x0 0x100000>;
> +			/*
> +			 * USB interconnect DMA is limited to 40-bit addresses
> +			 * (1 TiB window from 0).
> +			 */
> +			dma-ranges = <0x0 0x0 0x0 0x100 0x0>;

[Severity: High]
Does this 40-bit dma-ranges window structurally overflow its parent bus?

The usb31_bus node is defined as a child of the soc node, which only has
a 32-bit address space (#address-cells = <1>). Translating a 1 TiB DMA window
into a 32-bit parent bus mathematically overflows the parent's addressability.

The kernel's OF DMA parser evaluates this window against the parent's 32-bit
addressability and truncates DMA addresses to the parent bus size. Any DMA
address beyond 4 GB cannot be represented or routed correctly.

This breaks 64-bit DMA for the USB controller, which can cause memory
corruption or IOMMU faults if system memory > 4GB is used for DMA buffers.

> +
> +			usb31: usb@0 {
> +				compatible = "altr,agilex5-dwc3";
> +				reg = <0x0 0x0 0x0 0x100000>;
> +				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +				/*
> +				 * ref and suspend share the same hardware
> +				 * source; reuse the published suspend clock ID.
> +				 */
> +				clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>,
> +					 <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
> +					 <&clkmgr AGILEX5_USB31_SUSPEND_CLK>;
> +				clock-names = "bus_early", "ref", "suspend";
> +				resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
> +				reset-names = "core", "ecc";
> +				iommus = <&smmu 7>;
> +				phys = <&usbphy0>, <&usbphy0>;
> +				phy-names = "usb2-phy", "usb3-phy";

[Severity: Medium]
Will this phys property actually be parsed, or is it treated as dead code?

The usbphy0 node has compatible = "usb-nop-xceiv". The generic PHY subsystem
in drivers/phy/phy-core.c explicitly rejects usb-nop-xceiv and returns -ENODEV.
The DWC3 core driver dwc3_core_get_phy() handles this error by falling back to
the legacy USB PHY subsystem.

However, the legacy subsystem explicitly expects the legacy property name
usb-phy. Since this node uses the generic phys property name, the legacy
fallback also fails.

The DWC3 driver ignores the resulting -ENODEV error and silently proceeds
without a PHY.

> +				maximum-speed = "super-speed";
> +				snps,dis_u2_susphy_quirk;
> +				snps,dis_u3_susphy_quirk;
> +				status = "disabled";
> +			};
> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1788886615.git.adrian.ho.yin.ng@altera.com?part=2

Re: [PATCH v6 1/4] dt-bindings: usb: add Altera Agilex5 DWC3 controller

[Krzysztof Kozlowski]

On Wed, Sep 09, 2026 at 01:04:37AM +0800, Adrian Ng Ho Yin wrote:
> Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3
> USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets,
> PHYs, and optional IOMMU support.
> 
> Clock names follow the snps,dwc3.yaml example order (bus_early, ref,
> suspend). Reset names use core/ecc. On this SoC ref and suspend are the
> same hardware source, so the example reuses AGILEX5_USB31_SUSPEND_CLK.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> ---
>  .../bindings/usb/altr,agilex5-dwc3.yaml       | 112 ++++++++++++++++++
>  1 file changed, 112 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH v6 2/4] arm64: dts: intel: agilex5: add USB3.1 controller node

[Krzysztof Kozlowski]

On Wed, Sep 09, 2026 at 01:04:38AM +0800, Adrian Ng Ho Yin wrote:
> Add a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC.
> Place it under a simple-bus with a 40-bit dma-ranges window (#address-cells
> = 2) to match the USB DMA address width of the interconnect. Enable it in
> host mode on the SoCDK board.
> 
> ref and suspend both use AGILEX5_USB31_SUSPEND_CLK because they share the
> same hardware clock source on this SoC.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Same comments apply. From 5 revisions ago!

Best regards,
Krzysztof

Re: [PATCH v6 3/4] arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK

[Krzysztof Kozlowski]

On Wed, Sep 09, 2026 at 01:04:39AM +0800, Adrian Ng Ho Yin wrote:
> The Agilex5 SoCDK daughter card only provides a USB3.1 interface (USB1).
> USB0 is not connected or used on this board. Remove the USB0 node to avoid
> unnecessary initialization and potential resource conflicts.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Same comments.

Respond to the feedback or implement it.

NAK

Best regards,
Krzysztof

Re: [PATCH v6 2/4] arm64: dts: intel: agilex5: add USB3.1 controller node

[NG, ADRIAN HO YIN]

On 9/11/2026 3:21 PM, Krzysztof Kozlowski wrote:
> On Wed, Sep 09, 2026 at 01:04:38AM +0800, Adrian Ng Ho Yin wrote:
>> Add a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC.
>> Place it under a simple-bus with a 40-bit dma-ranges window (#address-cells
>> = 2) to match the USB DMA address width of the interconnect. Enable it in
>> host mode on the SoCDK board.
>>
>> ref and suspend both use AGILEX5_USB31_SUSPEND_CLK because they share the
>> same hardware clock source on this SoC.
>>
>> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> Same comments apply. From 5 revisions ago!

Hi Krzysztof

You are right! sorry for repeating this across revisions.

v1 feedback was that DTS must not be mixed into a USB-targeted series.
Splitting the USB3 add and USB0 removal into separate commits inside the
same USB series did not address that; both are still SoC/arm64 DTS and
belong outside the USB tree.

I will send v7 as two postings:
1) USB only: dt-bindings + dwc3-generic-plat
2) DTS only: Agilex5 USB3.1 node + SoCDK enable, and USB0 cleanup

Thanks for the patience.

Best regards,
Adrian
>
> Best regards,
> Krzysztof

Re: [PATCH v6 3/4] arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK

[NG, ADRIAN HO YIN]

On 9/11/2026 3:22 PM, Krzysztof Kozlowski wrote:
> On Wed, Sep 09, 2026 at 01:04:39AM +0800, Adrian Ng Ho Yin wrote:
>> The Agilex5 SoCDK daughter card only provides a USB3.1 interface (USB1).
>> USB0 is not connected or used on this board. Remove the USB0 node to avoid
>> unnecessary initialization and potential resource conflicts.
>>
>> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> Same comments.
>
> Respond to the feedback or implement it.
>
> NAK
Acknowledged — dropping this from the USB series.

USB0 removal stays with the separate arm64 DTS posting (SoC/board
enablement), not with the USB bindings/driver patches.

Best regards,
Adrian
>
> Best regards,
> Krzysztof

[PATCH v7 0/2] usb: dwc3: add Altera Agilex5 DWC3 support

[adrian.ho.yin.ng]

From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Agilex5 integrates a Synopsys DesignWare USB3 controller that is probed
through dwc3-generic-plat. This series adds:

1. dt-bindings for compatible "altr,agilex5-dwc3"
2. matching entry in dwc3-generic-plat

arm64 DTS enablement is posted separately.

---
changelog:
v6->v7:
* Drop arm64 DTS patches from this series (DTS must not be mixed into a
  USB-targeted series). DTS is reposted separately.

v6 patch link:
https://lore.kernel.org/all/cover.1788886615.git.adrian.ho.yin.ng@altera.com/

v5->v6:
* Make snps,dis_u2_susphy_quirk and snps,dis_u3_susphy_quirk required.

v5 patch link:
https://lore.kernel.org/all/cover.1788757821.git.adrian.ho.yin.ng@altera.com/

v4->v5:
* Binding: replace unevaluatedProperties: false with additionalProperties:
  false, and allow only the extra DWC3 properties used on this SoC via
  "foo: true".

v4 patch link:
https://lore.kernel.org/all/cover.1788503540.git.adrian.ho.yin.ng@altera.com/

v3->v4:
* Drop clk binding/driver patches; reuse AGILEX5_USB31_SUSPEND_CLK for
  both "ref" and "suspend".
* Update altr,agilex5-dwc3.yaml per review.
* Limit the series to USB binding, DTS, and dwc3-generic-plat.

v3 patch link:
https://lore.kernel.org/all/cover.1786518803.git.adrian.ho.yin.ng@altera.com/

v2->v3:
* Drop dma_addressable_bits; describe 40-bit DMA limit with dma-ranges.
* Keep Agilex5 support in dwc3-generic-plat as a compatible match only.

v2 patch link:
https://lore.kernel.org/all/cover.1765249127.git.adrianhoyin.ng@altera.com/

v1->v2:
* Flattened model + dwc3-generic-plat instead of dwc3-of-simple.
* Split USB3 add vs USB0 disable in DTS (still wrongly kept in USB
  series until v7).

v1 patch link:
https://lore.kernel.org/all/cover.1762839776.git.adrianhoyin.ng@altera.com/
---

Adrian Ng Ho Yin (2):
  dt-bindings: usb: add Altera Agilex5 DWC3 controller
  usb: dwc3: add Altera Agilex5 support to generic platform driver

 .../bindings/usb/altr,agilex5-dwc3.yaml       | 112 ++++++++++++++++++
 drivers/usb/dwc3/dwc3-generic-plat.c          |   1 +
 2 files changed, 113 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml


base-commit: bc35965f6940a9bf834d54187b6088b8eb09206d
-- 
2.49.GIT

[PATCH v7 1/2] dt-bindings: usb: add Altera Agilex5 DWC3 controller

[adrian.ho.yin.ng]

From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3
USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets,
PHYs, and optional IOMMU support.

Clock names follow the snps,dwc3.yaml example order (bus_early, ref,
suspend). Reset names use core/ecc. On this SoC ref and suspend are the
same hardware source, so the example reuses AGILEX5_USB31_SUSPEND_CLK.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
 .../bindings/usb/altr,agilex5-dwc3.yaml       | 112 ++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml

diff --git a/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
new file mode 100644
index 000000000000..610ddcb632e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera Agilex5 DWC3 USB SoC Controller
+
+maintainers:
+  - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
+
+description:
+  The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3)
+  controller that supports host, device and DRD modes.
+
+allOf:
+  - $ref: snps,dwc3-common.yaml#
+
+properties:
+  compatible:
+    const: altr,agilex5-dwc3
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Master/Core bus clock
+      - description: Controller reference clock
+      - description: Controller suspend clock
+
+  clock-names:
+    items:
+      - const: bus_early
+      - const: ref
+      - const: suspend
+
+  interrupts:
+    maxItems: 1
+
+  phys:
+    minItems: 2
+    maxItems: 2
+
+  phy-names:
+    items:
+      - const: usb2-phy
+      - const: usb3-phy
+
+  iommus:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: DWC3 core reset
+      - description: DWC3 ECC reset
+
+  reset-names:
+    items:
+      - const: core
+      - const: ecc
+
+  dr_mode: true
+
+  maximum-speed: true
+
+  snps,dis_u2_susphy_quirk: true
+
+  snps,dis_u3_susphy_quirk: true
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - phys
+  - phy-names
+  - resets
+  - reset-names
+  - snps,dis_u2_susphy_quirk
+  - snps,dis_u3_susphy_quirk
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/reset/altr,rst-mgr-s10.h>
+    #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
+
+    soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        usb@11000000 {
+            compatible = "altr,agilex5-dwc3";
+            reg = <0x11000000 0x100000>;
+            interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>,
+                     <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
+                     <&clkmgr AGILEX5_USB31_SUSPEND_CLK>;
+            clock-names = "bus_early", "ref", "suspend";
+            phys = <&usbphy0>, <&usbphy1>;
+            phy-names = "usb2-phy", "usb3-phy";
+            resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+            reset-names = "core", "ecc";
+            iommus = <&smmu 7>;
+            snps,dis_u2_susphy_quirk;
+            snps,dis_u3_susphy_quirk;
+        };
+    };
-- 
2.49.GIT

[PATCH v7 2/2] usb: dwc3: add Altera Agilex5 support to generic platform driver

[adrian.ho.yin.ng]

From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Add the "altr,agilex5-dwc3" compatible string to dwc3-generic-plat so the
Agilex5 USB3.1 DWC3 controller can probe through the generic DWC3 platform
glue.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
---
 drivers/usb/dwc3/dwc3-generic-plat.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
index ca69ac0eb07c..8781d7ec6b9e 100644
--- a/drivers/usb/dwc3/dwc3-generic-plat.c
+++ b/drivers/usb/dwc3/dwc3-generic-plat.c
@@ -232,6 +232,7 @@ static const struct dwc3_generic_config eic7700_dwc3 =  {
 };
 
 static const struct of_device_id dwc3_generic_of_match[] = {
+	{ .compatible = "altr,agilex5-dwc3", },
 	{ .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3},
 	{ .compatible = "spacemit,k3-dwc3", },
 	{ .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3},
-- 
2.49.GIT

Re: [PATCH v7 1/2] dt-bindings: usb: add Altera Agilex5 DWC3 controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The schema incorrectly uses `additionalProperties: false` while referencing a common schema (`snps,dwc3-common.yaml#`), breaking property inheritance and leading to redundant property declarations.
- [Low] Mandating software workaround quirks (`snps,dis_u2_susphy_quirk`, `snps,dis_u3_susphy_quirk`) in the `required` list.
--

commit dc0ed2c5f838c95fd4fbbcd46531a58ec24f6ca2
Author: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

dt-bindings: usb: add Altera Agilex5 DWC3 controller

This commit adds a device tree binding for the Altera Agilex5 SoC integration
of the Synopsys DWC3 USB controller.

> diff --git a/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> new file mode 100644
> index 0000000000000..610ddcb632e28
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml

[ ... ]

> +  reset-names:
> +    items:
> +      - const: core
> +      - const: ecc
> +
> +  dr_mode: true
> +
> +  maximum-speed: true
> +
> +  snps,dis_u2_susphy_quirk: true
> +
> +  snps,dis_u3_susphy_quirk: true
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - phys
> +  - phy-names
> +  - resets
> +  - reset-names
> +  - snps,dis_u2_susphy_quirk
> +  - snps,dis_u3_susphy_quirk

[Severity: Low]
Are these software workaround quirks strictly required for all hardware configurations?

Quirks are meant to be optional software workarounds for specific boards or
silicon revisions. If every device matching altr,agilex5-dwc3 intrinsically
requires these suspend PHY quirks, shouldn't the driver apply them natively
in code when it matches the compatible string, rather than forcing device
tree authors to manually include these workaround flags in every node?

> +
> +additionalProperties: false

[Severity: Low]
Does this strict inheritance restriction cause the redundant definitions above?

In JSON schema, additionalProperties: false ignores properties validated by
allOf $ref schemas like snps,dwc3-common.yaml. This appears to force
redundantly redefining standard properties like dr_mode, maximum-speed, and
the suspend PHY quirks as true in the local properties block just to pass
validation.

Could this be changed to unevaluatedProperties: false to allow removing the
redundant local declarations while properly inheriting the schema definitions?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1789114385.git.adrian.ho.yin.ng@altera.com?part=1