Re: [PATCH 3/8] arm64: dts: qcom: monaco: Add t-power-on-us property for PCIe root ports

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The 't-power-on-us' property is added to the device tree but is not documented in any DT binding schema, which will cause dtbs_check schema validation errors.
--

commit 9b34f8b26e1f1d145e5d0352099be4384e076f5b
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: monaco: Add t-power-on-us property for PCIe root ports

This commit adds the t-power-on-us property to the PCIe root ports in the
Monaco device tree. The property is intended to correctly program the
T_POWER_ON value during host initialization to prevent improper L1.2 exit
behavior.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index cfe39f923224f..d9c3669b5e1b7 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2402,6 +2402,8 @@ pcieport0: pcie@0 {
>  				#size-cells = <2>;
>  				ranges;
>  				phys = <&pcie0_phy>;
> +
> +				t-power-on-us = <80>;

[Severity: Low]
Is there a corresponding device tree binding schema update for this property? 

Since t-power-on-us is not currently documented in the schema, it looks like 
this addition will trigger make dtbs_check validation errors when 
qcom,pcie-common.yaml enforces unevaluatedProperties: false on the pcie@ 
child nodes.

>  			};
>  		};
>  
> @@ -2593,6 +2595,8 @@ pcieport1: pcie@0 {
>  				#size-cells = <2>;
>  				ranges;
>  				phys = <&pcie1_phy>;
> +
> +				t-power-on-us = <80>;
>  			};
>  		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260911-t_pwr_on-v1-0-c9eee197d082@oss.qualcomm.com?part=3