[PATCH 0/8] arm64: dts: qcom: Add t-power-on-us property for PCIe root ports

[PATCH 0/8] arm64: dts: qcom: Add t-power-on-us property for PCIe root ports

[Krishna Chaitanya Chundru]

The Qualcomm PCIe host controller driver added support for parsing the
-power-on-us property[1] from each Root Port node and programming it as
art of host initialization (PCI: qcom: Program T_POWER_ON) [2]. Prior to
this, T_POWER_ON was expected to be programmed correctly in hardware or
by the bootloader, but not all targets support this, which can lead to an
incorrectly calculated LTR_L1.2_THRESHOLD in aspm.c and improper L1.2 exit
behavior.

This series adds the t-power-on-us = <80>; property to the PCIe root
port node(s) on the following targets, so the controller programs the
correct T_POWER_ON value instead of relying on the (currently incorrect)
hardware default:

- kodiak
- lemans
- monaco
- hamoa
- glymur
- talos
- sm8750
- kaanapali

[1] https://lore.kernel.org/all/20260205093346.667898-1-krishna.chundru@oss.qualcomm.com/
[2] https://lore.kernel.org/all/20260428-t_power_on_fux-v5-0-f1ef926a91ff@oss.qualcomm.com/

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
Krishna Chaitanya Chundru (8):
      arm64: dts: qcom: kodiak: Add t-power-on-us property for PCIe root ports
      arm64: dts: qcom: lemans: Add t-power-on-us property for PCIe root ports
      arm64: dts: qcom: monaco: Add t-power-on-us property for PCIe root ports
      arm64: dts: qcom: hamoa: Add t-power-on-us property for PCIe root ports
      arm64: dts: qcom: glymur: Add t-power-on-us property for PCIe root ports
      arm64: dts: qcom: talos: Add t-power-on-us property for PCIe root port
      arm64: dts: qcom: sm8750: Add t-power-on-us property for PCIe root port
      arm64: dts: qcom: kaanapali: Add t-power-on-us property for PCIe root port

 arch/arm64/boot/dts/qcom/glymur.dtsi    | 8 ++++++++
 arch/arm64/boot/dts/qcom/hamoa.dtsi     | 8 ++++++++
 arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 ++
 arch/arm64/boot/dts/qcom/kodiak.dtsi    | 4 ++++
 arch/arm64/boot/dts/qcom/lemans.dtsi    | 4 ++++
 arch/arm64/boot/dts/qcom/monaco.dtsi    | 4 ++++
 arch/arm64/boot/dts/qcom/sm8750.dtsi    | 2 ++
 arch/arm64/boot/dts/qcom/talos.dtsi     | 2 ++
 8 files changed, 34 insertions(+)
---
base-commit: 08df884136f1c1197bab2a27814404fd329d9aac
change-id: 20260911-t_pwr_on-069f454ebb23

Best regards,
--  
Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

[PATCH 1/8] arm64: dts: qcom: kodiak: Add t-power-on-us property for PCIe root ports

[Krishna Chaitanya Chundru]

Currently the PCIe controller is not programming the T_POWER_ON value,
which can result in improper L1.2 exit behavior. Add the
t-power-on-us property to the PCIe root ports so that this value is
correctly programmed during host initialization.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kodiak.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index f2da3706d5c8..54acc7d9bdea 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -2306,6 +2306,8 @@ pcie0_port: pcie@0 {
 				#address-cells = <3>;
 				#size-cells = <2>;
 				ranges;
+
+				t-power-on-us = <80>;
 			};
 		};
 
@@ -2439,6 +2441,8 @@ pcie1_port0: pcie@0 {
 				#address-cells = <3>;
 				#size-cells = <2>;
 				ranges;
+
+				t-power-on-us = <80>;
 			};
 		};
 

-- 
2.34.1

[PATCH 2/8] arm64: dts: qcom: lemans: Add t-power-on-us property for PCIe root ports

[Krishna Chaitanya Chundru]

Currently the PCIe controller is not programming the T_POWER_ON value,
which can result in improper L1.2 exit behavior. Add the
t-power-on-us property to the PCIe root ports so that this value is
correctly programmed during host initialization.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/lemans.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 695eae1b7256..615a9bfda237 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -2770,6 +2770,8 @@ pcieport0: pcie@0 {
 				#address-cells = <3>;
 				#size-cells = <2>;
 				ranges;
+
+				t-power-on-us = <80>;
 			};
 		};
 
@@ -2943,6 +2945,8 @@ pcie@0 {
 				#address-cells = <3>;
 				#size-cells = <2>;
 				ranges;
+
+				t-power-on-us = <80>;
 			};
 		};
 

-- 
2.34.1

Re: [PATCH 2/8] arm64: dts: qcom: lemans: Add t-power-on-us property for PCIe root ports

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Logic Error / Dead Code: The newly added `t-power-on-us` property is completely ignored
- [Low] Missing DT Binding Documentation
--

commit 821321f53e293af9b1a675f69406aacca48b199d
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: lemans: Add t-power-on-us property for PCIe root ports

This commit attempts to fix improper L1.2 exit behavior by programming the
T_POWER_ON value. It adds the t-power-on-us property to the PCIe root port
nodes in the lemans device tree.

> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 695eae1b72569..615a9bfda2377 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -2770,6 +2770,8 @@ pcieport0: pcie@0 {
>  				#address-cells = <3>;
>  				#size-cells = <2>;
>  				ranges;
> +
> +				t-power-on-us = <80>;

[Severity: Low]
Is this missing a corresponding update to the device tree binding
documentation? This introduces the t-power-on-us property without
documenting it in any Documentation/devicetree/bindings/ YAML file, which
will cause dtbs_check to fail.

[Severity: High]
Will this property actually be parsed by the driver as structured?

Since this child node lacks a phys property, devm_of_phy_get() will return
-ENODEV when qcom_pcie_parse_port() iterates over child nodes to parse the
port properties.

The fallback path, qcom_pcie_parse_legacy_binding(), successfully reads
the PHY from the parent node, but it appears to never parse the new
t-power-on-us property.

Does this cause the value to be completely ignored during device probe,
preventing the T_POWER_ON value from being programmed into hardware?

>  			};
>  		};
>  
> @@ -2943,6 +2945,8 @@ pcie@0 {
>  				#address-cells = <3>;
>  				#size-cells = <2>;
>  				ranges;
> +
> +				t-power-on-us = <80>;

[Severity: High]
Does this second child node also suffer from the same parsing fallback
issue? Without a phys property on this node, the driver will likely
ignore the new t-power-on-us property here as well.

>  			};
>  		};
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260911-t_pwr_on-v1-0-c9eee197d082@oss.qualcomm.com?part=2

[PATCH 3/8] arm64: dts: qcom: monaco: Add t-power-on-us property for PCIe root ports

[Krishna Chaitanya Chundru]

Currently the PCIe controller is not programming the T_POWER_ON value,
which can result in improper L1.2 exit behavior. Add the
t-power-on-us property to the PCIe root ports so that this value is
correctly programmed during host initialization.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index cfe39f923224..d9c3669b5e1b 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2402,6 +2402,8 @@ pcieport0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 				phys = <&pcie0_phy>;
+
+				t-power-on-us = <80>;
 			};
 		};
 
@@ -2593,6 +2595,8 @@ pcieport1: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 				phys = <&pcie1_phy>;
+
+				t-power-on-us = <80>;
 			};
 		};
 

-- 
2.34.1

Re: [PATCH 3/8] arm64: dts: qcom: monaco: Add t-power-on-us property for PCIe root ports

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The 't-power-on-us' property is added to the device tree but is not documented in any DT binding schema, which will cause dtbs_check schema validation errors.
--

commit 9b34f8b26e1f1d145e5d0352099be4384e076f5b
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: monaco: Add t-power-on-us property for PCIe root ports

This commit adds the t-power-on-us property to the PCIe root ports in the
Monaco device tree. The property is intended to correctly program the
T_POWER_ON value during host initialization to prevent improper L1.2 exit
behavior.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index cfe39f923224f..d9c3669b5e1b7 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2402,6 +2402,8 @@ pcieport0: pcie@0 {
>  				#size-cells = <2>;
>  				ranges;
>  				phys = <&pcie0_phy>;
> +
> +				t-power-on-us = <80>;

[Severity: Low]
Is there a corresponding device tree binding schema update for this property? 

Since t-power-on-us is not currently documented in the schema, it looks like 
this addition will trigger make dtbs_check validation errors when 
qcom,pcie-common.yaml enforces unevaluatedProperties: false on the pcie@ 
child nodes.

>  			};
>  		};
>  
> @@ -2593,6 +2595,8 @@ pcieport1: pcie@0 {
>  				#size-cells = <2>;
>  				ranges;
>  				phys = <&pcie1_phy>;
> +
> +				t-power-on-us = <80>;
>  			};
>  		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260911-t_pwr_on-v1-0-c9eee197d082@oss.qualcomm.com?part=3

[PATCH 4/8] arm64: dts: qcom: hamoa: Add t-power-on-us property for PCIe root ports

[Krishna Chaitanya Chundru]

Currently the PCIe controller is not programming the T_POWER_ON value,
which can result in improper L1.2 exit behavior. Add the
t-power-on-us property to the PCIe root ports so that this value is
correctly programmed during host initialization.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hamoa.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 8a96ea1bdb9c..2fbcdd4e9088 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -3374,6 +3374,8 @@ pcie3_port0: pcie@0 {
 				#address-cells = <3>;
 				#size-cells = <2>;
 				ranges;
+
+				t-power-on-us = <80>;
 			};
 		};
 
@@ -3514,6 +3516,8 @@ pcie6a_port0: pcie@0 {
 				#address-cells = <3>;
 				#size-cells = <2>;
 				ranges;
+
+				t-power-on-us = <80>;
 			};
 		};
 
@@ -3654,6 +3658,8 @@ pcie5_port0: pcie@0 {
 				#address-cells = <3>;
 				#size-cells = <2>;
 				ranges;
+
+				t-power-on-us = <80>;
 			};
 		};
 
@@ -3793,6 +3799,8 @@ pcie4_port0: pcie@0 {
 				#address-cells = <3>;
 				#size-cells = <2>;
 				ranges;
+
+				t-power-on-us = <80>;
 			};
 		};
 

-- 
2.34.1

[PATCH 5/8] arm64: dts: qcom: glymur: Add t-power-on-us property for PCIe root ports

[Krishna Chaitanya Chundru]

Currently the PCIe controller is not programming the T_POWER_ON value,
which can result in improper L1.2 exit behavior. Add the
t-power-on-us property to the PCIe root ports so that this value is
correctly programmed during host initialization.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index f04058d2e089..f7d7d76830b3 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3001,6 +3001,8 @@ pcie4_port0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 
+				t-power-on-us = <80>;
+
 				port {
 					pcie4_port0_ep: endpoint {
 					};
@@ -3273,6 +3275,8 @@ pcie5_port0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 
+				t-power-on-us = <80>;
+
 				port {
 					pcie5_port0_ep: endpoint {
 					};
@@ -3489,6 +3493,8 @@ pcie6_port0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 
+				t-power-on-us = <80>;
+
 				port {
 					pcie6_port0_ep: endpoint {
 					};
@@ -3759,6 +3765,8 @@ pcie3b_port0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 
+				t-power-on-us = <80>;
+
 				port {
 					pcie3b_port0_ep: endpoint {
 					};

-- 
2.34.1

[PATCH 6/8] arm64: dts: qcom: talos: Add t-power-on-us property for PCIe root port

[Krishna Chaitanya Chundru]

Currently the PCIe controller is not programming the T_POWER_ON value,
which can result in improper L1.2 exit behavior. Add the
t-power-on-us property to the PCIe root port so that this value is
correctly programmed during host initialization.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/talos.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index eedfdce3c479..ceb1dfc5189d 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -1401,6 +1401,8 @@ pcie_port0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 				bus-range = <0x01 0xff>;
+
+				t-power-on-us = <80>;
 			};
 		};
 

-- 
2.34.1

[PATCH 7/8] arm64: dts: qcom: sm8750: Add t-power-on-us property for PCIe root port

[Krishna Chaitanya Chundru]

Currently the PCIe controller is not programming the T_POWER_ON value,
which can result in improper L1.2 exit behavior. Add the
t-power-on-us property to the PCIe root port so that this value is
correctly programmed during host initialization.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index dd738d13df8e..bb57385678f4 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -5577,6 +5577,8 @@ pcieport0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 				phys = <&pcie0_phy>;
+
+				t-power-on-us = <80>;
 			};
 		};
 

-- 
2.34.1

Re: [PATCH 7/8] arm64: dts: qcom: sm8750: Add t-power-on-us property for PCIe root port

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The property 't-power-on-us' is introduced in the device tree without a corresponding update to the device tree binding schema.
--

commit 0f66318dcdfeebf212674b31a30fbfa300a4c149
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: sm8750: Add t-power-on-us property for PCIe root port

This commit adds the t-power-on-us property to the PCIe root port on the
sm8750 platform. This ensures T_POWER_ON is correctly programmed during host
initialization, preventing improper L1.2 exit behavior.

> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index dd738d13df8e0..bb57385678f4d 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -5577,6 +5577,8 @@ pcieport0: pcie@0 {
>  				#size-cells = <2>;
>  				ranges;
>  				phys = <&pcie0_phy>;
> +
> +				t-power-on-us = <80>;

[Severity: Low]
Does this new property cause make dtbs_check to emit schema validation
warnings? It appears t-power-on-us is being introduced here in pcieport0
without a corresponding update to the device tree binding schema.

>  			};
>  		};
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260911-t_pwr_on-v1-0-c9eee197d082@oss.qualcomm.com?part=7

[PATCH 8/8] arm64: dts: qcom: kaanapali: Add t-power-on-us property for PCIe root port

[Krishna Chaitanya Chundru]

Currently the PCIe controller is not programming the T_POWER_ON value,
which can result in improper L1.2 exit behavior. Add the
t-power-on-us property to the PCIe root port so that this value is
correctly programmed during host initialization.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 131fd2a16c54..1a47fafe7265 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -2456,6 +2456,8 @@ pcie_port0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 				phys = <&pcie0_phy>;
+
+				t-power-on-us = <80>;
 			};
 		};
 

-- 
2.34.1