Devicetree
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From: sashiko-bot@kernel.org
To: adrian.ho.yin.ng@altera.com
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v7 1/2] arm64: dts: intel: agilex5: add USB3.1 controller node
Date: Fri, 11 Sep 2026 09:19:54 +0000	[thread overview]
Message-ID: <20260911091955.52BF31F00893@smtp.kernel.org> (raw)
In-Reply-To: <dba41aa636c6db86be9e0e2a3e2ae1a03095e1cb.1789114403.git.adrian.ho.yin.ng@altera.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Missing fallback compatible string prevents the DWC3 controller from probing.
- [Medium] Devicetree Topology / Address Space Overflow in DMA ranges mapping.
--

commit f5eee55ab58207528984fe03c0204fcdede698dd
Author: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Date:   Fri Sep 11 09:09:24 2026 +0000

arm64: dts: intel: agilex5: add USB3.1 controller node

This commit adds a devicetree node for the Synopsys DWC3 USB3.1 controller on
the Agilex5 SoC. It places the controller under a simple-bus with a 40-bit
dma-ranges window to match the interconnect's DMA address width. The
controller is also enabled in host mode for the SoCDK board.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index f54767d1526e1..523f722a2a642 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -493,6 +493,41 @@ usb0: usb@10b00000 {
>  			status = "disabled";
>  		};
>  
> +		usb31_bus: usb-bus@11000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges = <0x0 0x0 0x11000000 0x0 0x100000>;
> +			/*
> +			 * USB interconnect DMA is limited to 40-bit addresses
> +			 * (1 TiB window from 0).
> +			 */
> +			dma-ranges = <0x0 0x0 0x0 0x100 0x0>;

[Severity: Medium]
Does this dma-ranges mapping structurally overflow the parent bus?

This property specifies a 1 TiB window (0x100 0x0) and maps it into the parent
bus which only has 32-bit address capacity. Since a 32-bit bus can
mathematically only address up to 4 GB, could this cause DMA configuration
failures or silent truncations depending on how the OF core parses the tree?

> +
> +			usb31: usb@0 {
> +				compatible = "altr,agilex5-dwc3";

[Severity: High]
Will the USB subsystem fail to bind to this device without a generic fallback?

This node specifies a SoC-specific compatible string but does not include a
generic fallback string like "snps,dwc3". Because there is no matching driver
in the kernel for "altr,agilex5-dwc3", won't the DWC3 core driver silently
ignore this node and leave the controller unprobed?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1789114403.git.adrian.ho.yin.ng@altera.com?part=1

  reply	other threads:[~2026-09-11  9:19 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-11  9:09 [PATCH v7 0/2] arm64: dts: intel: agilex5: enable USB3.1 on SoCDK adrian.ho.yin.ng
2026-09-11  9:09 ` [PATCH v7 1/2] arm64: dts: intel: agilex5: add USB3.1 controller node adrian.ho.yin.ng
2026-09-11  9:19   ` sashiko-bot [this message]
2026-09-11  9:09 ` [PATCH v7 2/2] arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK adrian.ho.yin.ng

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