[PATCH v7 0/2] arm64: dts: intel: agilex5: enable USB3.1 on SoCDK

[PATCH v7 0/2] arm64: dts: intel: agilex5: enable USB3.1 on SoCDK

[adrian.ho.yin.ng]

From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Add the Agilex5 USB3.1 DWC3 controller node and enable it in host mode on
the SoCDK board. Place the controller under a simple-bus with a 40-bit
dma-ranges window so the DMA/IOMMU stack respects the interconnect address
width when SMMU is enabled.

The SoCDK daughter card only exposes the USB3.1 interface, so the unused
USB0 (DWC2) board enablement is removed in a follow-up patch.

This DTS series is posted separately from the USB bindings/driver series
("[PATCH v7 0/2] usb: dwc3: add Altera Agilex5 DWC3 support"). Depends on
compatible "altr,agilex5-dwc3" from that series:
https://lore.kernel.org/all/cover.1789114385.git.adrian.ho.yin.ng@altera.com/

---
changelog:
v6->v7:
* Split out of the USB series into a standalone DTS posting.

USB v7 series:
https://lore.kernel.org/all/cover.1789114385.git.adrian.ho.yin.ng@altera.com/

Previous combined series (v6):
https://lore.kernel.org/all/cover.1788886615.git.adrian.ho.yin.ng@altera.com/
---

Adrian Ng Ho Yin (2):
  arm64: dts: intel: agilex5: add USB3.1 controller node
  arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK

 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 35 +++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  4 +--
 2 files changed, 37 insertions(+), 2 deletions(-)


base-commit: bc35965f6940a9bf834d54187b6088b8eb09206d
-- 
2.49.GIT

[PATCH v7 1/2] arm64: dts: intel: agilex5: add USB3.1 controller node

[adrian.ho.yin.ng]

From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Add a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC.
Place it under a simple-bus with a 40-bit dma-ranges window (#address-cells
= 2) to match the USB DMA address width of the interconnect. Enable it in
host mode on the SoCDK board.

ref and suspend both use AGILEX5_USB31_SUSPEND_CLK because they share the
same hardware clock source on this SoC.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 35 +++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  5 +++
 2 files changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index f54767d1526e..523f722a2a64 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -493,6 +493,41 @@ usb0: usb@10b00000 {
 			status = "disabled";
 		};
 
+		usb31_bus: usb-bus@11000000 {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x11000000 0x0 0x100000>;
+			/*
+			 * USB interconnect DMA is limited to 40-bit addresses
+			 * (1 TiB window from 0).
+			 */
+			dma-ranges = <0x0 0x0 0x0 0x100 0x0>;
+
+			usb31: usb@0 {
+				compatible = "altr,agilex5-dwc3";
+				reg = <0x0 0x0 0x0 0x100000>;
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				/*
+				 * ref and suspend share the same hardware
+				 * source; reuse the published suspend clock ID.
+				 */
+				clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>,
+					 <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
+					 <&clkmgr AGILEX5_USB31_SUSPEND_CLK>;
+				clock-names = "bus_early", "ref", "suspend";
+				resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+				reset-names = "core", "ecc";
+				iommus = <&smmu 7>;
+				phys = <&usbphy0>, <&usbphy0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				maximum-speed = "super-speed";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				status = "disabled";
+			};
+		};
+
 		watchdog0: watchdog@10d00200 {
 			compatible = "snps,dw-wdt";
 			reg = <0x10d00200 0x100>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 1e9b87d96765..aa9294494421 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -109,6 +109,11 @@ &usb0 {
 	disable-over-current;
 };
 
+&usb31 {
+	dr_mode = "host";
+	status = "okay";
+};
+
 &watchdog0 {
 	status = "okay";
 };
-- 
2.49.GIT

[PATCH v7 2/2] arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK

[adrian.ho.yin.ng]

From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

The Agilex5 SoCDK daughter card only provides a USB3.1 interface (USB1).
USB0 is not connected or used on this board. Remove the USB0 node to avoid
unnecessary initialization and potential resource conflicts.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index aa9294494421..c48867cc3043 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -104,11 +104,6 @@ &uart0 {
 	status = "okay";
 };
 
-&usb0 {
-	status = "okay";
-	disable-over-current;
-};
-
 &usb31 {
 	dr_mode = "host";
 	status = "okay";
-- 
2.49.GIT

Re: [PATCH v7 1/2] arm64: dts: intel: agilex5: add USB3.1 controller node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Missing fallback compatible string prevents the DWC3 controller from probing.
- [Medium] Devicetree Topology / Address Space Overflow in DMA ranges mapping.
--

commit f5eee55ab58207528984fe03c0204fcdede698dd
Author: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Date:   Fri Sep 11 09:09:24 2026 +0000

arm64: dts: intel: agilex5: add USB3.1 controller node

This commit adds a devicetree node for the Synopsys DWC3 USB3.1 controller on
the Agilex5 SoC. It places the controller under a simple-bus with a 40-bit
dma-ranges window to match the interconnect's DMA address width. The
controller is also enabled in host mode for the SoCDK board.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index f54767d1526e1..523f722a2a642 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -493,6 +493,41 @@ usb0: usb@10b00000 {
>  			status = "disabled";
>  		};
>  
> +		usb31_bus: usb-bus@11000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges = <0x0 0x0 0x11000000 0x0 0x100000>;
> +			/*
> +			 * USB interconnect DMA is limited to 40-bit addresses
> +			 * (1 TiB window from 0).
> +			 */
> +			dma-ranges = <0x0 0x0 0x0 0x100 0x0>;

[Severity: Medium]
Does this dma-ranges mapping structurally overflow the parent bus?

This property specifies a 1 TiB window (0x100 0x0) and maps it into the parent
bus which only has 32-bit address capacity. Since a 32-bit bus can
mathematically only address up to 4 GB, could this cause DMA configuration
failures or silent truncations depending on how the OF core parses the tree?

> +
> +			usb31: usb@0 {
> +				compatible = "altr,agilex5-dwc3";

[Severity: High]
Will the USB subsystem fail to bind to this device without a generic fallback?

This node specifies a SoC-specific compatible string but does not include a
generic fallback string like "snps,dwc3". Because there is no matching driver
in the kernel for "altr,agilex5-dwc3", won't the DWC3 core driver silently
ignore this node and leave the controller unprobed?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1789114403.git.adrian.ho.yin.ng@altera.com?part=1