Re: [PATCH v5 5/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R5S

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The PCI root port bridge nodes (`pcie@0,0`) specify invalid `bus-range` properties that incorrectly duplicate the host controllers' bus ranges, resulting in secondary buses that overlap with their primary buses and conflict with downstream child device configurations.
--

commit 9036af8384aaa0dde91ac21a4bd6adf0c3d12244
Author: Ricardo Pardini <ricardo@pardini.net>

arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R5S

The FriendlyElec NanoPi R5S (rk3568) carries two on-board Realtek
RTL8125 NICs behind pcie2x1 and pcie3x1, alongside the existing gmac0
RGMII PHY. This describes the fixed function nodes and attaches ethernet1
and ethernet2 aliases so U-Boot can inject MAC addresses for them.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> index 90ce6f0e1dcff..9ed11663c31c9 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts

[ ... ]

> @@ -107,6 +109,20 @@ &pcie2x1 {
>  	num-lanes = <1>;
>  	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
>  	status = "okay";
> +
> +	pcie@0,0 {
> +		reg = <0x000000 0 0 0 0>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges;
> +		device_type = "pci";
> +		bus-range = <0x00 0x0f>;

[Severity: Low]
Does this describe an invalid PCI topology where the pcie2x1 bridge's
secondary bus is identical to its primary bus? Setting the secondary
bus to 0x00 conflicts with its primary bus (0x00) and the downstream
rtl_eth1 child node's bus (0x01).

> +
> +		rtl_eth1: ethernet@0,0 {
> +			compatible = "pci10ec,8125";
> +			reg = <0x010000 0 0 0 0>;
> +		};
> +	};
>  };

[ ... ]

> @@ -119,6 +135,20 @@ &pcie3x1 {
>  	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
>  	vpcie3v3-supply = <&vcc3v3_pcie>;
>  	status = "okay";
> +
> +	pcie@0,0 {
> +		reg = <0x100000 0 0 0 0>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges;
> +		device_type = "pci";
> +		bus-range = <0x10 0x1f>;

[Severity: Low]
Does this also configure the pcie3x1 bridge's secondary bus to 0x10,
conflicting with its own primary bus (0x10) and the downstream
rtl_eth2 child node's bus (0x11)?

> +
> +		rtl_eth2: ethernet@0,0 {
> +			compatible = "pci10ec,8125";
> +			reg = <0x110000 0 0 0 0>;
> +		};
> +	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260910-rk3588-dts-rtl-eth-describe-dt-alias-v5-0-c1b9e5f10cd6@pardini.net?part=5