From: sashiko-bot@kernel.org
To: "Ricardo Pardini" <ricardo@pardini.net>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v5 4/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on CM3588-NAS
Date: Fri, 11 Sep 2026 20:08:17 +0000 [thread overview]
Message-ID: <20260911200818.347B91F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260910-rk3588-dts-rtl-eth-describe-dt-alias-v5-4-c1b9e5f10cd6@pardini.net>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Device Tree Topology Error: Conflicting PCI bus assignment for Root Port and its child device
--
commit 8bfbba94d98cec905dbfa4da80cf6195fd8103fa
Author: Ricardo Pardini <ricardo@pardini.net>
arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on CM3588-NAS
This commit adds the fixed function node for the on-board Realtek RTL8125 NIC
and attaches an ethernet0 alias so that U-Boot can inject a MAC address.
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
> index f4c34da61c4df..96b3b245e0866 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
[ ... ]
> @@ -512,6 +516,23 @@ &pcie2x1l1 {
> status = "okay";
> };
>
> +&pcie2x1l2 {
> + /* on-board RTL8125 2.5GbE NIC */
> + pcie@0,0 {
> + reg = <0x400000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + device_type = "pci";
> + bus-range = <0x40 0x4f>;
[Severity: Low]
Does this create a conflicting PCI bus assignment? The PCI-to-PCI bridge
pcie@0,0 resides on primary bus 0x40 but also claims a secondary bus of 0x40
via this bus-range declaration.
A bridge cannot have the same primary and secondary bus. Furthermore, its
downstream child device ethernet@0,0 is explicitly placed on bus 0x41 below,
which contradicts the bridge's claimed secondary bus 0x40.
While the Linux PCI subsystem typically ignores this DT property on bridges and
dynamically re-enumerates the bus topology correctly, could this cause issues
for static DT parsers like U-Boot that this patch relies on for MAC address
injection?
> +
> + rtl_eth0: ethernet@0,0 {
> + compatible = "pci10ec,8125";
> + reg = <0x410000 0 0 0 0>;
> + };
> + };
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260910-rk3588-dts-rtl-eth-describe-dt-alias-v5-0-c1b9e5f10cd6@pardini.net?part=4
next prev parent reply other threads:[~2026-09-11 20:08 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-10 20:07 [PATCH v5 0/7] describe RTL8125 PCIe NICs on Rockchip boards (and add DT binding) Ricardo Pardini via B4 Relay
2026-09-10 20:07 ` [PATCH v5 1/7] dt-bindings: net: add Realtek RTL8125 PCIe Ethernet Ricardo Pardini via B4 Relay
2026-09-12 12:43 ` Heiko Stuebner
2026-09-10 20:07 ` [PATCH v5 2/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6 Ricardo Pardini via B4 Relay
2026-09-11 9:52 ` Diederik de Haas
2026-09-11 12:19 ` Ricardo Pardini
2026-09-11 13:04 ` Diederik de Haas
2026-09-10 20:07 ` [PATCH v5 3/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 family Ricardo Pardini via B4 Relay
2026-09-10 20:07 ` [PATCH v5 4/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on CM3588-NAS Ricardo Pardini via B4 Relay
2026-09-11 20:08 ` sashiko-bot [this message]
2026-09-10 20:07 ` [PATCH v5 5/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R5S Ricardo Pardini via B4 Relay
2026-09-11 20:08 ` sashiko-bot
2026-09-10 20:07 ` [PATCH v5 6/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R6C Ricardo Pardini via B4 Relay
2026-09-10 20:07 ` [PATCH v5 7/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 ITX Ricardo Pardini via B4 Relay
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