Re: [PATCH DNM RFC v2 10/10] arm64: dts: qcom: kaanapali: Add MPAM MSC nodes for the L2 caches

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Moving CPU cache nodes to the root of the DT to act as memory buses violates devicetree architecture and topology guidelines.
- [Medium] The patch merges a DTS example that the author explicitly stated is not intended for merging.
--

commit f6c1db4f30b0478f01fb8ab1a9aacf8a8f1f03a0
Author: Yin Li <yin.li@oss.qualcomm.com>

arm64: dts: qcom: kaanapali: Add MPAM MSC nodes for the L2 caches

This commit adds MPAM MSC device nodes for each L2 cache in the kaanapali
device tree. The L2 cache nodes are moved from the CPU nodes to the root
of the device tree, gaining memory bus properties like ranges to allow the
MSC devices to be nested under them.

> The nodes are disabled by default. Production firmware does not expose
> MSC register access to the OS, so these nodes can only be enabled on a
> local test setup where firmware permits direct MMIO access to the MSCs.
> This DTS is therefore only an example for other platform DT authors and
> is not intended to be merged.

[Severity: Medium]
Is this patch intended for the production tree? The commit message explicitly
states that this device tree is only an example for a local test setup and is
not intended to be merged, so applying it would pollute the production
hardware description with dead test code.

> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
[ ... ]
> @@ -531,6 +519,44 @@ soccp_smp2p_in: slave-kernel {
>  		};
>  	};
>  
> +	l2_0: l2-cache-0 {
> +		compatible = "cache";
> +		cache-level = <2>;
> +		cache-unified;
> +		cache-size = <0xc00000>;
> +		ranges;
> +
> +		#address-cells = <2>;
> +		#size-cells = <2>;

[Severity: Medium]
Does moving the CPU cache nodes to the root of the device tree and treating
them as memory buses (by adding ranges and #address-cells) violate
devicetree architectural topology guidelines? Typically, logical cache nodes
reside within the /cpus hierarchy rather than at the root of the physical
address space.

> +
> +		msc@19870000 {
> +			compatible = "arm,mpam-msc";
> +			reg = <0x0 0x19870000 0x0 0x10000>;
> +			arm,not-ready-us = <1>;
> +			status = "disabled";
> +		};
> +
> +	};
> +
> +	l2_1: l2-cache-1 {
> +		compatible = "cache";
> +		cache-level = <2>;
> +		cache-unified;
> +		cache-size = <0xc00000>;
> +		ranges;

[Severity: Medium]
Similarly, the second cache node is moved to the root to act as a bus. Does
this distort the device tree topology?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260914-mpam-resctrl-dt-knp-support-v2-0-bf6645bb2f65@oss.qualcomm.com?part=10