* [PATCH v2 00/14] ARM: deprecated platform removal
@ 2026-09-14 14:08 Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 06/14] ARM: omap2: remove omap24xx support Arnd Bergmann
` (7 more replies)
0 siblings, 8 replies; 13+ messages in thread
From: Arnd Bergmann @ 2026-09-14 14:08 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, Krzysztof Kozlowski, Rob Herring, Conor Dooley,
Russell King, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Alexandre Belloni,
Claudiu Beznea, Andrew Lunn, Sebastian Hesselbarth,
Gregory Clement, Robert Jarzmik, Kristoffer Ericson,
Linus Walleij, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm), Nicolas Pitre, linux-doc, linux-kernel,
linux-arm-kernel, devicetree, imx, linux-stm32, linux-omap
From: Arnd Bergmann <arnd@arndb.de>
In the 7.3 kernel, I marked a number of platforms and features as
deprecated, with the plan to keep these around for the LTS kernel, but
remove them in 7.4, see [1].
Cleaning out the deprecated platform code has turned into a larger effort
than I expected, currently standing at 300 patches, with a lot of them
still in need of being split up into smaller ones, see [2] for a current
snapshot.
The first series here removes just the bits in arch/arm/mach-*/, plus
the portions that directly depend on the removed Kconfig symbols where
these are trivial to remove.
The parts that are not included are those that remove architectural
features and device drivers that become unused after this part,
This also gives everyone a chance to voice their objections in case
that some of the removed platform code does have active users after all,
before all the corresponding drivers are gone.
Arnd
Changes since v1 [3]:
- minor cleanups and fixes based on feedback
- skipped riscpc patch, which is still under discussion
- added patch to remove plat-orion, folding the remaining
PCI support into mach-orion5x
- added patch to remove Integrator/CM1136JF-S
Links:
[1] https://lore.kernel.org/all/20260701212353.2196041-1-arnd@kernel.org/
[2] https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/log/?h=board-remove-7.3
[3] https://lore.kernel.org/lkml/20260908152808.3928630-1-arnd@kernel.org/T/#t
Arnd Bergmann (14):
ARM: remove sa1100 platform
ARM: remove footbridge
ARM: remove legacy pxa board files
ARM: orion/dove/mv78xx0: remove all board files
ARM: orion5x: fold plat-orion/pcie.c and hw_pci into pci.c
ARM: omap2: remove omap24xx support
ARM: imx: remove i.MX31 SoC support
ARM: versatile: remove Integrator/CM1136JF-S option
ARM: imx: remove nommu support
ARM: lpc18xx: remove entire platform
ARM: stm32: remove stm32f4/f7/h7 MCU support
ARM: versatile: remove mps2 support
ARM: at91: remove samv7 support
ARM: axxia: remove entire platform
Documentation/arch/arm/index.rst | 9 -
Documentation/arch/arm/marvell.rst | 15 +-
Documentation/arch/arm/microchip.rst | 39 -
Documentation/arch/arm/netwinder.rst | 85 -
Documentation/arch/arm/sa1100/assabet.rst | 301 ---
Documentation/arch/arm/sa1100/cerf.rst | 35 -
Documentation/arch/arm/sa1100/index.rst | 13 -
Documentation/arch/arm/sa1100/lart.rst | 15 -
Documentation/arch/arm/sa1100/serial_uart.rst | 51 -
Documentation/arch/arm/stm32/overview.rst | 8 +-
.../arch/arm/stm32/stm32f429-overview.rst | 25 -
.../arch/arm/stm32/stm32f746-overview.rst | 32 -
.../arch/arm/stm32/stm32f769-overview.rst | 34 -
.../arch/arm/stm32/stm32h743-overview.rst | 33 -
.../arch/arm/stm32/stm32h750-overview.rst | 34 -
.../devicetree/bindings/arm/atmel-at91.yaml | 39 -
.../devicetree/bindings/arm/axxia.yaml | 23 -
MAINTAINERS | 48 -
arch/arm/Kconfig | 63 +-
arch/arm/Kconfig.debug | 104 +-
arch/arm/Makefile | 15 -
arch/arm/boot/bootp/Makefile | 2 -
arch/arm/boot/compressed/Makefile | 8 -
arch/arm/boot/compressed/head-sa1100.S | 45 -
arch/arm/boot/compressed/head-sharpsl.S | 151 --
arch/arm/boot/compressed/head.S | 7 -
arch/arm/boot/dts/arm/Makefile | 3 -
arch/arm/boot/dts/arm/mps2-an385.dts | 92 -
arch/arm/boot/dts/arm/mps2-an399.dts | 92 -
arch/arm/boot/dts/arm/mps2.dtsi | 220 --
arch/arm/boot/dts/intel/Makefile | 1 -
arch/arm/boot/dts/intel/axm/Makefile | 5 -
.../boot/dts/intel/axm/axm5516-amarillo.dts | 47 -
arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi | 200 --
arch/arm/boot/dts/intel/axm/axm55xx.dtsi | 200 --
arch/arm/boot/dts/nxp/imx/Makefile | 5 -
arch/arm/boot/dts/nxp/imx/imx31-bug.dts | 22 -
arch/arm/boot/dts/nxp/imx/imx31-lite.dts | 178 --
arch/arm/boot/dts/nxp/imx/imx31.dtsi | 371 ----
arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 ---------
arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 --------------
arch/arm/boot/dts/nxp/lpc/Makefile | 5 -
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 543 -----
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts | 221 --
.../boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 485 -----
arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi | 48 -
.../dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 624 ------
.../boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 621 ------
arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi | 52 -
arch/arm/boot/dts/nxp/vf/Makefile | 2 -
arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -
arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 -
arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -
arch/arm/boot/dts/st/Makefile | 11 -
arch/arm/boot/dts/st/stm32429i-eval.dts | 349 ----
arch/arm/boot/dts/st/stm32746g-eval.dts | 236 ---
arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi | 482 -----
arch/arm/boot/dts/st/stm32f429-disco.dts | 243 ---
arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi | 91 -
arch/arm/boot/dts/st/stm32f429.dtsi | 800 --------
arch/arm/boot/dts/st/stm32f469-disco.dts | 260 ---
arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi | 92 -
arch/arm/boot/dts/st/stm32f469.dtsi | 18 -
arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi | 436 ----
arch/arm/boot/dts/st/stm32f746-disco.dts | 234 ---
arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi | 55 -
arch/arm/boot/dts/st/stm32f746.dtsi | 727 -------
.../dts/st/stm32f769-disco-mb1166-reva09.dts | 13 -
arch/arm/boot/dts/st/stm32f769-disco.dts | 243 ---
arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi | 55 -
arch/arm/boot/dts/st/stm32f769.dtsi | 37 -
arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi | 301 ---
arch/arm/boot/dts/st/stm32h743.dtsi | 738 -------
arch/arm/boot/dts/st/stm32h743i-disco.dts | 145 --
arch/arm/boot/dts/st/stm32h743i-eval.dts | 185 --
arch/arm/boot/dts/st/stm32h747i-disco.dts | 149 --
arch/arm/boot/dts/st/stm32h750.dtsi | 6 -
arch/arm/boot/dts/st/stm32h750i-art-pi.dts | 229 ---
arch/arm/boot/dts/ti/omap/Makefile | 6 -
arch/arm/boot/dts/ti/omap/omap2.dtsi | 338 ----
.../arm/boot/dts/ti/omap/omap2420-clocks.dtsi | 267 ---
arch/arm/boot/dts/ti/omap/omap2420-h4.dts | 63 -
arch/arm/boot/dts/ti/omap/omap2420-n800.dts | 9 -
.../boot/dts/ti/omap/omap2420-n810-wimax.dts | 9 -
arch/arm/boot/dts/ti/omap/omap2420-n810.dts | 75 -
.../dts/ti/omap/omap2420-n8x0-common.dtsi | 123 --
arch/arm/boot/dts/ti/omap/omap2420.dtsi | 262 ---
.../arm/boot/dts/ti/omap/omap2430-clocks.dtsi | 341 ----
arch/arm/boot/dts/ti/omap/omap2430-sdp.dts | 70 -
arch/arm/boot/dts/ti/omap/omap2430.dtsi | 366 ----
.../arm/boot/dts/ti/omap/omap24xx-clocks.dtsi | 1241 ------------
arch/arm/common/Kconfig | 13 -
arch/arm/common/Makefile | 4 -
arch/arm/common/locomo.c | 886 --------
arch/arm/common/sa1111.c | 1413 -------------
arch/arm/common/scoop.c | 269 ---
arch/arm/common/sharpsl_param.c | 63 -
arch/arm/configs/am200epdkit_defconfig | 91 -
arch/arm/configs/assabet_defconfig | 57 -
arch/arm/configs/axm55xx_defconfig | 231 ---
arch/arm/configs/collie_defconfig | 87 -
arch/arm/configs/dove_defconfig | 134 --
arch/arm/configs/footbridge_defconfig | 114 --
arch/arm/configs/h3600_defconfig | 63 -
arch/arm/configs/imx_v6_v7_defconfig | 1 -
arch/arm/configs/imxrt_defconfig | 35 -
arch/arm/configs/jornada720_defconfig | 95 -
arch/arm/configs/lpc18xx_defconfig | 158 --
arch/arm/configs/mps2_defconfig | 102 -
arch/arm/configs/mv78xx0_defconfig | 120 --
arch/arm/configs/neponset_defconfig | 88 -
arch/arm/configs/netwinder_defconfig | 88 -
arch/arm/configs/omap2plus_defconfig | 4 -
arch/arm/configs/spitz_defconfig | 237 ---
arch/arm/configs/stm32_defconfig | 80 -
arch/arm/configs/vf610m4_defconfig | 39 -
arch/arm/include/asm/cputype.h | 4 -
arch/arm/include/asm/hardware/dec21285.h | 138 --
arch/arm/include/asm/hardware/locomo.h | 217 --
arch/arm/include/asm/hardware/sa1111.h | 442 ----
arch/arm/include/asm/hardware/scoop.h | 67 -
arch/arm/include/asm/hardware/ssp.h | 25 -
arch/arm/include/asm/mach/pci.h | 86 -
arch/arm/include/asm/mach/sharpsl_param.h | 33 -
arch/arm/include/asm/pci.h | 3 -
arch/arm/include/debug/dc21285.S | 41 -
arch/arm/include/debug/imx-uart.h | 10 -
arch/arm/include/debug/sa1100.S | 67 -
arch/arm/kernel/atags_parse.c | 18 -
arch/arm/kernel/bios32.c | 254 ---
arch/arm/kernel/head.S | 10 -
arch/arm/mach-at91/Kconfig | 11 +-
arch/arm/mach-at91/Makefile | 1 -
arch/arm/mach-at91/samv7.c | 17 -
arch/arm/mach-axxia/Kconfig | 17 -
arch/arm/mach-axxia/Makefile | 3 -
arch/arm/mach-axxia/axxia.c | 19 -
arch/arm/mach-axxia/platsmp.c | 87 -
arch/arm/mach-dove/Kconfig | 32 -
arch/arm/mach-dove/Makefile | 7 -
arch/arm/mach-dove/bridge-regs.h | 50 -
arch/arm/mach-dove/cm-a510.c | 94 -
arch/arm/mach-dove/common.c | 449 ----
arch/arm/mach-dove/common.h | 46 -
arch/arm/mach-dove/dove.h | 185 --
arch/arm/mach-dove/irq.c | 81 -
arch/arm/mach-dove/irqs.h | 89 -
arch/arm/mach-dove/mpp.c | 159 --
arch/arm/mach-dove/mpp.h | 197 --
arch/arm/mach-dove/pcie.c | 226 ---
arch/arm/mach-dove/pm.h | 58 -
arch/arm/mach-footbridge/Kconfig | 57 -
arch/arm/mach-footbridge/Makefile | 18 -
arch/arm/mach-footbridge/common.c | 280 ---
arch/arm/mach-footbridge/common.h | 15 -
arch/arm/mach-footbridge/dc21285-timer.c | 136 --
arch/arm/mach-footbridge/dc21285.c | 360 ----
arch/arm/mach-footbridge/dma-isa.c | 230 ---
arch/arm/mach-footbridge/ebsa285-pci.c | 48 -
arch/arm/mach-footbridge/ebsa285.c | 124 --
.../mach-footbridge/include/mach/hardware.h | 90 -
arch/arm/mach-footbridge/include/mach/irqs.h | 97 -
.../mach-footbridge/include/mach/isa-dma.h | 18 -
.../arm/mach-footbridge/include/mach/memory.h | 26 -
.../mach-footbridge/include/mach/uncompress.h | 34 -
arch/arm/mach-footbridge/isa-irq.c | 177 --
arch/arm/mach-footbridge/isa-rtc.c | 57 -
arch/arm/mach-footbridge/isa-timer.c | 36 -
arch/arm/mach-footbridge/isa.c | 94 -
arch/arm/mach-footbridge/netwinder-hw.c | 772 -------
arch/arm/mach-footbridge/netwinder-pci.c | 62 -
arch/arm/mach-imx/Kconfig | 38 +-
arch/arm/mach-imx/Makefile | 4 -
arch/arm/mach-imx/common.h | 2 -
arch/arm/mach-imx/cpu-imx31.c | 72 -
arch/arm/mach-imx/mach-imx31.c | 18 -
arch/arm/mach-imx/mach-imx7d-cm4.c | 18 -
arch/arm/mach-imx/mach-imxrt.c | 19 -
arch/arm/mach-imx/mach-vf610.c | 1 -
arch/arm/mach-imx/mm-imx3.c | 44 -
arch/arm/mach-lpc18xx/Makefile | 2 -
arch/arm/mach-lpc18xx/board-dt.c | 19 -
arch/arm/mach-mv78xx0/Kconfig | 27 -
arch/arm/mach-mv78xx0/Makefile | 5 -
arch/arm/mach-mv78xx0/bridge-regs.h | 31 -
arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 183 --
arch/arm/mach-mv78xx0/common.c | 444 ----
arch/arm/mach-mv78xx0/common.h | 54 -
arch/arm/mach-mv78xx0/irq.c | 69 -
arch/arm/mach-mv78xx0/irqs.h | 87 -
arch/arm/mach-mv78xx0/mpp.c | 34 -
arch/arm/mach-mv78xx0/mpp.h | 337 ---
arch/arm/mach-mv78xx0/mv78xx0.h | 134 --
arch/arm/mach-mv78xx0/pcie.c | 280 ---
arch/arm/mach-mvebu/Makefile | 2 -
arch/arm/mach-omap2/Kconfig | 62 +-
arch/arm/mach-omap2/Makefile | 63 +-
arch/arm/mach-omap2/board-generic.c | 34 -
arch/arm/mach-omap2/board-n8x0.c | 512 -----
arch/arm/mach-omap2/clkt2xxx_dpll.c | 56 -
arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 194 --
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 259 ---
arch/arm/mach-omap2/clock.c | 12 +-
arch/arm/mach-omap2/clock2xxx.h | 17 -
arch/arm/mach-omap2/clockdomain.c | 4 +-
arch/arm/mach-omap2/clockdomain.h | 5 -
arch/arm/mach-omap2/clockdomains2420_data.c | 154 --
arch/arm/mach-omap2/clockdomains2430_data.c | 181 --
.../mach-omap2/clockdomains2xxx_3xxx_data.c | 29 +-
arch/arm/mach-omap2/cm-regbits-24xx.h | 51 -
arch/arm/mach-omap2/cm2xxx.c | 302 ---
arch/arm/mach-omap2/cm2xxx.h | 60 -
arch/arm/mach-omap2/cm_common.c | 12 -
arch/arm/mach-omap2/common-board-devices.h | 11 -
arch/arm/mach-omap2/common.h | 12 -
arch/arm/mach-omap2/control.h | 56 -
arch/arm/mach-omap2/display.c | 4 +-
arch/arm/mach-omap2/dma.c | 53 +-
arch/arm/mach-omap2/fb.c | 14 +-
arch/arm/mach-omap2/gpmc.h | 10 -
arch/arm/mach-omap2/i2c.c | 2 +-
arch/arm/mach-omap2/id.c | 80 +-
arch/arm/mach-omap2/io.c | 140 +-
arch/arm/mach-omap2/iomap.h | 46 -
arch/arm/mach-omap2/l3_2xxx.h | 15 -
arch/arm/mach-omap2/l4_2xxx.h | 19 -
arch/arm/mach-omap2/mmc.h | 18 -
arch/arm/mach-omap2/msdi.c | 75 -
arch/arm/mach-omap2/omap2-restart.c | 62 -
arch/arm/mach-omap2/omap24xx.h | 73 -
arch/arm/mach-omap2/omap_hwmod.c | 20 +-
arch/arm/mach-omap2/omap_hwmod.h | 2 -
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 402 ----
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 606 ------
.../omap_hwmod_2xxx_interconnect_data.c | 256 ---
.../mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 668 ------
arch/arm/mach-omap2/omap_hwmod_common_data.h | 66 -
arch/arm/mach-omap2/opp2420_data.c | 131 --
arch/arm/mach-omap2/opp2430_data.c | 136 --
arch/arm/mach-omap2/opp2xxx.h | 430 ----
arch/arm/mach-omap2/pdata-quirks.c | 37 +-
arch/arm/mach-omap2/pm.h | 5 -
arch/arm/mach-omap2/powerdomain.h | 3 -
arch/arm/mach-omap2/powerdomains2xxx_data.c | 134 --
arch/arm/mach-omap2/prcm-common.h | 147 --
arch/arm/mach-omap2/prm-regbits-24xx.h | 39 -
arch/arm/mach-omap2/prm2xxx.c | 229 ---
arch/arm/mach-omap2/prm2xxx.h | 128 --
arch/arm/mach-omap2/prm2xxx_3xxx.c | 1 -
arch/arm/mach-omap2/prm_common.c | 11 -
arch/arm/mach-omap2/sdrc.h | 21 -
arch/arm/mach-omap2/sdrc2xxx.c | 164 --
arch/arm/mach-omap2/sleep24xx.S | 91 -
arch/arm/mach-omap2/soc.h | 59 -
arch/arm/mach-omap2/sram.c | 159 +-
arch/arm/mach-omap2/sram.h | 32 -
arch/arm/mach-omap2/sram242x.S | 317 ---
arch/arm/mach-omap2/sram243x.S | 317 ---
arch/arm/mach-omap2/usb-tusb6010.c | 217 --
arch/arm/mach-omap2/usb-tusb6010.h | 12 -
arch/arm/mach-omap2/voltage.h | 1 -
arch/arm/mach-omap2/voltagedomains2xxx_data.c | 29 -
arch/arm/mach-orion5x/Kconfig | 95 -
arch/arm/mach-orion5x/Makefile | 13 +-
arch/arm/mach-orion5x/board-d2net.c | 2 -
arch/arm/mach-orion5x/board-dt.c | 4 +-
arch/arm/mach-orion5x/board-mss2.c | 1 -
arch/arm/mach-orion5x/board-rd88f5182.c | 1 -
arch/arm/mach-orion5x/common.c | 238 +--
arch/arm/mach-orion5x/common.h | 34 +-
arch/arm/mach-orion5x/dns323-setup.c | 757 -------
arch/arm/mach-orion5x/irq.c | 51 -
arch/arm/mach-orion5x/irqs.h | 9 -
arch/arm/mach-orion5x/kurobox_pro-setup.c | 407 ----
arch/arm/mach-orion5x/mpp.c | 41 -
arch/arm/mach-orion5x/mpp.h | 130 --
arch/arm/mach-orion5x/mv2120-setup.c | 256 ---
arch/arm/mach-orion5x/net2big-setup.c | 444 ----
arch/arm/mach-orion5x/pci.c | 429 +++-
.../arm/mach-orion5x/terastation_pro2-setup.c | 366 ----
arch/arm/mach-orion5x/ts209-setup.c | 331 ---
arch/arm/mach-orion5x/ts409-setup.c | 329 ---
arch/arm/mach-orion5x/ts78xx-fpga.h | 42 -
arch/arm/mach-orion5x/ts78xx-setup.c | 574 ------
arch/arm/mach-orion5x/tsx09-common.c | 129 --
arch/arm/mach-orion5x/tsx09-common.h | 21 -
arch/arm/mach-pxa/Kconfig | 89 -
arch/arm/mach-pxa/Makefile | 8 -
arch/arm/mach-pxa/am200epd.c | 395 ----
arch/arm/mach-pxa/am300epd.c | 296 ---
arch/arm/mach-pxa/devices.c | 705 -------
arch/arm/mach-pxa/devices.h | 68 -
arch/arm/mach-pxa/generic.h | 5 -
arch/arm/mach-pxa/gumstix.c | 237 ---
arch/arm/mach-pxa/gumstix.h | 89 -
arch/arm/mach-pxa/pxa25x.c | 59 -
arch/arm/mach-pxa/pxa27x.c | 77 -
arch/arm/mach-pxa/pxa300.c | 1 -
arch/arm/mach-pxa/pxa320.c | 1 -
arch/arm/mach-pxa/pxa3xx.c | 6 -
arch/arm/mach-pxa/sharpsl_pm.c | 941 ---------
arch/arm/mach-pxa/sharpsl_pm.h | 108 -
arch/arm/mach-pxa/spitz.c | 1174 -----------
arch/arm/mach-pxa/spitz.h | 185 --
arch/arm/mach-pxa/spitz_pm.c | 257 ---
arch/arm/mach-sa1100/Kconfig | 92 -
arch/arm/mach-sa1100/Makefile | 20 -
arch/arm/mach-sa1100/assabet.c | 770 -------
arch/arm/mach-sa1100/clock.c | 145 --
arch/arm/mach-sa1100/collie.c | 447 ----
arch/arm/mach-sa1100/generic.c | 470 -----
arch/arm/mach-sa1100/generic.h | 58 -
arch/arm/mach-sa1100/h3600.c | 134 --
arch/arm/mach-sa1100/h3xxx.c | 305 ---
arch/arm/mach-sa1100/include/mach/SA-1100.h | 1798 -----------------
arch/arm/mach-sa1100/include/mach/assabet.h | 99 -
arch/arm/mach-sa1100/include/mach/bitfield.h | 113 --
arch/arm/mach-sa1100/include/mach/collie.h | 94 -
arch/arm/mach-sa1100/include/mach/generic.h | 1 -
arch/arm/mach-sa1100/include/mach/h3xxx.h | 81 -
arch/arm/mach-sa1100/include/mach/hardware.h | 56 -
arch/arm/mach-sa1100/include/mach/irqs.h | 101 -
.../arm/mach-sa1100/include/mach/jornada720.h | 28 -
arch/arm/mach-sa1100/include/mach/memory.h | 37 -
arch/arm/mach-sa1100/include/mach/mtd-xip.h | 23 -
arch/arm/mach-sa1100/include/mach/neponset.h | 31 -
arch/arm/mach-sa1100/include/mach/reset.h | 18 -
.../arm/mach-sa1100/include/mach/uncompress.h | 52 -
arch/arm/mach-sa1100/jornada720.c | 380 ----
arch/arm/mach-sa1100/jornada720_ssp.c | 202 --
arch/arm/mach-sa1100/neponset.c | 438 ----
arch/arm/mach-sa1100/pm.c | 128 --
arch/arm/mach-sa1100/sleep.S | 143 --
arch/arm/mach-sa1100/ssp.c | 240 ---
arch/arm/mach-stm32/Kconfig | 38 +-
arch/arm/mach-stm32/board-dt.c | 7 -
arch/arm/mach-versatile/Kconfig | 10 -
arch/arm/mach-versatile/Makefile | 3 -
arch/arm/mach-versatile/v2m-mps2.c | 17 -
arch/arm/mm/Kconfig | 2 +-
arch/arm/mm/init.c | 5 -
arch/arm/mm/ioremap.c | 1 -
arch/arm/mm/mmu.c | 16 -
arch/arm/plat-orion/Makefile | 9 -
arch/arm/plat-orion/common.c | 826 --------
arch/arm/plat-orion/gpio.c | 616 ------
arch/arm/plat-orion/include/plat/addr-map.h | 54 -
arch/arm/plat-orion/include/plat/common.h | 104 -
arch/arm/plat-orion/include/plat/irq.h | 15 -
arch/arm/plat-orion/include/plat/mpp.h | 34 -
arch/arm/plat-orion/include/plat/orion-gpio.h | 38 -
arch/arm/plat-orion/include/plat/pcie.h | 34 -
arch/arm/plat-orion/include/plat/time.h | 20 -
arch/arm/plat-orion/irq.c | 39 -
arch/arm/plat-orion/mpp.c | 82 -
arch/arm/plat-orion/pcie.c | 288 ---
arch/arm/plat-orion/time.c | 238 ---
drivers/ata/Kconfig | 3 +-
drivers/crypto/Kconfig | 2 +-
drivers/i2c/busses/Kconfig | 2 +-
drivers/media/platform/ti/omap/Kconfig | 4 +-
drivers/mmc/host/Kconfig | 2 +-
drivers/mtd/nand/onenand/Kconfig | 4 +-
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pci-mvebu.c | 5 -
drivers/phy/marvell/Kconfig | 2 +-
drivers/rtc/Kconfig | 8 +-
drivers/rtc/rtc-sa1100.c | 17 +-
drivers/soc/Makefile | 1 -
drivers/soc/atmel/soc.c | 36 -
drivers/soc/atmel/soc.h | 26 -
drivers/thermal/Kconfig | 2 +-
drivers/video/console/Kconfig | 6 +-
drivers/video/console/dummycon.c | 6 -
drivers/video/fbdev/cyber2000fb.c | 10 -
drivers/video/fbdev/omap2/omapfb/Kconfig | 2 +-
drivers/watchdog/Kconfig | 14 +-
include/linux/clk/ti.h | 8 -
sound/soc/kirkwood/Kconfig | 2 +-
381 files changed, 567 insertions(+), 55511 deletions(-)
delete mode 100644 Documentation/arch/arm/netwinder.rst
delete mode 100644 Documentation/arch/arm/sa1100/assabet.rst
delete mode 100644 Documentation/arch/arm/sa1100/cerf.rst
delete mode 100644 Documentation/arch/arm/sa1100/index.rst
delete mode 100644 Documentation/arch/arm/sa1100/lart.rst
delete mode 100644 Documentation/arch/arm/sa1100/serial_uart.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32f429-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32f746-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32f769-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32h743-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32h750-overview.rst
delete mode 100644 Documentation/devicetree/bindings/arm/axxia.yaml
delete mode 100644 arch/arm/boot/compressed/head-sa1100.S
delete mode 100644 arch/arm/boot/compressed/head-sharpsl.S
delete mode 100644 arch/arm/boot/dts/arm/mps2-an385.dts
delete mode 100644 arch/arm/boot/dts/arm/mps2-an399.dts
delete mode 100644 arch/arm/boot/dts/arm/mps2.dtsi
delete mode 100644 arch/arm/boot/dts/intel/axm/Makefile
delete mode 100644 arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts
delete mode 100644 arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi
delete mode 100644 arch/arm/boot/dts/intel/axm/axm55xx.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31-bug.dts
delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31-lite.dts
delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32429i-eval.dts
delete mode 100644 arch/arm/boot/dts/st/stm32746g-eval.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f429-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f429.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f469-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f469.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f746-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f746.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f769-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f769.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h743.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h743i-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32h743i-eval.dts
delete mode 100644 arch/arm/boot/dts/st/stm32h747i-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32h750.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h750i-art-pi.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-h4.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n800.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n810.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430-sdp.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi
delete mode 100644 arch/arm/common/locomo.c
delete mode 100644 arch/arm/common/sa1111.c
delete mode 100644 arch/arm/common/scoop.c
delete mode 100644 arch/arm/common/sharpsl_param.c
delete mode 100644 arch/arm/configs/am200epdkit_defconfig
delete mode 100644 arch/arm/configs/assabet_defconfig
delete mode 100644 arch/arm/configs/axm55xx_defconfig
delete mode 100644 arch/arm/configs/collie_defconfig
delete mode 100644 arch/arm/configs/dove_defconfig
delete mode 100644 arch/arm/configs/footbridge_defconfig
delete mode 100644 arch/arm/configs/h3600_defconfig
delete mode 100644 arch/arm/configs/imxrt_defconfig
delete mode 100644 arch/arm/configs/jornada720_defconfig
delete mode 100644 arch/arm/configs/lpc18xx_defconfig
delete mode 100644 arch/arm/configs/mps2_defconfig
delete mode 100644 arch/arm/configs/mv78xx0_defconfig
delete mode 100644 arch/arm/configs/neponset_defconfig
delete mode 100644 arch/arm/configs/netwinder_defconfig
delete mode 100644 arch/arm/configs/spitz_defconfig
delete mode 100644 arch/arm/configs/stm32_defconfig
delete mode 100644 arch/arm/configs/vf610m4_defconfig
delete mode 100644 arch/arm/include/asm/hardware/dec21285.h
delete mode 100644 arch/arm/include/asm/hardware/locomo.h
delete mode 100644 arch/arm/include/asm/hardware/sa1111.h
delete mode 100644 arch/arm/include/asm/hardware/scoop.h
delete mode 100644 arch/arm/include/asm/hardware/ssp.h
delete mode 100644 arch/arm/include/asm/mach/pci.h
delete mode 100644 arch/arm/include/asm/mach/sharpsl_param.h
delete mode 100644 arch/arm/include/debug/dc21285.S
delete mode 100644 arch/arm/include/debug/sa1100.S
delete mode 100644 arch/arm/mach-at91/samv7.c
delete mode 100644 arch/arm/mach-axxia/Kconfig
delete mode 100644 arch/arm/mach-axxia/Makefile
delete mode 100644 arch/arm/mach-axxia/axxia.c
delete mode 100644 arch/arm/mach-axxia/platsmp.c
delete mode 100644 arch/arm/mach-dove/Kconfig
delete mode 100644 arch/arm/mach-dove/Makefile
delete mode 100644 arch/arm/mach-dove/bridge-regs.h
delete mode 100644 arch/arm/mach-dove/cm-a510.c
delete mode 100644 arch/arm/mach-dove/common.c
delete mode 100644 arch/arm/mach-dove/common.h
delete mode 100644 arch/arm/mach-dove/dove.h
delete mode 100644 arch/arm/mach-dove/irq.c
delete mode 100644 arch/arm/mach-dove/irqs.h
delete mode 100644 arch/arm/mach-dove/mpp.c
delete mode 100644 arch/arm/mach-dove/mpp.h
delete mode 100644 arch/arm/mach-dove/pcie.c
delete mode 100644 arch/arm/mach-dove/pm.h
delete mode 100644 arch/arm/mach-footbridge/Kconfig
delete mode 100644 arch/arm/mach-footbridge/Makefile
delete mode 100644 arch/arm/mach-footbridge/common.c
delete mode 100644 arch/arm/mach-footbridge/common.h
delete mode 100644 arch/arm/mach-footbridge/dc21285-timer.c
delete mode 100644 arch/arm/mach-footbridge/dc21285.c
delete mode 100644 arch/arm/mach-footbridge/dma-isa.c
delete mode 100644 arch/arm/mach-footbridge/ebsa285-pci.c
delete mode 100644 arch/arm/mach-footbridge/ebsa285.c
delete mode 100644 arch/arm/mach-footbridge/include/mach/hardware.h
delete mode 100644 arch/arm/mach-footbridge/include/mach/irqs.h
delete mode 100644 arch/arm/mach-footbridge/include/mach/isa-dma.h
delete mode 100644 arch/arm/mach-footbridge/include/mach/memory.h
delete mode 100644 arch/arm/mach-footbridge/include/mach/uncompress.h
delete mode 100644 arch/arm/mach-footbridge/isa-irq.c
delete mode 100644 arch/arm/mach-footbridge/isa-rtc.c
delete mode 100644 arch/arm/mach-footbridge/isa-timer.c
delete mode 100644 arch/arm/mach-footbridge/isa.c
delete mode 100644 arch/arm/mach-footbridge/netwinder-hw.c
delete mode 100644 arch/arm/mach-footbridge/netwinder-pci.c
delete mode 100644 arch/arm/mach-imx/cpu-imx31.c
delete mode 100644 arch/arm/mach-imx/mach-imx31.c
delete mode 100644 arch/arm/mach-imx/mach-imx7d-cm4.c
delete mode 100644 arch/arm/mach-imx/mach-imxrt.c
delete mode 100644 arch/arm/mach-lpc18xx/Makefile
delete mode 100644 arch/arm/mach-lpc18xx/board-dt.c
delete mode 100644 arch/arm/mach-mv78xx0/Kconfig
delete mode 100644 arch/arm/mach-mv78xx0/Makefile
delete mode 100644 arch/arm/mach-mv78xx0/bridge-regs.h
delete mode 100644 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
delete mode 100644 arch/arm/mach-mv78xx0/common.c
delete mode 100644 arch/arm/mach-mv78xx0/common.h
delete mode 100644 arch/arm/mach-mv78xx0/irq.c
delete mode 100644 arch/arm/mach-mv78xx0/irqs.h
delete mode 100644 arch/arm/mach-mv78xx0/mpp.c
delete mode 100644 arch/arm/mach-mv78xx0/mpp.h
delete mode 100644 arch/arm/mach-mv78xx0/mv78xx0.h
delete mode 100644 arch/arm/mach-mv78xx0/pcie.c
delete mode 100644 arch/arm/mach-omap2/board-n8x0.c
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_dpllcore.c
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
delete mode 100644 arch/arm/mach-omap2/clock2xxx.h
delete mode 100644 arch/arm/mach-omap2/clockdomains2420_data.c
delete mode 100644 arch/arm/mach-omap2/clockdomains2430_data.c
delete mode 100644 arch/arm/mach-omap2/cm-regbits-24xx.h
delete mode 100644 arch/arm/mach-omap2/cm2xxx.c
delete mode 100644 arch/arm/mach-omap2/cm2xxx.h
delete mode 100644 arch/arm/mach-omap2/common-board-devices.h
delete mode 100644 arch/arm/mach-omap2/gpmc.h
delete mode 100644 arch/arm/mach-omap2/l3_2xxx.h
delete mode 100644 arch/arm/mach-omap2/l4_2xxx.h
delete mode 100644 arch/arm/mach-omap2/mmc.h
delete mode 100644 arch/arm/mach-omap2/msdi.c
delete mode 100644 arch/arm/mach-omap2/omap2-restart.c
delete mode 100644 arch/arm/mach-omap2/omap24xx.h
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2420_data.c
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2430_data.c
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
delete mode 100644 arch/arm/mach-omap2/opp2420_data.c
delete mode 100644 arch/arm/mach-omap2/opp2430_data.c
delete mode 100644 arch/arm/mach-omap2/opp2xxx.h
delete mode 100644 arch/arm/mach-omap2/powerdomains2xxx_data.c
delete mode 100644 arch/arm/mach-omap2/prm-regbits-24xx.h
delete mode 100644 arch/arm/mach-omap2/prm2xxx.c
delete mode 100644 arch/arm/mach-omap2/prm2xxx.h
delete mode 100644 arch/arm/mach-omap2/sdrc2xxx.c
delete mode 100644 arch/arm/mach-omap2/sleep24xx.S
delete mode 100644 arch/arm/mach-omap2/sram242x.S
delete mode 100644 arch/arm/mach-omap2/sram243x.S
delete mode 100644 arch/arm/mach-omap2/usb-tusb6010.c
delete mode 100644 arch/arm/mach-omap2/usb-tusb6010.h
delete mode 100644 arch/arm/mach-omap2/voltagedomains2xxx_data.c
delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c
delete mode 100644 arch/arm/mach-orion5x/irq.c
delete mode 100644 arch/arm/mach-orion5x/kurobox_pro-setup.c
delete mode 100644 arch/arm/mach-orion5x/mpp.c
delete mode 100644 arch/arm/mach-orion5x/mpp.h
delete mode 100644 arch/arm/mach-orion5x/mv2120-setup.c
delete mode 100644 arch/arm/mach-orion5x/net2big-setup.c
delete mode 100644 arch/arm/mach-orion5x/terastation_pro2-setup.c
delete mode 100644 arch/arm/mach-orion5x/ts209-setup.c
delete mode 100644 arch/arm/mach-orion5x/ts409-setup.c
delete mode 100644 arch/arm/mach-orion5x/ts78xx-fpga.h
delete mode 100644 arch/arm/mach-orion5x/ts78xx-setup.c
delete mode 100644 arch/arm/mach-orion5x/tsx09-common.c
delete mode 100644 arch/arm/mach-orion5x/tsx09-common.h
delete mode 100644 arch/arm/mach-pxa/am200epd.c
delete mode 100644 arch/arm/mach-pxa/am300epd.c
delete mode 100644 arch/arm/mach-pxa/devices.h
delete mode 100644 arch/arm/mach-pxa/gumstix.c
delete mode 100644 arch/arm/mach-pxa/gumstix.h
delete mode 100644 arch/arm/mach-pxa/sharpsl_pm.c
delete mode 100644 arch/arm/mach-pxa/sharpsl_pm.h
delete mode 100644 arch/arm/mach-pxa/spitz.c
delete mode 100644 arch/arm/mach-pxa/spitz.h
delete mode 100644 arch/arm/mach-pxa/spitz_pm.c
delete mode 100644 arch/arm/mach-sa1100/Kconfig
delete mode 100644 arch/arm/mach-sa1100/Makefile
delete mode 100644 arch/arm/mach-sa1100/assabet.c
delete mode 100644 arch/arm/mach-sa1100/clock.c
delete mode 100644 arch/arm/mach-sa1100/collie.c
delete mode 100644 arch/arm/mach-sa1100/generic.c
delete mode 100644 arch/arm/mach-sa1100/generic.h
delete mode 100644 arch/arm/mach-sa1100/h3600.c
delete mode 100644 arch/arm/mach-sa1100/h3xxx.c
delete mode 100644 arch/arm/mach-sa1100/include/mach/SA-1100.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/assabet.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/bitfield.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/collie.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/generic.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/h3xxx.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/hardware.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/irqs.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/jornada720.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/memory.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/mtd-xip.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/neponset.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/reset.h
delete mode 100644 arch/arm/mach-sa1100/include/mach/uncompress.h
delete mode 100644 arch/arm/mach-sa1100/jornada720.c
delete mode 100644 arch/arm/mach-sa1100/jornada720_ssp.c
delete mode 100644 arch/arm/mach-sa1100/neponset.c
delete mode 100644 arch/arm/mach-sa1100/pm.c
delete mode 100644 arch/arm/mach-sa1100/sleep.S
delete mode 100644 arch/arm/mach-sa1100/ssp.c
delete mode 100644 arch/arm/mach-versatile/v2m-mps2.c
delete mode 100644 arch/arm/plat-orion/Makefile
delete mode 100644 arch/arm/plat-orion/common.c
delete mode 100644 arch/arm/plat-orion/gpio.c
delete mode 100644 arch/arm/plat-orion/include/plat/addr-map.h
delete mode 100644 arch/arm/plat-orion/include/plat/common.h
delete mode 100644 arch/arm/plat-orion/include/plat/irq.h
delete mode 100644 arch/arm/plat-orion/include/plat/mpp.h
delete mode 100644 arch/arm/plat-orion/include/plat/orion-gpio.h
delete mode 100644 arch/arm/plat-orion/include/plat/pcie.h
delete mode 100644 arch/arm/plat-orion/include/plat/time.h
delete mode 100644 arch/arm/plat-orion/irq.c
delete mode 100644 arch/arm/plat-orion/mpp.c
delete mode 100644 arch/arm/plat-orion/pcie.c
delete mode 100644 arch/arm/plat-orion/time.c
--
2.53.0
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Frank Li <Frank.Li@nxp.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Andreas Kemnade <andreas@kemnade.info>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Roger Quadros <rogerq@kernel.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Kristoffer Ericson <kristoffer.ericson@gmail.com>
Cc: Linus Walleij <linusw@kernel.org>
Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Karl Mehltretter <kmehltretter@gmail.com>
Cc: "David Hildenbrand (Arm)" <david@kernel.org>
Cc: Nicolas Pitre <npitre@baylibre.com>
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: imx@lists.linux.dev
Cc: linux-stm32@st-md-mailman.stormreply.com
Cc: linux-omap@vger.kernel.org
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 06/14] ARM: omap2: remove omap24xx support
2026-09-14 14:08 [PATCH v2 00/14] ARM: deprecated platform removal Arnd Bergmann
@ 2026-09-14 14:08 ` Arnd Bergmann
2026-09-21 16:06 ` Kevin Hilman
2026-09-14 14:08 ` [PATCH v2 07/14] ARM: imx: remove i.MX31 SoC support Arnd Bergmann
` (6 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Arnd Bergmann @ 2026-09-14 14:08 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, Andreas Kemnade, Kevin Hilman, Roger Quadros,
Tony Lindgren, Paul Walmsley, Herbert Xu, David S. Miller,
Mauro Carvalho Chehab, Kyungmin Park, Helge Deller, Tero Kristo,
Stephen Boyd, linux-kernel, linux-omap, devicetree, linux-media,
linux-mtd, linux-fbdev, dri-devel, linux-clk, Thomas Zimmermann,
Aaro Koskinen
From: Arnd Bergmann <arnd@arndb.de>
The omap24xx SoC platform was used in the Nokia N800 and N810 tablets
released on 2007 and was among the first ARMv6 CPUs in products that
made it into products.
Unfortunately the early ARM1136r0 CPU cores had a number of quirks that
caused a disproportionate amount of work to keep them compatible with
later ARMv6K/v7/v8 implementations.
Drop the support for this SoC in order to allow removing ARM1136r0.
Cc: Andreas Kemnade <andreas@kemnade.info>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Roger Quadros <rogerq@kernel.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Helge Deller <deller@gmx.de>
Cc: Tero Kristo <kristo@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-media@vger.kernel.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-fbdev@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-clk@vger.kernel.org
Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> # omapfb
Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
I have follow-up patches to remove platform_data probing in
OMAP2+ specific driver and patches to remove the now orphaned
menelaus mfd omap2 clk support. I'll post these separately.
---
MAINTAINERS | 2 -
arch/arm/boot/dts/ti/omap/Makefile | 6 -
arch/arm/boot/dts/ti/omap/omap2.dtsi | 338 -----
.../arm/boot/dts/ti/omap/omap2420-clocks.dtsi | 267 ----
arch/arm/boot/dts/ti/omap/omap2420-h4.dts | 63 -
arch/arm/boot/dts/ti/omap/omap2420-n800.dts | 9 -
.../boot/dts/ti/omap/omap2420-n810-wimax.dts | 9 -
arch/arm/boot/dts/ti/omap/omap2420-n810.dts | 75 -
.../dts/ti/omap/omap2420-n8x0-common.dtsi | 123 --
arch/arm/boot/dts/ti/omap/omap2420.dtsi | 262 ----
.../arm/boot/dts/ti/omap/omap2430-clocks.dtsi | 341 -----
arch/arm/boot/dts/ti/omap/omap2430-sdp.dts | 70 -
arch/arm/boot/dts/ti/omap/omap2430.dtsi | 366 -----
.../arm/boot/dts/ti/omap/omap24xx-clocks.dtsi | 1241 -----------------
arch/arm/configs/omap2plus_defconfig | 4 -
arch/arm/mach-omap2/Kconfig | 62 +-
arch/arm/mach-omap2/Makefile | 63 +-
arch/arm/mach-omap2/board-generic.c | 34 -
arch/arm/mach-omap2/board-n8x0.c | 512 -------
arch/arm/mach-omap2/clkt2xxx_dpll.c | 56 -
arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 194 ---
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 259 ----
arch/arm/mach-omap2/clock.c | 12 +-
arch/arm/mach-omap2/clock2xxx.h | 17 -
arch/arm/mach-omap2/clockdomain.c | 4 +-
arch/arm/mach-omap2/clockdomain.h | 5 -
arch/arm/mach-omap2/clockdomains2420_data.c | 154 --
arch/arm/mach-omap2/clockdomains2430_data.c | 181 ---
.../mach-omap2/clockdomains2xxx_3xxx_data.c | 29 +-
arch/arm/mach-omap2/cm-regbits-24xx.h | 51 -
arch/arm/mach-omap2/cm2xxx.c | 302 ----
arch/arm/mach-omap2/cm2xxx.h | 60 -
arch/arm/mach-omap2/cm_common.c | 12 -
arch/arm/mach-omap2/common-board-devices.h | 11 -
arch/arm/mach-omap2/common.h | 12 -
arch/arm/mach-omap2/control.h | 56 -
arch/arm/mach-omap2/display.c | 4 +-
arch/arm/mach-omap2/dma.c | 53 +-
arch/arm/mach-omap2/fb.c | 14 +-
arch/arm/mach-omap2/gpmc.h | 10 -
arch/arm/mach-omap2/i2c.c | 2 +-
arch/arm/mach-omap2/id.c | 80 +-
arch/arm/mach-omap2/io.c | 140 +-
arch/arm/mach-omap2/iomap.h | 46 -
arch/arm/mach-omap2/l3_2xxx.h | 15 -
arch/arm/mach-omap2/l4_2xxx.h | 19 -
arch/arm/mach-omap2/mmc.h | 18 -
arch/arm/mach-omap2/msdi.c | 75 -
arch/arm/mach-omap2/omap2-restart.c | 62 -
arch/arm/mach-omap2/omap24xx.h | 73 -
arch/arm/mach-omap2/omap_hwmod.c | 20 +-
arch/arm/mach-omap2/omap_hwmod.h | 2 -
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 402 ------
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 606 --------
.../omap_hwmod_2xxx_interconnect_data.c | 256 ----
.../mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 668 ---------
arch/arm/mach-omap2/omap_hwmod_common_data.h | 66 -
arch/arm/mach-omap2/opp2420_data.c | 131 --
arch/arm/mach-omap2/opp2430_data.c | 136 --
arch/arm/mach-omap2/opp2xxx.h | 430 ------
arch/arm/mach-omap2/pdata-quirks.c | 37 +-
arch/arm/mach-omap2/pm.h | 5 -
arch/arm/mach-omap2/powerdomain.h | 3 -
arch/arm/mach-omap2/powerdomains2xxx_data.c | 134 --
arch/arm/mach-omap2/prcm-common.h | 147 --
arch/arm/mach-omap2/prm-regbits-24xx.h | 39 -
arch/arm/mach-omap2/prm2xxx.c | 229 ---
arch/arm/mach-omap2/prm2xxx.h | 128 --
arch/arm/mach-omap2/prm2xxx_3xxx.c | 1 -
arch/arm/mach-omap2/prm_common.c | 11 -
arch/arm/mach-omap2/sdrc.h | 21 -
arch/arm/mach-omap2/sdrc2xxx.c | 164 ---
arch/arm/mach-omap2/sleep24xx.S | 91 --
arch/arm/mach-omap2/soc.h | 59 -
arch/arm/mach-omap2/sram.c | 159 +--
arch/arm/mach-omap2/sram.h | 32 -
arch/arm/mach-omap2/sram242x.S | 317 -----
arch/arm/mach-omap2/sram243x.S | 317 -----
arch/arm/mach-omap2/usb-tusb6010.c | 217 ---
arch/arm/mach-omap2/usb-tusb6010.h | 12 -
arch/arm/mach-omap2/voltage.h | 1 -
arch/arm/mach-omap2/voltagedomains2xxx_data.c | 29 -
drivers/crypto/Kconfig | 2 +-
drivers/media/platform/ti/omap/Kconfig | 4 +-
drivers/mtd/nand/onenand/Kconfig | 4 +-
drivers/video/fbdev/omap2/omapfb/Kconfig | 2 +-
include/linux/clk/ti.h | 8 -
87 files changed, 62 insertions(+), 10701 deletions(-)
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-h4.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n800.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n810.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2420.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430-sdp.dts
delete mode 100644 arch/arm/boot/dts/ti/omap/omap2430.dtsi
delete mode 100644 arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi
delete mode 100644 arch/arm/mach-omap2/board-n8x0.c
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_dpllcore.c
delete mode 100644 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
delete mode 100644 arch/arm/mach-omap2/clock2xxx.h
delete mode 100644 arch/arm/mach-omap2/clockdomains2420_data.c
delete mode 100644 arch/arm/mach-omap2/clockdomains2430_data.c
delete mode 100644 arch/arm/mach-omap2/cm-regbits-24xx.h
delete mode 100644 arch/arm/mach-omap2/cm2xxx.c
delete mode 100644 arch/arm/mach-omap2/cm2xxx.h
delete mode 100644 arch/arm/mach-omap2/common-board-devices.h
delete mode 100644 arch/arm/mach-omap2/gpmc.h
delete mode 100644 arch/arm/mach-omap2/l3_2xxx.h
delete mode 100644 arch/arm/mach-omap2/l4_2xxx.h
delete mode 100644 arch/arm/mach-omap2/mmc.h
delete mode 100644 arch/arm/mach-omap2/msdi.c
delete mode 100644 arch/arm/mach-omap2/omap2-restart.c
delete mode 100644 arch/arm/mach-omap2/omap24xx.h
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2420_data.c
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2430_data.c
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
delete mode 100644 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
delete mode 100644 arch/arm/mach-omap2/opp2420_data.c
delete mode 100644 arch/arm/mach-omap2/opp2430_data.c
delete mode 100644 arch/arm/mach-omap2/opp2xxx.h
delete mode 100644 arch/arm/mach-omap2/powerdomains2xxx_data.c
delete mode 100644 arch/arm/mach-omap2/prm-regbits-24xx.h
delete mode 100644 arch/arm/mach-omap2/prm2xxx.c
delete mode 100644 arch/arm/mach-omap2/prm2xxx.h
delete mode 100644 arch/arm/mach-omap2/sdrc2xxx.c
delete mode 100644 arch/arm/mach-omap2/sleep24xx.S
delete mode 100644 arch/arm/mach-omap2/sram242x.S
delete mode 100644 arch/arm/mach-omap2/sram243x.S
delete mode 100644 arch/arm/mach-omap2/usb-tusb6010.c
delete mode 100644 arch/arm/mach-omap2/usb-tusb6010.h
delete mode 100644 arch/arm/mach-omap2/voltagedomains2xxx_data.c
diff --git a/MAINTAINERS b/MAINTAINERS
index ab572953735d..4522bde3f92e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19886,7 +19886,6 @@ M: Jarkko Nikula <jarkko.nikula@bitmer.com>
L: linux-sound@vger.kernel.org
L: linux-omap@vger.kernel.org
S: Maintained
-F: sound/soc/ti/n810.c
F: sound/soc/ti/omap*
F: sound/soc/ti/rx51.c
F: sound/soc/ti/sdma-pcm.*
@@ -19926,7 +19925,6 @@ M: Roger Quadros <rogerq@kernel.org>
M: Tony Lindgren <tony@atomide.com>
L: linux-omap@vger.kernel.org
S: Maintained
-F: arch/arm/mach-omap2/*gpmc*
F: drivers/memory/omap-gpmc.c
OMAP GPIO DRIVER
diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile
index 498c36ccb5ea..3c5d378df6b9 100644
--- a/arch/arm/boot/dts/ti/omap/Makefile
+++ b/arch/arm/boot/dts/ti/omap/Makefile
@@ -1,10 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_OMAP2) += \
- omap2420-h4.dtb \
- omap2420-n800.dtb \
- omap2420-n810.dtb \
- omap2420-n810-wimax.dtb \
- omap2430-sdp.dtb
dtb-$(CONFIG_ARCH_OMAP3) += \
am3517-craneboard.dtb \
am3517-evm.dtb \
diff --git a/arch/arm/boot/dts/ti/omap/omap2.dtsi b/arch/arm/boot/dts/ti/omap/omap2.dtsi
deleted file mode 100644
index fdc1790adf43..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2.dtsi
+++ /dev/null
@@ -1,338 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP2 SoC
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/bus/ti-sysc.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/omap.h>
-
-/ {
- compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
-
- aliases {
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- };
-
- cpus {
- #address-cells = <0>;
- #size-cells = <0>;
-
- cpu {
- compatible = "arm,arm1136jf-s";
- device_type = "cpu";
- };
- };
-
- pmu {
- compatible = "arm,arm1136-pmu";
- interrupts = <3>;
- };
-
- soc {
- compatible = "ti,omap-infra";
- mpu {
- compatible = "ti,omap2-mpu";
- ti,hwmods = "mpu";
- };
- };
-
- ocp {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "l3_main";
-
- aes: aes@480a6000 {
- compatible = "ti,omap2-aes";
- ti,hwmods = "aes";
- reg = <0x480a6000 0x50>;
- dmas = <&sdma 9 &sdma 10>;
- dma-names = "tx", "rx";
- };
-
- hdq1w: 1w@480b2000 {
- compatible = "ti,omap2420-1w";
- ti,hwmods = "hdq1w";
- reg = <0x480b2000 0x1000>;
- interrupts = <58>;
- };
-
- intc: interrupt-controller@1 {
- compatible = "ti,omap2-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x480FE000 0x1000>;
- };
-
- target-module@48056000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x48056000 0x4>,
- <0x4805602c 0x4>,
- <0x48056028 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- clocks = <&core_l3_ck>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x48056000 0x1000>;
-
- sdma: dma-controller@0 {
- compatible = "ti,omap2420-sdma", "ti,omap-sdma";
- reg = <0 0x1000>;
- interrupts = <12>,
- <13>,
- <14>,
- <15>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <64>;
- };
- };
-
- i2c1: i2c@48070000 {
- compatible = "ti,omap2-i2c";
- ti,hwmods = "i2c1";
- reg = <0x48070000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <56>;
- };
-
- i2c2: i2c@48072000 {
- compatible = "ti,omap2-i2c";
- ti,hwmods = "i2c2";
- reg = <0x48072000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <57>;
- };
-
- mcspi1: spi@48098000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,omap2-mcspi";
- ti,hwmods = "mcspi1";
- reg = <0x48098000 0x100>;
- interrupts = <65>;
- dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
- &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
- dma-names = "tx0", "rx0", "tx1", "rx1",
- "tx2", "rx2", "tx3", "rx3";
- };
-
- mcspi2: spi@4809a000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,omap2-mcspi";
- ti,hwmods = "mcspi2";
- reg = <0x4809a000 0x100>;
- interrupts = <66>;
- dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
-
- rng: rng@480a0000 {
- compatible = "ti,omap2-rng";
- ti,hwmods = "rng";
- reg = <0x480a0000 0x50>;
- interrupts = <52>;
- };
-
- sham: sham@480a4000 {
- compatible = "ti,omap2-sham";
- ti,hwmods = "sham";
- reg = <0x480a4000 0x64>;
- interrupts = <51>;
- dmas = <&sdma 13>;
- dma-names = "rx";
- };
-
- uart1: serial@4806a000 {
- compatible = "ti,omap2-uart";
- ti,hwmods = "uart1";
- reg = <0x4806a000 0x2000>;
- interrupts = <72>;
- dmas = <&sdma 49 &sdma 50>;
- dma-names = "tx", "rx";
- clock-frequency = <48000000>;
- };
-
- uart2: serial@4806c000 {
- compatible = "ti,omap2-uart";
- ti,hwmods = "uart2";
- reg = <0x4806c000 0x400>;
- interrupts = <73>;
- dmas = <&sdma 51 &sdma 52>;
- dma-names = "tx", "rx";
- clock-frequency = <48000000>;
- };
-
- uart3: serial@4806e000 {
- compatible = "ti,omap2-uart";
- ti,hwmods = "uart3";
- reg = <0x4806e000 0x400>;
- interrupts = <74>;
- dmas = <&sdma 53 &sdma 54>;
- dma-names = "tx", "rx";
- clock-frequency = <48000000>;
- };
-
- timer2_target: target-module@4802a000 {
- compatible = "ti,sysc-omap2-timer", "ti,sysc";
- reg = <0x4802a000 0x4>,
- <0x4802a010 0x4>,
- <0x4802a014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- clocks = <&gpt2_fck>, <&gpt2_ick>;
- clock-names = "fck", "ick";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4802a000 0x1000>;
-
- timer2: timer@0 {
- compatible = "ti,omap2420-timer";
- reg = <0 0x400>;
- interrupts = <38>;
- };
- };
-
- timer3: timer@48078000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48078000 0x400>;
- interrupts = <39>;
- ti,hwmods = "timer3";
- };
-
- timer4: timer@4807a000 {
- compatible = "ti,omap2420-timer";
- reg = <0x4807a000 0x400>;
- interrupts = <40>;
- ti,hwmods = "timer4";
- };
-
- timer5: timer@4807c000 {
- compatible = "ti,omap2420-timer";
- reg = <0x4807c000 0x400>;
- interrupts = <41>;
- ti,hwmods = "timer5";
- ti,timer-dsp;
- };
-
- timer6: timer@4807e000 {
- compatible = "ti,omap2420-timer";
- reg = <0x4807e000 0x400>;
- interrupts = <42>;
- ti,hwmods = "timer6";
- ti,timer-dsp;
- };
-
- timer7: timer@48080000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48080000 0x400>;
- interrupts = <43>;
- ti,hwmods = "timer7";
- ti,timer-dsp;
- };
-
- timer8: timer@48082000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48082000 0x400>;
- interrupts = <44>;
- ti,hwmods = "timer8";
- ti,timer-dsp;
- };
-
- timer9: timer@48084000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48084000 0x400>;
- interrupts = <45>;
- ti,hwmods = "timer9";
- ti,timer-pwm;
- };
-
- timer10: timer@48086000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48086000 0x400>;
- interrupts = <46>;
- ti,hwmods = "timer10";
- ti,timer-pwm;
- };
-
- timer11: timer@48088000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48088000 0x400>;
- interrupts = <47>;
- ti,hwmods = "timer11";
- ti,timer-pwm;
- };
-
- timer12: timer@4808a000 {
- compatible = "ti,omap2420-timer";
- reg = <0x4808a000 0x400>;
- interrupts = <48>;
- ti,hwmods = "timer12";
- ti,timer-pwm;
- };
-
- dss: dss@48050000 {
- compatible = "ti,omap2-dss";
- reg = <0x48050000 0x400>;
- status = "disabled";
- ti,hwmods = "dss_core";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- dispc@48050400 {
- compatible = "ti,omap2-dispc";
- reg = <0x48050400 0x400>;
- interrupts = <25>;
- ti,hwmods = "dss_dispc";
- };
-
- rfbi: encoder@48050800 {
- compatible = "ti,omap2-rfbi";
- reg = <0x48050800 0x400>;
- status = "disabled";
- ti,hwmods = "dss_rfbi";
- };
-
- venc: encoder@48050c00 {
- compatible = "ti,omap2-venc";
- reg = <0x48050c00 0x400>;
- status = "disabled";
- ti,hwmods = "dss_venc";
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi
deleted file mode 100644
index 00a7a199a91c..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi
+++ /dev/null
@@ -1,267 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP2420 clock data
- *
- * Copyright (C) 2014 Texas Instruments, Inc.
- */
-
-&prcm_clocks {
- sys_clkout2_src_gate: sys_clkout2_src_gate@70 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <15>;
- reg = <0x0070>;
- };
-
- sys_clkout2_src_mux: sys_clkout2_src_mux@70 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
- ti,bit-shift = <8>;
- reg = <0x0070>;
- };
-
- sys_clkout2_src: sys_clkout2_src {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
- };
-
- sys_clkout2: sys_clkout2@70 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sys_clkout2_src>;
- ti,bit-shift = <11>;
- ti,max-div = <64>;
- reg = <0x0070>;
- ti,index-power-of-two;
- };
-
- dsp_gate_ick: dsp_gate_ick@810 {
- #clock-cells = <0>;
- compatible = "ti,composite-interface-clock";
- clocks = <&dsp_fck>;
- ti,bit-shift = <1>;
- reg = <0x0810>;
- };
-
- dsp_div_ick: dsp_div_ick@840 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&dsp_fck>;
- ti,bit-shift = <5>;
- ti,max-div = <3>;
- reg = <0x0840>;
- ti,index-starts-at-one;
- };
-
- dsp_ick: dsp_ick {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
- };
-
- iva1_gate_ifck: iva1_gate_ifck@800 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <10>;
- reg = <0x0800>;
- };
-
- iva1_div_ifck: iva1_div_ifck@840 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <8>;
- reg = <0x0840>;
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
- };
-
- iva1_ifck: iva1_ifck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
- };
-
- iva1_ifck_div: iva1_ifck_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&iva1_ifck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&iva1_ifck_div>;
- ti,bit-shift = <8>;
- reg = <0x0800>;
- };
-
- wdt3_ick: wdt3_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <28>;
- reg = <0x0210>;
- };
-
- wdt3_fck: wdt3_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <28>;
- reg = <0x0200>;
- };
-
- mmc_ick: mmc_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <26>;
- reg = <0x0210>;
- };
-
- mmc_fck: mmc_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <26>;
- reg = <0x0200>;
- };
-
- eac_ick: eac_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <24>;
- reg = <0x0210>;
- };
-
- eac_fck: eac_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <24>;
- reg = <0x0200>;
- };
-
- i2c1_fck: i2c1_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_12m_ck>;
- ti,bit-shift = <19>;
- reg = <0x0200>;
- };
-
- i2c2_fck: i2c2_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_12m_ck>;
- ti,bit-shift = <20>;
- reg = <0x0200>;
- };
-
- vlynq_ick: vlynq_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <3>;
- reg = <0x0210>;
- };
-
- vlynq_gate_fck: vlynq_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <3>;
- reg = <0x0200>;
- };
-
- core_d18_ck: core_d18_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <18>;
- };
-
- vlynq_mux_fck: vlynq_mux_fck@240 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
- ti,bit-shift = <15>;
- reg = <0x0240>;
- };
-
- vlynq_fck: vlynq_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
- };
-};
-
-&prcm_clockdomains {
- gfx_clkdm: gfx_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gfx_ick>;
- };
-
- core_l3_clkdm: core_l3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
- };
-
- wkup_clkdm: wkup_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
- <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
- <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
- };
-
- iva1_clkdm: iva1_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&iva1_mpu_int_ifck>;
- };
-
- dss_clkdm: dss_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dss_ick>, <&dss_54m_fck>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
- <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
- <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
- <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
- <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
- <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
- <&uart3_ick>, <&uart3_fck>, <&cam_ick>,
- <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
- <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
- <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
- <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
- <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
- <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
- <&pka_ick>;
- };
-};
-
-&func_96m_ck {
- compatible = "fixed-factor-clock";
- clocks = <&apll96_ck>;
- clock-mult = <1>;
- clock-div = <1>;
-};
-
-&dsp_div_fck {
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
-};
-
-&ssi_ssr_sst_div_fck {
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-h4.dts b/arch/arm/boot/dts/ti/omap/omap2420-h4.dts
deleted file mode 100644
index 5acf5dd87c59..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-h4.dts
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "omap2420.dtsi"
-
-/ {
- model = "TI OMAP2420 H4 board";
- compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x4000000>; /* 64 MB */
- };
-};
-
-&gpmc {
- ranges = <0 0 0x08000000 0x04000000>;
-
- nor@0,0 {
- compatible = "cfi-flash";
- linux,mtd-name = "intel,ge28f256l18b85";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x04000000>;
- bank-width = <2>;
-
- gpmc,mux-add-data = <2>;
- gpmc,cs-on-ns = <10>;
- gpmc,cs-rd-off-ns = <160>;
- gpmc,cs-wr-off-ns = <160>;
- gpmc,adv-on-ns = <20>;
- gpmc,adv-rd-off-ns = <50>;
- gpmc,adv-wr-off-ns = <50>;
- gpmc,oe-on-ns = <60>;
- gpmc,oe-off-ns = <120>;
- gpmc,we-on-ns = <60>;
- gpmc,we-off-ns = <120>;
- gpmc,rd-cycle-ns = <170>;
- gpmc,wr-cycle-ns = <170>;
- gpmc,access-ns = <150>;
- gpmc,page-burst-access-ns = <10>;
-
- partition@0 {
- label = "bootloader";
- reg = <0 0x20000>;
- };
- partition@20000 {
- label = "params";
- reg = <0x20000 0x20000>;
- };
- partition@40000 {
- label = "kernel";
- reg = <0x40000 0x200000>;
- };
- partition@240000 {
- label = "file-system";
- reg = <0x240000 0x3dc0000>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n800.dts b/arch/arm/boot/dts/ti/omap/omap2420-n800.dts
deleted file mode 100644
index f06d767e818b..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-n800.dts
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "omap2420-n8x0-common.dtsi"
-
-/ {
- model = "Nokia N800";
- compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2";
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts
deleted file mode 100644
index ac9acbd609b6..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "omap2420-n8x0-common.dtsi"
-
-/ {
- model = "Nokia N810 WiMax";
- compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2";
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n810.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810.dts
deleted file mode 100644
index 3bf8175d85a8..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-n810.dts
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "omap2420-n8x0-common.dtsi"
-
-/ {
- model = "Nokia N810";
- compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2";
-
- vio_ape: vio_ape {
- compatible = "regulator-fixed";
- regulator-name = "vio_ape";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- v28_aic: v28_aic {
- compatible = "regulator-fixed";
- regulator-name = "v28_aic";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-};
-
-&omap2420_pmx {
- mcbsp2_pins: mcbsp2-pins {
- pinctrl-single,pins = <
- OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT | MUX_MODE1) /* eac_ac_sclk.mcbsp2_clkx */
- OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT | MUX_MODE1) /* eac_ac_fs.mcbsp2_fsx */
- OMAP2420_CORE_IOPAD(0x0126, PIN_INPUT | MUX_MODE1) /* eac_ac_din.mcbsp2_dr */
- OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1) /* eac_ac_dout.mcbsp2_dx */
- >;
- };
-
- aic33_pins: aic33-pins {
- pinctrl-single,pins = <
- OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */
- OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */
- >;
- };
-};
-
-&i2c2 {
- aic33@18 {
- compatible = "ti,tlv320aic33";
- reg = <0x18>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&aic33_pins>;
-
- reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */
-
- ai3x-gpio-func = <
- 10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */
- 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
- >;
- ai3x-micbias-vg = <1>; /* 2V */
-
- AVDD-supply = <&v28_aic>;
- DRVDD-supply = <&v28_aic>;
- IOVDD-supply = <&vio_ape>;
- DVDD-supply = <&vio_ape>;
-
- assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>;
- assigned-clock-parents = <&func_96m_ck>;
- assigned-clock-rates = <0>, <12000000>;
- };
-};
-
-&mcbsp2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp2_pins>;
-
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi
deleted file mode 100644
index fe9dd8bbfc85..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "omap2420.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x8000000>; /* 128 MB */
- };
-
- chosen {
- stdout-path = &uart3;
- };
-
- ocp {
- i2c0 {
- compatible = "i2c-cbus-gpio";
- gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */
- &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */
- &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */
- >;
- #address-cells = <1>;
- #size-cells = <0>;
- retu: retu@1 {
- compatible = "nokia,retu";
- interrupt-parent = <&gpio4>;
- interrupts = <12 IRQ_TYPE_EDGE_RISING>;
- reg = <0x1>;
- };
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
-
- pmic@72 {
- compatible = "menelaus";
- reg = <0x72>;
- interrupts = <7 IRQ_TYPE_EDGE_RISING>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
-};
-
-&gpmc {
- ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
-
- /* gpio-irq for dma: 26 */
-
- onenand@0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "ti,omap2-onenand";
- reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
-
- gpmc,sync-read;
- gpmc,burst-length = <16>;
- gpmc,burst-read;
- gpmc,burst-wrap;
- gpmc,device-width = <2>;
- gpmc,mux-add-data = <2>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <127>;
- gpmc,cs-wr-off-ns = <109>;
- gpmc,adv-on-ns = <0>;
- gpmc,adv-rd-off-ns = <18>;
- gpmc,adv-wr-off-ns = <18>;
- gpmc,oe-on-ns = <27>;
- gpmc,oe-off-ns = <127>;
- gpmc,we-on-ns = <27>;
- gpmc,we-off-ns = <72>;
- gpmc,rd-cycle-ns = <145>;
- gpmc,wr-cycle-ns = <136>;
- gpmc,access-ns = <118>;
- gpmc,page-burst-access-ns = <27>;
- gpmc,bus-turnaround-ns = <0>;
- gpmc,cycle2cycle-delay-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
- gpmc,clk-activation-ns = <9>;
- gpmc,sync-clk-ps = <27000>;
-
- /* MTD partition table corresponding to old board-n8x0 file. */
- partition@0 {
- label = "bootloader";
- reg = <0x00000000 0x00020000>;
- read-only;
- };
- partition@1 {
- label = "config";
- reg = <0x00020000 0x00060000>;
- };
- partition@2 {
- label = "kernel";
- reg = <0x00080000 0x00200000>;
- };
- partition@3 {
- label = "initfs";
- reg = <0x00280000 0x00400000>;
- };
- partition@4 {
- label = "rootfs";
- reg = <0x00680000 0x0f980000>;
- };
- partition@5 {
- label = "omap2-onenand";
- reg = <0x00000000 0x10000000>;
- };
- };
-};
-
-&mcspi2 {
- status = "okay";
-
- wifi@0 {
- reg = <0>;
- compatible = "st,stlc4560";
- spi-max-frequency = <48000000>;
- interrupts-extended = <&gpio3 23 IRQ_TYPE_EDGE_RISING>;
- powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* gpio 97 */
- };
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2420.dtsi b/arch/arm/boot/dts/ti/omap/omap2420.dtsi
deleted file mode 100644
index 821da51cb870..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2420.dtsi
+++ /dev/null
@@ -1,262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP2420 SoC
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "omap2.dtsi"
-
-/ {
- compatible = "ti,omap2420", "ti,omap2";
-
- ocp {
- l4: l4@48000000 {
- compatible = "ti,omap2-l4", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x48000000 0x100000>;
-
- prcm: prcm@8000 {
- compatible = "ti,omap2-prcm";
- reg = <0x8000 0x1000>;
-
- prcm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prcm_clockdomains: clockdomains {
- };
- };
-
- scm: scm@0 {
- compatible = "ti,omap2-scm", "simple-bus";
- reg = <0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- #pinctrl-cells = <1>;
- ranges = <0 0x0 0x1000>;
-
- omap2420_pmx: pinmux@30 {
- compatible = "ti,omap2420-padconf",
- "pinctrl-single";
- reg = <0x30 0x0113>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <8>;
- pinctrl-single,function-mask = <0x3f>;
- };
-
- scm_conf: scm_conf@270 {
- compatible = "syscon";
- reg = <0x270 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- scm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- scm_clockdomains: clockdomains {
- };
- };
-
- target-module@4000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x4000 0x4>,
- <0x4004 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>;
- clocks = <&func_32k_ck>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4000 0x1000>;
-
- counter32k: counter@0 {
- compatible = "ti,omap-counter32k";
- reg = <0 0x20>;
- };
- };
- };
-
- gpio1: gpio@48018000 {
- compatible = "ti,omap2-gpio";
- reg = <0x48018000 0x200>;
- interrupts = <29>;
- ti,hwmods = "gpio1";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio2: gpio@4801a000 {
- compatible = "ti,omap2-gpio";
- reg = <0x4801a000 0x200>;
- interrupts = <30>;
- ti,hwmods = "gpio2";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio3: gpio@4801c000 {
- compatible = "ti,omap2-gpio";
- reg = <0x4801c000 0x200>;
- interrupts = <31>;
- ti,hwmods = "gpio3";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio4: gpio@4801e000 {
- compatible = "ti,omap2-gpio";
- reg = <0x4801e000 0x200>;
- interrupts = <32>;
- ti,hwmods = "gpio4";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpmc: gpmc@6800a000 {
- compatible = "ti,omap2420-gpmc";
- reg = <0x6800a000 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- interrupts = <20>;
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- ti,hwmods = "gpmc";
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- mcbsp1: mcbsp@48074000 {
- compatible = "ti,omap2420-mcbsp";
- reg = <0x48074000 0xff>;
- reg-names = "mpu";
- interrupts = <59>, /* TX interrupt */
- <60>; /* RX interrupt */
- interrupt-names = "tx", "rx";
- ti,hwmods = "mcbsp1";
- dmas = <&sdma 31>,
- <&sdma 32>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mcbsp2: mcbsp@48076000 {
- compatible = "ti,omap2420-mcbsp";
- reg = <0x48076000 0xff>;
- reg-names = "mpu";
- interrupts = <62>, /* TX interrupt */
- <63>; /* RX interrupt */
- interrupt-names = "tx", "rx";
- ti,hwmods = "mcbsp2";
- dmas = <&sdma 33>,
- <&sdma 34>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- msdi1: mmc@4809c000 {
- compatible = "ti,omap2420-mmc";
- ti,hwmods = "msdi1";
- reg = <0x4809c000 0x80>;
- interrupts = <83>;
- dmas = <&sdma 61 &sdma 62>;
- dma-names = "tx", "rx";
- };
-
- mailbox: mailbox@48094000 {
- compatible = "ti,omap2-mailbox";
- reg = <0x48094000 0x200>;
- interrupts = <26>, <34>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <6>;
- mbox_dsp: mbox-dsp {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <1 0 0>;
- };
- mbox_iva: mbox-iva {
- ti,mbox-tx = <2 1 3>;
- ti,mbox-rx = <3 1 3>;
- };
- };
-
- timer1_target: target-module@48028000 {
- compatible = "ti,sysc-omap2-timer", "ti,sysc";
- reg = <0x48028000 0x4>,
- <0x48028010 0x4>,
- <0x48028014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- clocks = <&gpt1_fck>, <&gpt1_ick>;
- clock-names = "fck", "ick";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x48028000 0x1000>;
-
- timer1: timer@0 {
- compatible = "ti,omap2420-timer";
- reg = <0 0x400>;
- interrupts = <37>;
- ti,timer-alwon;
- };
- };
-
- wd_timer2: wdt@48022000 {
- compatible = "ti,omap2-wdt";
- ti,hwmods = "wd_timer2";
- reg = <0x48022000 0x80>;
- };
- };
-};
-
-&i2c1 {
- compatible = "ti,omap2420-i2c";
-};
-
-&i2c2 {
- compatible = "ti,omap2420-i2c";
-};
-
-#include "omap24xx-clocks.dtsi"
-#include "omap2420-clocks.dtsi"
-
-/* Preferred always-on timer for clockevent */
-&timer1_target {
- ti,no-reset-on-init;
- ti,no-idle;
- timer@0 {
- assigned-clocks = <&gpt1_fck>;
- assigned-clock-parents = <&func_32k_ck>;
- };
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi
deleted file mode 100644
index 4e5ab5189476..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi
+++ /dev/null
@@ -1,341 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP2430 clock data
- *
- * Copyright (C) 2014 Texas Instruments, Inc.
- */
-
-&scm_clocks {
- mcbsp3_mux_fck: mcbsp3_mux_fck@78 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&mcbsp_clks>;
- reg = <0x78>;
- };
-
- mcbsp3_fck: mcbsp3_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
- };
-
- mcbsp4_mux_fck: mcbsp4_mux_fck@78 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x78>;
- };
-
- mcbsp4_fck: mcbsp4_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
- };
-
- mcbsp5_mux_fck: mcbsp5_mux_fck@78 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&mcbsp_clks>;
- ti,bit-shift = <4>;
- reg = <0x78>;
- };
-
- mcbsp5_fck: mcbsp5_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
- };
-};
-
-&prcm_clocks {
- iva2_1_gate_ick: iva2_1_gate_ick@800 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&dsp_fck>;
- ti,bit-shift = <0>;
- reg = <0x0800>;
- };
-
- iva2_1_div_ick: iva2_1_div_ick@840 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&dsp_fck>;
- ti,bit-shift = <5>;
- ti,max-div = <3>;
- reg = <0x0840>;
- ti,index-starts-at-one;
- };
-
- iva2_1_ick: iva2_1_ick {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
- };
-
- mdm_gate_ick: mdm_gate_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,composite-interface-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <0>;
- reg = <0x0c10>;
- };
-
- mdm_div_ick: mdm_div_ick@c40 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_ck>;
- reg = <0x0c40>;
- ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
- };
-
- mdm_ick: mdm_ick {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
- };
-
- mdm_osc_ck: mdm_osc_ck@c00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&osc_ck>;
- ti,bit-shift = <1>;
- reg = <0x0c00>;
- };
-
- mcbsp3_ick: mcbsp3_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <3>;
- reg = <0x0214>;
- };
-
- mcbsp3_gate_fck: mcbsp3_gate_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <3>;
- reg = <0x0204>;
- };
-
- mcbsp4_ick: mcbsp4_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <4>;
- reg = <0x0214>;
- };
-
- mcbsp4_gate_fck: mcbsp4_gate_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <4>;
- reg = <0x0204>;
- };
-
- mcbsp5_ick: mcbsp5_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <5>;
- reg = <0x0214>;
- };
-
- mcbsp5_gate_fck: mcbsp5_gate_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <5>;
- reg = <0x0204>;
- };
-
- mcspi3_ick: mcspi3_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <9>;
- reg = <0x0214>;
- };
-
- mcspi3_fck: mcspi3_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <9>;
- reg = <0x0204>;
- };
-
- icr_ick: icr_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x0410>;
- };
-
- i2chs1_fck: i2chs1_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,omap2430-interface-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <19>;
- reg = <0x0204>;
- };
-
- i2chs2_fck: i2chs2_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,omap2430-interface-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <20>;
- reg = <0x0204>;
- };
-
- usbhs_ick: usbhs_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <6>;
- reg = <0x0214>;
- };
-
- mmchs1_ick: mmchs1_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <7>;
- reg = <0x0214>;
- };
-
- mmchs1_fck: mmchs1_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <7>;
- reg = <0x0204>;
- };
-
- mmchs2_ick: mmchs2_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <8>;
- reg = <0x0214>;
- };
-
- mmchs2_fck: mmchs2_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <8>;
- reg = <0x0204>;
- };
-
- gpio5_ick: gpio5_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <10>;
- reg = <0x0214>;
- };
-
- gpio5_fck: gpio5_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <10>;
- reg = <0x0204>;
- };
-
- mdm_intc_ick: mdm_intc_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <11>;
- reg = <0x0214>;
- };
-
- mmchsdb1_fck: mmchsdb1_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <16>;
- reg = <0x0204>;
- };
-
- mmchsdb2_fck: mmchsdb2_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <17>;
- reg = <0x0204>;
- };
-};
-
-&prcm_clockdomains {
- gfx_clkdm: gfx_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gfx_ick>;
- };
-
- core_l3_clkdm: core_l3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
- };
-
- wkup_clkdm: wkup_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
- <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
- <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
- <&icr_ick>;
- };
-
- dss_clkdm: dss_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dss_ick>, <&dss_54m_fck>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
- <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
- <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
- <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
- <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
- <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
- <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
- <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
- <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
- <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
- <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
- <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
- <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
- <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
- <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
- <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
- <&mmchsdb2_fck>;
- };
-
- mdm_clkdm: mdm_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&mdm_osc_ck>;
- };
-};
-
-&func_96m_ck {
- compatible = "ti,mux-clock";
- clocks = <&apll96_ck>, <&alt_ck>;
- ti,bit-shift = <4>;
- reg = <0x0540>;
-};
-
-&dsp_div_fck {
- ti,max-div = <4>;
- ti,index-starts-at-one;
-};
-
-&ssi_ssr_sst_div_fck {
- ti,max-div = <5>;
- ti,index-starts-at-one;
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts b/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts
deleted file mode 100644
index 207070677e3a..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "omap2430.dtsi"
-
-/ {
- model = "TI OMAP2430 SDP";
- compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x8000000>; /* 128 MB */
- };
-};
-
-&i2c2 {
- clock-frequency = <100000>;
-
- twl: twl@48 {
- reg = <0x48>;
- interrupts = <7>; /* SYS_NIRQ cascaded to intc */
- };
-};
-
-#include "twl4030.dtsi"
-
-&mmc1 {
- vmmc-supply = <&vmmc1>;
- bus-width = <4>;
-};
-
-&gpmc {
- ranges = <5 0 0x08000000 0x01000000>;
- ethernet@gpmc {
- compatible = "smsc,lan91c94";
- interrupt-parent = <&gpio5>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */
- reg = <5 0x300 0xf>;
- bank-width = <2>;
- gpmc,sync-clk-ps = <0>;
- gpmc,mux-add-data = <2>;
- gpmc,device-width = <1>;
- gpmc,cycle2cycle-samecsen;
- gpmc,cycle2cycle-diffcsen;
- gpmc,cs-on-ns = <6>;
- gpmc,cs-rd-off-ns = <187>;
- gpmc,cs-wr-off-ns = <187>;
- gpmc,adv-on-ns = <18>;
- gpmc,adv-rd-off-ns = <48>;
- gpmc,adv-wr-off-ns = <48>;
- gpmc,oe-on-ns = <60>;
- gpmc,oe-off-ns = <169>;
- gpmc,we-on-ns = <66>;
- gpmc,we-off-ns = <169>;
- gpmc,rd-cycle-ns = <187>;
- gpmc,wr-cycle-ns = <187>;
- gpmc,access-ns = <187>;
- gpmc,page-burst-access-ns = <24>;
- gpmc,bus-turnaround-ns = <24>;
- gpmc,cycle2cycle-delay-ns = <24>;
- gpmc,wait-monitoring-ns = <0>;
- gpmc,clk-activation-ns = <0>;
- gpmc,wr-data-mux-bus-ns = <0>;
- gpmc,wr-access-ns = <0>;
- };
-};
-
diff --git a/arch/arm/boot/dts/ti/omap/omap2430.dtsi b/arch/arm/boot/dts/ti/omap/omap2430.dtsi
deleted file mode 100644
index 01bd471f9223..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap2430.dtsi
+++ /dev/null
@@ -1,366 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP243x SoC
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "omap2.dtsi"
-
-/ {
- compatible = "ti,omap2430", "ti,omap2";
-
- ocp {
- l4_wkup: l4_wkup@49000000 {
- compatible = "ti,omap2-l4-wkup", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x49000000 0x31000>;
-
- prcm: prcm@6000 {
- compatible = "ti,omap2-prcm";
- reg = <0x6000 0x1000>;
-
- prcm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prcm_clockdomains: clockdomains {
- };
- };
-
- scm: scm@2000 {
- compatible = "ti,omap2-scm", "simple-bus";
- reg = <0x2000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- #pinctrl-cells = <1>;
- ranges = <0 0x2000 0x1000>;
-
- omap2430_pmx: pinmux@30 {
- compatible = "ti,omap2430-padconf",
- "pinctrl-single";
- reg = <0x30 0x0154>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <8>;
- pinctrl-single,function-mask = <0x3f>;
- };
-
- scm_conf: scm_conf@270 {
- compatible = "ti,omap2-scm-conf", "syscon",
- "simple-bus";
- reg = <0x270 0x240>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x270 0x240>;
-
- scm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pbias_regulator: pbias_regulator@230 {
- compatible = "ti,pbias-omap2", "ti,pbias-omap";
- reg = <0x230 0x4>;
- syscon = <&scm_conf>;
- pbias_mmc_reg: pbias_mmc_omap2430 {
- regulator-name = "pbias_mmc_omap2430";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- };
- };
- };
-
- scm_clockdomains: clockdomains {
- };
- };
-
- target-module@20000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x20000 0x4>,
- <0x20004 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>;
- clocks = <&func_32k_ck>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x20000 0x1000>;
-
- counter32k: counter@0 {
- compatible = "ti,omap-counter32k";
- reg = <0 0x20>;
- };
- };
- };
-
- gpio1: gpio@4900c000 {
- compatible = "ti,omap2-gpio";
- reg = <0x4900c000 0x200>;
- interrupts = <29>;
- ti,hwmods = "gpio1";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio2: gpio@4900e000 {
- compatible = "ti,omap2-gpio";
- reg = <0x4900e000 0x200>;
- interrupts = <30>;
- ti,hwmods = "gpio2";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio3: gpio@49010000 {
- compatible = "ti,omap2-gpio";
- reg = <0x49010000 0x200>;
- interrupts = <31>;
- ti,hwmods = "gpio3";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio4: gpio@49012000 {
- compatible = "ti,omap2-gpio";
- reg = <0x49012000 0x200>;
- interrupts = <32>;
- ti,hwmods = "gpio4";
- ti,gpio-always-on;
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpio5: gpio@480b6000 {
- compatible = "ti,omap2-gpio";
- reg = <0x480b6000 0x200>;
- interrupts = <33>;
- ti,hwmods = "gpio5";
- #gpio-cells = <2>;
- gpio-controller;
- #interrupt-cells = <2>;
- interrupt-controller;
- };
-
- gpmc: gpmc@6e000000 {
- compatible = "ti,omap2430-gpmc";
- reg = <0x6e000000 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- interrupts = <20>;
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- ti,hwmods = "gpmc";
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- mcbsp1: mcbsp@48074000 {
- compatible = "ti,omap2430-mcbsp";
- reg = <0x48074000 0xff>;
- reg-names = "mpu";
- interrupts = <64>, /* OCP compliant interrupt */
- <59>, /* TX interrupt */
- <60>, /* RX interrupt */
- <61>; /* RX overflow interrupt */
- interrupt-names = "common", "tx", "rx", "rx_overflow";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp1";
- dmas = <&sdma 31>,
- <&sdma 32>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mcbsp2: mcbsp@48076000 {
- compatible = "ti,omap2430-mcbsp";
- reg = <0x48076000 0xff>;
- reg-names = "mpu";
- interrupts = <16>, /* OCP compliant interrupt */
- <62>, /* TX interrupt */
- <63>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp2";
- dmas = <&sdma 33>,
- <&sdma 34>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mcbsp3: mcbsp@4808c000 {
- compatible = "ti,omap2430-mcbsp";
- reg = <0x4808c000 0xff>;
- reg-names = "mpu";
- interrupts = <17>, /* OCP compliant interrupt */
- <89>, /* TX interrupt */
- <90>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp3";
- dmas = <&sdma 17>,
- <&sdma 18>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mcbsp4: mcbsp@4808e000 {
- compatible = "ti,omap2430-mcbsp";
- reg = <0x4808e000 0xff>;
- reg-names = "mpu";
- interrupts = <18>, /* OCP compliant interrupt */
- <54>, /* TX interrupt */
- <55>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp4";
- dmas = <&sdma 19>,
- <&sdma 20>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mcbsp5: mcbsp@48096000 {
- compatible = "ti,omap2430-mcbsp";
- reg = <0x48096000 0xff>;
- reg-names = "mpu";
- interrupts = <19>, /* OCP compliant interrupt */
- <81>, /* TX interrupt */
- <82>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp5";
- dmas = <&sdma 21>,
- <&sdma 22>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- mmc1: mmc@4809c000 {
- compatible = "ti,omap2-hsmmc";
- reg = <0x4809c000 0x200>;
- interrupts = <83>;
- ti,hwmods = "mmc1";
- ti,dual-volt;
- dmas = <&sdma 61>, <&sdma 62>;
- dma-names = "tx", "rx";
- pbias-supply = <&pbias_mmc_reg>;
- };
-
- mmc2: mmc@480b4000 {
- compatible = "ti,omap2-hsmmc";
- reg = <0x480b4000 0x200>;
- interrupts = <86>;
- ti,hwmods = "mmc2";
- dmas = <&sdma 47>, <&sdma 48>;
- dma-names = "tx", "rx";
- };
-
- mailbox: mailbox@48094000 {
- compatible = "ti,omap2-mailbox";
- reg = <0x48094000 0x200>;
- interrupts = <26>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <6>;
- mbox_dsp: mbox-dsp {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <1 0 0>;
- };
- };
-
- timer1_target: target-module@49018000 {
- compatible = "ti,sysc-omap2-timer", "ti,sysc";
- reg = <0x49018000 0x4>,
- <0x49018010 0x4>,
- <0x49018014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- clocks = <&gpt1_fck>, <&gpt1_ick>;
- clock-names = "fck", "ick";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x49018000 0x1000>;
-
- timer1: timer@0 {
- compatible = "ti,omap2420-timer";
- reg = <0 0x400>;
- interrupts = <37>;
- ti,timer-alwon;
- };
- };
-
- mcspi3: spi@480b8000 {
- compatible = "ti,omap2-mcspi";
- ti,hwmods = "mcspi3";
- reg = <0x480b8000 0x100>;
- interrupts = <91>;
- dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
-
- usb_otg_hs: usb_otg_hs@480ac000 {
- compatible = "ti,omap2-musb";
- ti,hwmods = "usb_otg_hs";
- reg = <0x480ac000 0x1000>;
- interrupts = <93>;
- };
-
- wd_timer2: watchdog@49016000 {
- compatible = "ti,omap2-wdt";
- ti,hwmods = "wd_timer2";
- reg = <0x49016000 0x80>;
- };
- };
-};
-
-&sdma {
- compatible = "ti,omap2430-sdma", "ti,omap-sdma";
-};
-
-&i2c1 {
- compatible = "ti,omap2430-i2c";
-};
-
-&i2c2 {
- compatible = "ti,omap2430-i2c";
-};
-
-#include "omap24xx-clocks.dtsi"
-#include "omap2430-clocks.dtsi"
-
-/* Preferred always-on timer for clockevent */
-&timer1_target {
- ti,no-reset-on-init;
- ti,no-idle;
- timer@0 {
- assigned-clocks = <&gpt1_fck>;
- assigned-clock-parents = <&func_32k_ck>;
- };
-};
diff --git a/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi
deleted file mode 100644
index 07af87edf0e2..000000000000
--- a/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi
+++ /dev/null
@@ -1,1241 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP24xx clock data
- *
- * Copyright (C) 2014 Texas Instruments, Inc.
- */
-&scm_clocks {
- mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x4>;
- };
-
- mcbsp1_fck: mcbsp1_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
- };
-
- mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_96m_ck>, <&mcbsp_clks>;
- ti,bit-shift = <6>;
- reg = <0x4>;
- };
-
- mcbsp2_fck: mcbsp2_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
- };
-};
-
-&prcm_clocks {
- func_32k_ck: func_32k_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- secure_32k_ck: secure_32k_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- virt_12m_ck: virt_12m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- };
-
- virt_13m_ck: virt_13m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <13000000>;
- };
-
- virt_19200000_ck: virt_19200000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <19200000>;
- };
-
- virt_26m_ck: virt_26m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- };
-
- aplls_clkin_ck: aplls_clkin_ck@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
- ti,bit-shift = <23>;
- reg = <0x0540>;
- };
-
- aplls_clkin_x2_ck: aplls_clkin_x2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&aplls_clkin_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- osc_ck: osc_ck@60 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
- ti,bit-shift = <6>;
- reg = <0x0060>;
- ti,index-starts-at-one;
- };
-
- sys_ck: sys_ck@60 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&osc_ck>;
- ti,bit-shift = <6>;
- ti,max-div = <3>;
- reg = <0x0060>;
- ti,index-starts-at-one;
- };
-
- alt_ck: alt_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <54000000>;
- };
-
- mcbsp_clks: mcbsp_clks {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0x0>;
- };
-
- dpll_ck: dpll_ck@500 {
- #clock-cells = <0>;
- compatible = "ti,omap2-dpll-core-clock";
- clocks = <&sys_ck>, <&sys_ck>;
- reg = <0x0500>, <0x0540>;
- };
-
- apll96_ck: apll96_ck@500 {
- #clock-cells = <0>;
- compatible = "ti,omap2-apll-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <2>;
- ti,idlest-shift = <8>;
- ti,clock-frequency = <96000000>;
- reg = <0x0500>, <0x0530>, <0x0520>;
- };
-
- apll54_ck: apll54_ck@500 {
- #clock-cells = <0>;
- compatible = "ti,omap2-apll-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <6>;
- ti,idlest-shift = <9>;
- ti,clock-frequency = <54000000>;
- reg = <0x0500>, <0x0530>, <0x0520>;
- };
-
- func_54m_ck: func_54m_ck@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&apll54_ck>, <&alt_ck>;
- ti,bit-shift = <5>;
- reg = <0x0540>;
- };
-
- core_ck: core_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- func_96m_ck: func_96m_ck@540 {
- #clock-cells = <0>;
- };
-
- apll96_d2_ck: apll96_d2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&apll96_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- func_48m_ck: func_48m_ck@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&apll96_d2_ck>, <&alt_ck>;
- ti,bit-shift = <3>;
- reg = <0x0540>;
- };
-
- func_12m_ck: func_12m_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&func_48m_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- sys_clkout_src_gate: sys_clkout_src_gate@70 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <7>;
- reg = <0x0070>;
- };
-
- sys_clkout_src_mux: sys_clkout_src_mux@70 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
- reg = <0x0070>;
- };
-
- sys_clkout_src: sys_clkout_src {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
- };
-
- sys_clkout: sys_clkout@70 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sys_clkout_src>;
- ti,bit-shift = <3>;
- ti,max-div = <64>;
- reg = <0x0070>;
- ti,index-power-of-two;
- };
-
- emul_ck: emul_ck@78 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_54m_ck>;
- ti,bit-shift = <0>;
- reg = <0x0078>;
- };
-
- mpu_ck: mpu_ck@140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,max-div = <31>;
- reg = <0x0140>;
- ti,index-starts-at-one;
- };
-
- dsp_gate_fck: dsp_gate_fck@800 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <0>;
- reg = <0x0800>;
- };
-
- dsp_div_fck: dsp_div_fck@840 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_ck>;
- reg = <0x0840>;
- };
-
- dsp_fck: dsp_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
- };
-
- core_l3_ck: core_l3_ck@240 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,max-div = <31>;
- reg = <0x0240>;
- ti,index-starts-at-one;
- };
-
- gfx_3d_gate_fck: gfx_3d_gate_fck@300 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <2>;
- reg = <0x0300>;
- };
-
- gfx_3d_div_fck: gfx_3d_div_fck@340 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_l3_ck>;
- ti,max-div = <4>;
- reg = <0x0340>;
- ti,index-starts-at-one;
- };
-
- gfx_3d_fck: gfx_3d_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
- };
-
- gfx_2d_gate_fck: gfx_2d_gate_fck@300 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <1>;
- reg = <0x0300>;
- };
-
- gfx_2d_div_fck: gfx_2d_div_fck@340 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_l3_ck>;
- ti,max-div = <4>;
- reg = <0x0340>;
- ti,index-starts-at-one;
- };
-
- gfx_2d_fck: gfx_2d_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
- };
-
- gfx_ick: gfx_ick@310 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <0>;
- reg = <0x0310>;
- };
-
- l4_ck: l4_ck@240 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <5>;
- ti,max-div = <3>;
- reg = <0x0240>;
- ti,index-starts-at-one;
- };
-
- dss_ick: dss_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <0>;
- reg = <0x0210>;
- };
-
- dss1_gate_fck: dss1_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <0>;
- reg = <0x0200>;
- };
-
- core_d2_ck: core_d2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- core_d3_ck: core_d3_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <3>;
- };
-
- core_d4_ck: core_d4_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- core_d5_ck: core_d5_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <5>;
- };
-
- core_d6_ck: core_d6_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <6>;
- };
-
- dummy_ck: dummy_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- core_d8_ck: core_d8_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <8>;
- };
-
- core_d9_ck: core_d9_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <9>;
- };
-
- core_d12_ck: core_d12_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <12>;
- };
-
- core_d16_ck: core_d16_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <16>;
- };
-
- dss1_mux_fck: dss1_mux_fck@240 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
- ti,bit-shift = <8>;
- reg = <0x0240>;
- };
-
- dss1_fck: dss1_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
- };
-
- dss2_gate_fck: dss2_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <1>;
- reg = <0x0200>;
- };
-
- dss2_mux_fck: dss2_mux_fck@240 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_ck>, <&func_48m_ck>;
- ti,bit-shift = <13>;
- reg = <0x0240>;
- };
-
- dss2_fck: dss2_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
- };
-
- dss_54m_fck: dss_54m_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_54m_ck>;
- ti,bit-shift = <2>;
- reg = <0x0200>;
- };
-
- ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <1>;
- reg = <0x0204>;
- };
-
- ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <20>;
- reg = <0x0240>;
- };
-
- ssi_ssr_sst_fck: ssi_ssr_sst_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
- };
-
- usb_l4_gate_ick: usb_l4_gate_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,composite-interface-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <0>;
- reg = <0x0214>;
- };
-
- usb_l4_div_ick: usb_l4_div_ick@240 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&core_l3_ck>;
- ti,bit-shift = <25>;
- reg = <0x0240>;
- ti,dividers = <0>, <1>, <2>, <0>, <4>;
- };
-
- usb_l4_ick: usb_l4_ick {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
- };
-
- ssi_l4_ick: ssi_l4_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <1>;
- reg = <0x0214>;
- };
-
- gpt1_ick: gpt1_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <0>;
- reg = <0x0410>;
- };
-
- gpt1_gate_fck: gpt1_gate_fck@400 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <0>;
- reg = <0x0400>;
- };
-
- gpt1_mux_fck: gpt1_mux_fck@440 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- reg = <0x0440>;
- };
-
- gpt1_fck: gpt1_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
- };
-
- gpt2_ick: gpt2_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <4>;
- reg = <0x0210>;
- };
-
- gpt2_gate_fck: gpt2_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <4>;
- reg = <0x0200>;
- };
-
- gpt2_mux_fck: gpt2_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <2>;
- reg = <0x0244>;
- };
-
- gpt2_fck: gpt2_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
- };
-
- gpt3_ick: gpt3_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <5>;
- reg = <0x0210>;
- };
-
- gpt3_gate_fck: gpt3_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <5>;
- reg = <0x0200>;
- };
-
- gpt3_mux_fck: gpt3_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <4>;
- reg = <0x0244>;
- };
-
- gpt3_fck: gpt3_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
- };
-
- gpt4_ick: gpt4_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <6>;
- reg = <0x0210>;
- };
-
- gpt4_gate_fck: gpt4_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <6>;
- reg = <0x0200>;
- };
-
- gpt4_mux_fck: gpt4_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <6>;
- reg = <0x0244>;
- };
-
- gpt4_fck: gpt4_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
- };
-
- gpt5_ick: gpt5_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <7>;
- reg = <0x0210>;
- };
-
- gpt5_gate_fck: gpt5_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <7>;
- reg = <0x0200>;
- };
-
- gpt5_mux_fck: gpt5_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <8>;
- reg = <0x0244>;
- };
-
- gpt5_fck: gpt5_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
- };
-
- gpt6_ick: gpt6_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <8>;
- reg = <0x0210>;
- };
-
- gpt6_gate_fck: gpt6_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x0200>;
- };
-
- gpt6_mux_fck: gpt6_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <10>;
- reg = <0x0244>;
- };
-
- gpt6_fck: gpt6_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
- };
-
- gpt7_ick: gpt7_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <9>;
- reg = <0x0210>;
- };
-
- gpt7_gate_fck: gpt7_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <9>;
- reg = <0x0200>;
- };
-
- gpt7_mux_fck: gpt7_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <12>;
- reg = <0x0244>;
- };
-
- gpt7_fck: gpt7_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
- };
-
- gpt8_ick: gpt8_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <10>;
- reg = <0x0210>;
- };
-
- gpt8_gate_fck: gpt8_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <10>;
- reg = <0x0200>;
- };
-
- gpt8_mux_fck: gpt8_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <14>;
- reg = <0x0244>;
- };
-
- gpt8_fck: gpt8_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
- };
-
- gpt9_ick: gpt9_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <11>;
- reg = <0x0210>;
- };
-
- gpt9_gate_fck: gpt9_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <11>;
- reg = <0x0200>;
- };
-
- gpt9_mux_fck: gpt9_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <16>;
- reg = <0x0244>;
- };
-
- gpt9_fck: gpt9_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
- };
-
- gpt10_ick: gpt10_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <12>;
- reg = <0x0210>;
- };
-
- gpt10_gate_fck: gpt10_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <12>;
- reg = <0x0200>;
- };
-
- gpt10_mux_fck: gpt10_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <18>;
- reg = <0x0244>;
- };
-
- gpt10_fck: gpt10_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
- };
-
- gpt11_ick: gpt11_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <13>;
- reg = <0x0210>;
- };
-
- gpt11_gate_fck: gpt11_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <13>;
- reg = <0x0200>;
- };
-
- gpt11_mux_fck: gpt11_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <20>;
- reg = <0x0244>;
- };
-
- gpt11_fck: gpt11_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
- };
-
- gpt12_ick: gpt12_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <14>;
- reg = <0x0210>;
- };
-
- gpt12_gate_fck: gpt12_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <14>;
- reg = <0x0200>;
- };
-
- gpt12_mux_fck: gpt12_mux_fck@244 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
- ti,bit-shift = <22>;
- reg = <0x0244>;
- };
-
- gpt12_fck: gpt12_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
- };
-
- mcbsp1_ick: mcbsp1_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <15>;
- reg = <0x0210>;
- };
-
- mcbsp1_gate_fck: mcbsp1_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <15>;
- reg = <0x0200>;
- };
-
- mcbsp2_ick: mcbsp2_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <16>;
- reg = <0x0210>;
- };
-
- mcbsp2_gate_fck: mcbsp2_gate_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <16>;
- reg = <0x0200>;
- };
-
- mcspi1_ick: mcspi1_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <17>;
- reg = <0x0210>;
- };
-
- mcspi1_fck: mcspi1_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <17>;
- reg = <0x0200>;
- };
-
- mcspi2_ick: mcspi2_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <18>;
- reg = <0x0210>;
- };
-
- mcspi2_fck: mcspi2_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <18>;
- reg = <0x0200>;
- };
-
- uart1_ick: uart1_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <21>;
- reg = <0x0210>;
- };
-
- uart1_fck: uart1_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <21>;
- reg = <0x0200>;
- };
-
- uart2_ick: uart2_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <22>;
- reg = <0x0210>;
- };
-
- uart2_fck: uart2_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <22>;
- reg = <0x0200>;
- };
-
- uart3_ick: uart3_ick@214 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <2>;
- reg = <0x0214>;
- };
-
- uart3_fck: uart3_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <2>;
- reg = <0x0204>;
- };
-
- gpios_ick: gpios_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <2>;
- reg = <0x0410>;
- };
-
- gpios_fck: gpios_fck@400 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <2>;
- reg = <0x0400>;
- };
-
- mpu_wdt_ick: mpu_wdt_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <3>;
- reg = <0x0410>;
- };
-
- mpu_wdt_fck: mpu_wdt_fck@400 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <3>;
- reg = <0x0400>;
- };
-
- sync_32k_ick: sync_32k_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <1>;
- reg = <0x0410>;
- };
-
- wdt1_ick: wdt1_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <4>;
- reg = <0x0410>;
- };
-
- omapctrl_ick: omapctrl_ick@410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <5>;
- reg = <0x0410>;
- };
-
- cam_fck: cam_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <31>;
- reg = <0x0200>;
- };
-
- cam_ick: cam_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <31>;
- reg = <0x0210>;
- };
-
- mailboxes_ick: mailboxes_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <30>;
- reg = <0x0210>;
- };
-
- wdt4_ick: wdt4_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <29>;
- reg = <0x0210>;
- };
-
- wdt4_fck: wdt4_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_32k_ck>;
- ti,bit-shift = <29>;
- reg = <0x0200>;
- };
-
- mspro_ick: mspro_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <27>;
- reg = <0x0210>;
- };
-
- mspro_fck: mspro_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_96m_ck>;
- ti,bit-shift = <27>;
- reg = <0x0200>;
- };
-
- fac_ick: fac_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <25>;
- reg = <0x0210>;
- };
-
- fac_fck: fac_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_12m_ck>;
- ti,bit-shift = <25>;
- reg = <0x0200>;
- };
-
- hdq_ick: hdq_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <23>;
- reg = <0x0210>;
- };
-
- hdq_fck: hdq_fck@200 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_12m_ck>;
- ti,bit-shift = <23>;
- reg = <0x0200>;
- };
-
- i2c1_ick: i2c1_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <19>;
- reg = <0x0210>;
- };
-
- i2c2_ick: i2c2_ick@210 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <20>;
- reg = <0x0210>;
- };
-
- gpmc_fck: gpmc_fck@238 {
- #clock-cells = <0>;
- compatible = "ti,fixed-factor-clock";
- clocks = <&core_l3_ck>;
- ti,clock-div = <1>;
- ti,autoidle-shift = <1>;
- reg = <0x0238>;
- ti,clock-mult = <1>;
- };
-
- sdma_fck: sdma_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_l3_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- sdma_ick: sdma_ick@238 {
- #clock-cells = <0>;
- compatible = "ti,fixed-factor-clock";
- clocks = <&core_l3_ck>;
- ti,clock-div = <1>;
- ti,autoidle-shift = <0>;
- reg = <0x0238>;
- ti,clock-mult = <1>;
- };
-
- sdrc_ick: sdrc_ick@238 {
- #clock-cells = <0>;
- compatible = "ti,fixed-factor-clock";
- clocks = <&core_l3_ck>;
- ti,clock-div = <1>;
- ti,autoidle-shift = <2>;
- reg = <0x0238>;
- ti,clock-mult = <1>;
- };
-
- des_ick: des_ick@21c {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <0>;
- reg = <0x021c>;
- };
-
- sha_ick: sha_ick@21c {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <1>;
- reg = <0x021c>;
- };
-
- rng_ick: rng_ick@21c {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <2>;
- reg = <0x021c>;
- };
-
- aes_ick: aes_ick@21c {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <3>;
- reg = <0x021c>;
- };
-
- pka_ick: pka_ick@21c {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l4_ck>;
- ti,bit-shift = <4>;
- reg = <0x021c>;
- };
-
- usb_fck: usb_fck@204 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&func_48m_ck>;
- ti,bit-shift = <0>;
- reg = <0x0204>;
- };
-};
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index f827f89567fd..0d0ba5cf0ce4 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -22,9 +22,7 @@ CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_PROFILING=y
-CONFIG_ARCH_MULTI_V6=y
CONFIG_OMAP_RESET_CLOCKS=y
-CONFIG_ARCH_OMAP2=y
CONFIG_ARCH_OMAP3=y
CONFIG_ARCH_OMAP4=y
CONFIG_SOC_OMAP5=y
@@ -34,7 +32,6 @@ CONFIG_SOC_DRA7XX=y
CONFIG_POWER_AVS_OMAP=y
CONFIG_POWER_AVS_OMAP_CLASS3=y
CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_ERRATA_411920=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_ARM_APPENDED_DTB=y
@@ -627,7 +624,6 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_M41T80=m
-CONFIG_RTC_DRV_TWL92330=y
CONFIG_RTC_DRV_TWL4030=m
CONFIG_RTC_DRV_PALMAS=m
CONFIG_RTC_DRV_OMAP=m
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 79f8afe3a6bf..37ecbfc0a19f 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -5,15 +5,6 @@ menu "TI OMAP/AM/DM/DRA Family"
config OMAP_HWMOD
bool
-config ARCH_OMAP2
- bool "TI OMAP2"
- depends on ARCH_MULTI_V6
- depends on !SMP
- select ARCH_OMAP2PLUS
- select CPU_ARM1136R0
- select OMAP_HWMOD
- select SOC_HAS_OMAP2_SDRC
-
config ARCH_OMAP3
bool "TI OMAP3"
depends on ARCH_MULTI_V7
@@ -118,7 +109,7 @@ config ARCH_OMAP2PLUS
select OMAP_IRQCHIP
select CLKSRC_TI_32K
help
- Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
+ Systems based on OMAP3, OMAP4 or OMAP5
config OMAP_INTERCONNECT_BARRIER
bool
@@ -129,7 +120,7 @@ config ARCH_OMAP
if ARCH_OMAP2PLUS
-menu "TI OMAP2/3/4 Specific Features"
+menu "TI OMAP3/4 Specific Features"
config ARCH_OMAP2PLUS_TYPICAL
bool "Typical OMAP configuration"
@@ -138,8 +129,7 @@ config ARCH_OMAP2PLUS_TYPICAL
select HIGHMEM
select I2C
select I2C_OMAP
- select MENELAUS if ARCH_OMAP2
- select NEON if CPU_V7
+ select NEON
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
@@ -204,27 +194,7 @@ config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
PPA routine service ID for setting L2 auxiliary control register.
comment "OMAP Core Type"
- depends on ARCH_OMAP2
-
-config SOC_OMAP2420
- bool "OMAP2420 support (DEPRECATED)"
- depends on ARCH_OMAP2
- default y
- select OMAP_DM_SYSTIMER
- select OMAP_DM_TIMER
- select SOC_HAS_OMAP2_SDRC
- help
- This SoC is scheduled for removal in early 2027,
- since it uses the ARM1136r0 CPU revision.
-
-config SOC_OMAP2430
- bool "OMAP2430 support (DEPRECATED)"
- depends on ARCH_OMAP2
- default y
- select SOC_HAS_OMAP2_SDRC
- help
- This SoC is scheduled for removal in early 2027,
- since it uses the ARM1136r0 CPU revision.
+ depends on ARCH_OMAP3
config SOC_OMAP3430
bool "OMAP3430 support"
@@ -237,33 +207,9 @@ config SOC_TI81XX
depends on ARCH_OMAP3
default y
-comment "OMAP Legacy Platform Data Board Type"
- depends on ARCH_OMAP2PLUS
-
config MACH_OMAP_GENERIC
bool
-config MACH_OMAP2_TUSB6010
- bool
- depends on ARCH_OMAP2 && SOC_OMAP2420
- default y if MACH_NOKIA_N8X0
-
-config MACH_NOKIA_N810
- bool
-
-config MACH_NOKIA_N810_WIMAX
- bool
-
-config MACH_NOKIA_N8X0
- bool "Nokia N800/N810 (DEPRECATED)"
- depends on SOC_OMAP2420
- default y
- select MACH_NOKIA_N810
- select MACH_NOKIA_N810_WIMAX
- help
- This machine is scheduled for removal in early 2027,
- since it uses the ARM1136r0 CPU revision.
-
endmenu
endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index daf21127c82f..6c741442dc0d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -5,23 +5,17 @@
# Common support
obj-y := id.o io.o control.o devices.o fb.o pm.o \
- common.o dma.o omap-headsmp.o sram.o
+ common.o dma.o omap-headsmp.o
-hwmod-common = omap_hwmod.o \
+# OMAP3 hwmod specific
+obj-$(CONFIG_ARCH_OMAP3) += sram.o omap_hwmod.o \
omap_hwmod_common_data.o \
omap_hwmod_common_ipblock_data.o \
omap_device.o display.o hdq1w.o \
i2c.o wd_timer.o
-clock-common = clock.o
-secure-common = omap-smc.o omap-secure.o
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(secure-common)
-obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
-obj-$(CONFIG_SOC_OMAP5) += $(secure-common)
-obj-$(CONFIG_SOC_AM43XX) += $(secure-common)
-obj-$(CONFIG_SOC_DRA7XX) += $(secure-common)
+# secure world
+obj-y += omap-smc.o omap-secure.o
ifneq ($(CONFIG_SND_SOC_OMAP_MCBSP),)
obj-$(CONFIG_OMAP_HWMOD) += mcbsp.o
@@ -49,13 +43,7 @@ omap5-dra7-common-$(CONFIG_SOC_HAS_REALTIME_COUNTER) = timer.o
obj-$(CONFIG_SOC_OMAP5) += $(omap5-dra7-common-y)
obj-$(CONFIG_SOC_DRA7XX) += $(omap5-dra7-common-y)
-# Functions loaded to SRAM
-obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
-obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
-
# Restart code (OMAP4/5 currently in omap4-common.c)
-obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
-obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
obj-$(CONFIG_SOC_TI81XX) += ti81xx-restart.o
obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
obj-$(CONFIG_SOC_AM43XX) += omap4-restart.o
@@ -65,7 +53,6 @@ obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
# SMS/SDRC
-obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
# OPP table initialization
@@ -80,7 +67,6 @@ obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
omap-4-5-pm-common += pm44xx.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
@@ -105,7 +91,6 @@ endif
# PRCM
obj-y += prm_common.o cm_common.o
-obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
omap-prcm-4-5-common = cminst44xx.o prm44xx.o \
@@ -122,8 +107,6 @@ obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
-obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
-obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
@@ -136,9 +119,6 @@ obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common)
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
-obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common)
-obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o
-obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
@@ -155,10 +135,6 @@ obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
-obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
-obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
-obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
@@ -176,47 +152,20 @@ obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
# Clock framework
-obj-$(CONFIG_ARCH_OMAP2) += $(clock-common)
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o
-obj-$(CONFIG_ARCH_OMAP3) += $(clock-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
-obj-$(CONFIG_SOC_AM33XX) += $(clock-common)
-obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
-obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
-obj-$(CONFIG_SOC_AM43XX) += $(clock-common)
-
-# OMAP2 clock rate set data (old "OPP" data)
-obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
-obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
+obj-y += clock.o
# hwmod data
-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o
-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_ipblock_data.o
-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o
-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_TI81XX) += omap_hwmod_81xx_data.o
-# OMAP2420 MSDI controller integration support ("MMC")
-obj-$(CONFIG_SOC_OMAP2420) += msdi.o
-
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
-obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
# Platform specific device init code
obj-y += omap_phy_internal.o
-obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
-
$(obj)/pm-asm-offsets.h: $(obj)/pm-asm-offsets.s FORCE
$(call filechk,offsets,__TI_PM_ASM_OFFSETS_H__)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index bff673e932fe..972b8cf0547f 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -45,40 +45,6 @@ void tick_broadcast(const struct cpumask *mask)
}
#endif
-#ifdef CONFIG_SOC_OMAP2420
-static const char *const omap242x_boards_compat[] __initconst = {
- "ti,omap2420",
- NULL,
-};
-
-DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
- .reserve = omap_reserve,
- .map_io = omap242x_map_io,
- .init_early = omap2420_init_early,
- .init_machine = omap_generic_init,
- .init_time = omap_init_time_of,
- .dt_compat = omap242x_boards_compat,
- .restart = omap2xxx_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-static const char *const omap243x_boards_compat[] __initconst = {
- "ti,omap2430",
- NULL,
-};
-
-DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
- .reserve = omap_reserve,
- .map_io = omap243x_map_io,
- .init_early = omap2430_init_early,
- .init_machine = omap_generic_init,
- .init_time = omap_init_time_of,
- .dt_compat = omap243x_boards_compat,
- .restart = omap2xxx_restart,
-MACHINE_END
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
/* Some boards need board name for legacy userspace in /proc/cpuinfo */
static const char *const n900_boards_compat[] __initconst = {
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
deleted file mode 100644
index d9acd32c5457..000000000000
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ /dev/null
@@ -1,512 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap2/board-n8x0.c
- *
- * Copyright (C) 2005-2009 Nokia Corporation
- * Author: Juha Yrjola <juha.yrjola@nokia.com>
- *
- * Modified from mach-omap2/board-generic.c
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio/consumer.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/stddef.h>
-#include <linux/i2c.h>
-#include <linux/spi/spi.h>
-#include <linux/usb/musb.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_data/mmc-omap.h>
-#include <linux/mfd/menelaus.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include "common.h"
-#include "mmc.h"
-#include "usb-tusb6010.h"
-#include "soc.h"
-#include "common-board-devices.h"
-
-#define TUSB6010_ASYNC_CS 1
-#define TUSB6010_SYNC_CS 4
-#define TUSB6010_DMACHAN 0x3f
-
-#define NOKIA_N810_WIMAX (1 << 2)
-#define NOKIA_N810 (1 << 1)
-#define NOKIA_N800 (1 << 0)
-
-static u32 board_caps;
-
-#define board_is_n800() (board_caps & NOKIA_N800)
-#define board_is_n810() (board_caps & NOKIA_N810)
-#define board_is_n810_wimax() (board_caps & NOKIA_N810_WIMAX)
-
-static void board_check_revision(void)
-{
- if (of_machine_is_compatible("nokia,n800"))
- board_caps = NOKIA_N800;
- else if (of_machine_is_compatible("nokia,n810"))
- board_caps = NOKIA_N810;
- else if (of_machine_is_compatible("nokia,n810-wimax"))
- board_caps = NOKIA_N810_WIMAX;
-
- if (!board_caps)
- pr_err("Unknown board\n");
-}
-
-#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps = 16,
- .ram_bits = 12,
-};
-
-static struct musb_hdrc_platform_data tusb_data = {
- .mode = MUSB_OTG,
- .min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */
- .power = 100, /* Max 100 mA VBUS for host mode */
- .config = &musb_config,
-};
-
-static struct gpiod_lookup_table tusb_gpio_table = {
- .dev_id = "musb-tusb",
- .table = {
- GPIO_LOOKUP("gpio-0-31", 0, "enable", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-32-63", 26, "int", GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static void __init n8x0_usb_init(void)
-{
- int ret = 0;
-
- gpiod_add_lookup_table(&tusb_gpio_table);
- ret = tusb6010_setup_interface(&tusb_data, TUSB6010_REFCLK_19, 2,
- TUSB6010_ASYNC_CS, TUSB6010_SYNC_CS,
- TUSB6010_DMACHAN);
- if (ret != 0)
- return;
-
- pr_info("TUSB 6010\n");
-
- return;
-}
-#else
-
-static void __init n8x0_usb_init(void) {}
-
-#endif /*CONFIG_USB_MUSB_TUSB6010 */
-
-#if defined(CONFIG_MENELAUS) && IS_ENABLED(CONFIG_MMC_OMAP)
-
-/*
- * On both N800 and N810, only the first of the two MMC controllers is in use.
- * The two MMC slots are multiplexed via Menelaus companion chip over I2C.
- * On N800, both slots are powered via Menelaus. On N810, only one of the
- * slots is powered via Menelaus. The N810 EMMC is powered via GPIO.
- *
- * VMMC slot 1 on both N800 and N810
- * VDCDC3_APE and VMCS2_APE slot 2 on N800
- * GPIO23 and GPIO9 slot 2 EMMC on N810
- *
- */
-static int slot1_cover_open;
-static int slot2_cover_open;
-static struct device *mmc_device;
-
-static struct gpiod_lookup_table nokia800_mmc_gpio_table = {
- .dev_id = "mmci-omap.0",
- .table = {
- /* Slot switch, GPIO 96 */
- GPIO_LOOKUP("gpio-96-127", 0, "switch", GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static struct gpiod_lookup_table nokia810_mmc_gpio_table = {
- .dev_id = "mmci-omap.0",
- .table = {
- /* Slot switch, GPIO 96 */
- GPIO_LOOKUP("gpio-96-127", 0, "switch", GPIO_ACTIVE_HIGH),
- /* Slot index 1, VSD power, GPIO 23 */
- GPIO_LOOKUP_IDX("gpio-0-31", 23, "vsd", 1, GPIO_ACTIVE_HIGH),
- /* Slot index 1, VIO power, GPIO 9 */
- GPIO_LOOKUP_IDX("gpio-0-31", 9, "vio", 1, GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static int n8x0_mmc_set_power_menelaus(struct device *dev, int slot,
- int power_on, int vdd)
-{
- int mV;
-
-#ifdef CONFIG_MMC_DEBUG
- dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
- str_on_off(power_on), vdd);
-#endif
- if (slot == 0) {
- if (!power_on)
- return menelaus_set_vmmc(0);
- switch (1 << vdd) {
- case MMC_VDD_33_34:
- case MMC_VDD_32_33:
- case MMC_VDD_31_32:
- mV = 3100;
- break;
- case MMC_VDD_30_31:
- mV = 3000;
- break;
- case MMC_VDD_28_29:
- mV = 2800;
- break;
- case MMC_VDD_165_195:
- mV = 1850;
- break;
- default:
- BUG();
- }
- return menelaus_set_vmmc(mV);
- } else {
- if (!power_on)
- return menelaus_set_vdcdc(3, 0);
- switch (1 << vdd) {
- case MMC_VDD_33_34:
- case MMC_VDD_32_33:
- mV = 3300;
- break;
- case MMC_VDD_30_31:
- case MMC_VDD_29_30:
- mV = 3000;
- break;
- case MMC_VDD_28_29:
- case MMC_VDD_27_28:
- mV = 2800;
- break;
- case MMC_VDD_24_25:
- case MMC_VDD_23_24:
- mV = 2400;
- break;
- case MMC_VDD_22_23:
- case MMC_VDD_21_22:
- mV = 2200;
- break;
- case MMC_VDD_20_21:
- mV = 2000;
- break;
- case MMC_VDD_165_195:
- mV = 1800;
- break;
- default:
- BUG();
- }
- return menelaus_set_vdcdc(3, mV);
- }
- return 0;
-}
-
-static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on,
- int vdd)
-{
- if (board_is_n800() || slot == 0)
- return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd);
-
- /* The n810 power will be handled by GPIO code in the driver */
-
- return 0;
-}
-
-static int n8x0_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
-{
- int r;
-
- dev_dbg(dev, "Set slot %d bus mode %s\n", slot + 1,
- bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
- BUG_ON(slot != 0 && slot != 1);
- slot++;
- switch (bus_mode) {
- case MMC_BUSMODE_OPENDRAIN:
- r = menelaus_set_mmc_opendrain(slot, 1);
- break;
- case MMC_BUSMODE_PUSHPULL:
- r = menelaus_set_mmc_opendrain(slot, 0);
- break;
- default:
- BUG();
- }
- if (r != 0 && printk_ratelimit())
- dev_err(dev, "MMC: unable to set bus mode for slot %d\n",
- slot);
- return r;
-}
-
-static int n8x0_mmc_get_cover_state(struct device *dev, int slot)
-{
- slot++;
- BUG_ON(slot != 1 && slot != 2);
- if (slot == 1)
- return slot1_cover_open;
- else
- return slot2_cover_open;
-}
-
-static void n8x0_mmc_callback(void *data, u8 card_mask)
-{
-#ifdef CONFIG_MMC_OMAP
- int bit, *openp, index;
-
- if (board_is_n800()) {
- bit = 1 << 1;
- openp = &slot2_cover_open;
- index = 1;
- } else {
- bit = 1;
- openp = &slot1_cover_open;
- index = 0;
- }
-
- if (card_mask & bit)
- *openp = 1;
- else
- *openp = 0;
-
- omap_mmc_notify_cover_event(mmc_device, index, *openp);
-#else
- pr_warn("MMC: notify cover event not available\n");
-#endif
-}
-
-static int n8x0_mmc_late_init(struct device *dev)
-{
- int r, bit, *openp;
- int vs2sel;
-
- mmc_device = dev;
-
- r = menelaus_set_slot_sel(1);
- if (r < 0)
- return r;
-
- if (board_is_n800())
- vs2sel = 0;
- else
- vs2sel = 2;
-
- r = menelaus_set_mmc_slot(2, 0, vs2sel, 1);
- if (r < 0)
- return r;
-
- n8x0_mmc_set_power(dev, 0, MMC_POWER_ON, 16); /* MMC_VDD_28_29 */
- n8x0_mmc_set_power(dev, 1, MMC_POWER_ON, 16);
-
- r = menelaus_set_mmc_slot(1, 1, 0, 1);
- if (r < 0)
- return r;
- r = menelaus_set_mmc_slot(2, 1, vs2sel, 1);
- if (r < 0)
- return r;
-
- r = menelaus_get_slot_pin_states();
- if (r < 0)
- return r;
-
- if (board_is_n800()) {
- bit = 1 << 1;
- openp = &slot2_cover_open;
- } else {
- bit = 1;
- openp = &slot1_cover_open;
- slot2_cover_open = 0;
- }
-
- /* All slot pin bits seem to be inversed until first switch change */
- if (r == 0xf || r == (0xf & ~bit))
- r = ~r;
-
- if (r & bit)
- *openp = 1;
- else
- *openp = 0;
-
- r = menelaus_register_mmc_callback(n8x0_mmc_callback, NULL);
-
- return r;
-}
-
-static void n8x0_mmc_shutdown(struct device *dev)
-{
- int vs2sel;
-
- if (board_is_n800())
- vs2sel = 0;
- else
- vs2sel = 2;
-
- menelaus_set_mmc_slot(1, 0, 0, 0);
- menelaus_set_mmc_slot(2, 0, vs2sel, 0);
-}
-
-static void n8x0_mmc_cleanup(struct device *dev)
-{
- menelaus_unregister_mmc_callback();
-}
-
-/*
- * MMC controller1 has two slots that are multiplexed via I2C.
- * MMC controller2 is not in use.
- */
-static struct omap_mmc_platform_data mmc1_data = {
- .nr_slots = 0,
- .init = n8x0_mmc_late_init,
- .cleanup = n8x0_mmc_cleanup,
- .shutdown = n8x0_mmc_shutdown,
- .max_freq = 24000000,
- .slots[0] = {
- .wires = 4,
- .set_power = n8x0_mmc_set_power,
- .set_bus_mode = n8x0_mmc_set_bus_mode,
- .get_cover_state = n8x0_mmc_get_cover_state,
- .ocr_mask = MMC_VDD_165_195 | MMC_VDD_30_31 |
- MMC_VDD_32_33 | MMC_VDD_33_34,
- .name = "internal",
- },
- .slots[1] = {
- .set_power = n8x0_mmc_set_power,
- .set_bus_mode = n8x0_mmc_set_bus_mode,
- .get_cover_state = n8x0_mmc_get_cover_state,
- .ocr_mask = MMC_VDD_165_195 | MMC_VDD_20_21 |
- MMC_VDD_21_22 | MMC_VDD_22_23 |
- MMC_VDD_23_24 | MMC_VDD_24_25 |
- MMC_VDD_27_28 | MMC_VDD_28_29 |
- MMC_VDD_29_30 | MMC_VDD_30_31 |
- MMC_VDD_32_33 | MMC_VDD_33_34,
- .name = "external",
- },
-};
-
-static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC];
-
-static void __init n8x0_mmc_init(void)
-{
- if (board_is_n810()) {
- mmc1_data.slots[0].name = "external";
-
- /*
- * Some Samsung Movinand chips do not like open-ended
- * multi-block reads and fall to braind-dead state
- * while doing so. Reducing the number of blocks in
- * the transfer or delays in clock disable do not help
- */
- mmc1_data.slots[1].name = "internal";
- mmc1_data.slots[1].ban_openended = 1;
- gpiod_add_lookup_table(&nokia810_mmc_gpio_table);
- } else {
- gpiod_add_lookup_table(&nokia800_mmc_gpio_table);
- }
-
- mmc1_data.nr_slots = 2;
- mmc_data[0] = &mmc1_data;
-}
-#else
-static struct omap_mmc_platform_data mmc1_data;
-static void __init n8x0_mmc_init(void)
-{
-}
-#endif /* CONFIG_MMC_OMAP */
-
-#ifdef CONFIG_MENELAUS
-
-static int n8x0_auto_sleep_regulators(void)
-{
- u32 val;
- int ret;
-
- val = EN_VPLL_SLEEP | EN_VMMC_SLEEP \
- | EN_VAUX_SLEEP | EN_VIO_SLEEP \
- | EN_VMEM_SLEEP | EN_DC3_SLEEP \
- | EN_VC_SLEEP | EN_DC2_SLEEP;
-
- ret = menelaus_set_regulator_sleep(1, val);
- if (ret < 0) {
- pr_err("Could not set regulators to sleep on menelaus: %u\n",
- ret);
- return ret;
- }
- return 0;
-}
-
-static int n8x0_auto_voltage_scale(void)
-{
- int ret;
-
- ret = menelaus_set_vcore_hw(1400, 1050);
- if (ret < 0) {
- pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
- return ret;
- }
- return 0;
-}
-
-static int n8x0_menelaus_late_init(struct device *dev)
-{
- int ret;
-
- ret = n8x0_auto_voltage_scale();
- if (ret < 0)
- return ret;
- ret = n8x0_auto_sleep_regulators();
- if (ret < 0)
- return ret;
- return 0;
-}
-
-#else
-static int n8x0_menelaus_late_init(struct device *dev)
-{
- return 0;
-}
-#endif
-
-struct menelaus_platform_data n8x0_menelaus_platform_data = {
- .late_init = n8x0_menelaus_late_init,
-};
-
-static struct gpiod_lookup_table nokia810_asoc_gpio_table = {
- .dev_id = "soc-audio",
- .table = {
- GPIO_LOOKUP("gpio-0-15", 10, "headset", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-80-111", 21, "speaker", GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static int __init n8x0_late_initcall(void)
-{
- if (!board_caps)
- return -ENODEV;
-
- n8x0_mmc_init();
- n8x0_usb_init();
- gpiod_add_lookup_table(&nokia810_asoc_gpio_table);
-
- return 0;
-}
-omap_late_initcall(n8x0_late_initcall);
-
-/*
- * Legacy init pdata init for n8x0. Note that we want to follow the
- * I2C bus numbering starting at 0 for device tree like other omaps.
- */
-void * __init n8x0_legacy_init(void)
-{
- board_check_revision();
- return &mmc1_data;
-}
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
deleted file mode 100644
index 0edebf3355fa..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_dpll.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2-specific DPLL control functions
- *
- * Copyright (C) 2011 Nokia Corporation
- * Paul Walmsley
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "clock.h"
-#include "cm2xxx.h"
-#include "cm-regbits-24xx.h"
-
-/* Private functions */
-
-/**
- * _allow_idle - enable DPLL autoidle bits
- * @clk: struct clk * of the DPLL to operate on
- *
- * Enable DPLL automatic idle control. The DPLL will enter low-power
- * stop when its downstream clocks are gated. No return value.
- * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
- * instead. Add some mechanism to optionally enter this mode.
- */
-static void _allow_idle(struct clk_hw_omap *clk)
-{
- if (!clk || !clk->dpll_data)
- return;
-
- omap2xxx_cm_set_dpll_auto_low_power_stop();
-}
-
-/**
- * _deny_idle - prevent DPLL from automatically idling
- * @clk: struct clk * of the DPLL to operate on
- *
- * Disable DPLL automatic idle control. No return value.
- */
-static void _deny_idle(struct clk_hw_omap *clk)
-{
- if (!clk || !clk->dpll_data)
- return;
-
- omap2xxx_cm_set_dpll_disable_autoidle();
-}
-
-
-/* Public data */
-const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
- .allow_idle = _allow_idle,
- .deny_idle = _deny_idle,
-};
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
deleted file mode 100644
index 93f6d3cd9525..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ /dev/null
@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * DPLL + CORE_CLK composite clock functions
- *
- * Copyright (C) 2005-2008 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
- *
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
- *
- * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- * Gordon McNutt and RidgeRun, Inc.
- *
- * XXX The DPLL and CORE clocks should be split into two separate clock
- * types.
- */
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/clk/ti.h>
-#include <linux/io.h>
-
-#include "clock.h"
-#include "clock2xxx.h"
-#include "opp2xxx.h"
-#include "cm2xxx.h"
-#include "cm-regbits-24xx.h"
-#include "sdrc.h"
-#include "sram.h"
-
-/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
-
-/*
- * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx
- * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
- * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
- */
-static struct clk_hw_omap *dpll_core_ck;
-
-/**
- * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
- *
- * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
- * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
- * (the latter is unusual). This currently should be called with
- * struct clk *dpll_ck, which is a composite clock of dpll_ck and
- * core_ck.
- */
-unsigned long omap2xxx_clk_get_core_rate(void)
-{
- long long core_clk;
- u32 v;
-
- WARN_ON(!dpll_core_ck);
-
- core_clk = omap2_get_dpll_rate(dpll_core_ck);
-
- v = omap2xxx_cm_get_core_clk_src();
-
- if (v == CORE_CLK_SRC_32K)
- core_clk = 32768;
- else
- core_clk *= v;
-
- return core_clk;
-}
-
-/*
- * Uses the current prcm set to tell if a rate is valid.
- * You can go slower, but not faster within a given rate set.
- */
-static long omap2_dpllcore_round_rate(unsigned long target_rate)
-{
- u32 high, low, core_clk_src;
-
- core_clk_src = omap2xxx_cm_get_core_clk_src();
-
- if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
- high = curr_prcm_set->dpll_speed * 2;
- low = curr_prcm_set->dpll_speed;
- } else { /* DPLL clockout x 2 */
- high = curr_prcm_set->dpll_speed;
- low = curr_prcm_set->dpll_speed / 2;
- }
-
-#ifdef DOWN_VARIABLE_DPLL
- if (target_rate > high)
- return high;
- else
- return target_rate;
-#else
- if (target_rate > low)
- return high;
- else
- return low;
-#endif
-
-}
-
-unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return omap2xxx_clk_get_core_rate();
-}
-
-int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- struct clk_hw_omap *clk = to_clk_hw_omap(hw);
- u32 cur_rate, low, mult, div, valid_rate, done_rate;
- u32 bypass = 0;
- struct prcm_config tmpset;
- const struct dpll_data *dd;
-
- cur_rate = omap2xxx_clk_get_core_rate();
- mult = omap2xxx_cm_get_core_clk_src();
-
- if ((rate == (cur_rate / 2)) && (mult == 2)) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
- } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
- } else if (rate != cur_rate) {
- valid_rate = omap2_dpllcore_round_rate(rate);
- if (valid_rate != rate)
- return -EINVAL;
-
- if (mult == 1)
- low = curr_prcm_set->dpll_speed;
- else
- low = curr_prcm_set->dpll_speed / 2;
-
- dd = clk->dpll_data;
- if (!dd)
- return -EINVAL;
-
- tmpset.cm_clksel1_pll =
- omap_clk_ll_ops.clk_readl(&dd->mult_div1_reg);
- tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
- dd->div1_mask);
- div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
- tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config();
- tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
- if (rate > low) {
- tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
- mult = ((rate / 2) / 1000000);
- done_rate = CORE_CLK_SRC_DPLL_X2;
- } else {
- tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
- mult = (rate / 1000000);
- done_rate = CORE_CLK_SRC_DPLL;
- }
- tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
- tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
-
- /* Worst case */
- tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
-
- if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
- bypass = 1;
-
- /* For omap2xxx_sdrc_init_params() */
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
- /* Force dll lock mode */
- omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
- bypass);
-
- /* Errata: ret dll entry state */
- omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
- omap2xxx_sdrc_reprogram(done_rate, 0);
- }
-
- return 0;
-}
-
-/**
- * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
- * @clk: struct clk *dpll_ck
- *
- * Store a local copy of @clk in dpll_core_ck so other code can query
- * the core rate without having to clk_get(), which can sleep. Must
- * only be called once. No return value. XXX If the clock
- * registration process is ever changed such that dpll_ck is no longer
- * statically defined, this code may need to change to increment some
- * kind of use count on dpll_ck.
- */
-void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
-{
- WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
- dpll_core_ck = to_clk_hw_omap(hw);
-}
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
deleted file mode 100644
index 2b04e422b46c..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ /dev/null
@@ -1,259 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2xxx DVFS virtual clock functions
- *
- * Copyright (C) 2005-2008, 2012 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
- *
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
- *
- * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- * Gordon McNutt and RidgeRun, Inc.
- *
- * XXX Some of this code should be replaceable by the upcoming OPP layer
- * code. However, some notion of "rate set" is probably still necessary
- * for OMAP2xxx at least. Rate sets should be generalized so they can be
- * used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff
- * has in the past expressed a preference to use rate sets for OPP changes,
- * rather than dynamically recalculating the clock tree, so if someone wants
- * this badly enough to write the code to handle it, we should support it
- * as an option.
- */
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/cpufreq.h>
-#include <linux/slab.h>
-
-#include "soc.h"
-#include "clock.h"
-#include "clock2xxx.h"
-#include "opp2xxx.h"
-#include "cm2xxx.h"
-#include "cm-regbits-24xx.h"
-#include "sdrc.h"
-#include "sram.h"
-
-static u16 cpu_mask;
-
-const struct prcm_config *curr_prcm_set;
-const struct prcm_config *rate_table;
-
-/*
- * sys_ck_rate: the rate of the external high-frequency clock
- * oscillator on the board. Set by the SoC-specific clock init code.
- * Once set during a boot, will not change.
- */
-static unsigned long sys_ck_rate;
-
-/**
- * omap2_table_mpu_recalc - just return the MPU speed
- * @clk: virt_prcm_set struct clk
- *
- * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
- */
-static unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
- unsigned long parent_rate)
-{
- return curr_prcm_set->mpu_speed;
-}
-
-/*
- * Look for a rate equal or less than the target rate given a configuration set.
- *
- * What's not entirely clear is "which" field represents the key field.
- * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
- * just uses the ARM rates.
- */
-static int omap2_determine_rate_to_table(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- const struct prcm_config *ptr;
- long highest_rate;
-
- highest_rate = -EINVAL;
-
- for (ptr = rate_table; ptr->mpu_speed; ptr++) {
- if (!(ptr->flags & cpu_mask))
- continue;
- if (ptr->xtal_speed != sys_ck_rate)
- continue;
-
- highest_rate = ptr->mpu_speed;
-
- /* Can check only after xtal frequency check */
- if (ptr->mpu_speed <= req->rate)
- break;
- }
- req->rate = highest_rate;
-
- return 0;
-}
-
-/* Sets basic clocks based on the specified rate */
-static int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- u32 cur_rate, done_rate, bypass = 0;
- const struct prcm_config *prcm;
- unsigned long found_speed = 0;
- unsigned long flags;
-
- for (prcm = rate_table; prcm->mpu_speed; prcm++) {
- if (!(prcm->flags & cpu_mask))
- continue;
-
- if (prcm->xtal_speed != sys_ck_rate)
- continue;
-
- if (prcm->mpu_speed <= rate) {
- found_speed = prcm->mpu_speed;
- break;
- }
- }
-
- if (!found_speed) {
- printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
- rate / 1000000);
- return -EINVAL;
- }
-
- curr_prcm_set = prcm;
- cur_rate = omap2xxx_clk_get_core_rate();
-
- if (prcm->dpll_speed == cur_rate / 2) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
- } else if (prcm->dpll_speed == cur_rate * 2) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
- } else if (prcm->dpll_speed != cur_rate) {
- local_irq_save(flags);
-
- if (prcm->dpll_speed == prcm->xtal_speed)
- bypass = 1;
-
- if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
- CORE_CLK_SRC_DPLL_X2)
- done_rate = CORE_CLK_SRC_DPLL_X2;
- else
- done_rate = CORE_CLK_SRC_DPLL;
-
- omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu,
- prcm->cm_clksel_dsp,
- prcm->cm_clksel_gfx,
- prcm->cm_clksel1_core,
- prcm->cm_clksel_mdm);
-
- /* x2 to enter omap2xxx_sdrc_init_params() */
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
- omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
- bypass);
-
- omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
- omap2xxx_sdrc_reprogram(done_rate, 0);
-
- local_irq_restore(flags);
- }
-
- return 0;
-}
-
-/**
- * omap2xxx_clkt_vps_check_bootloader_rates - determine which of the rate
- * table sets matches the current CORE DPLL hardware rate
- *
- * Check the MPU rate set by bootloader. Sets the 'curr_prcm_set'
- * global to point to the active rate set when found; otherwise, sets
- * it to NULL. No return value;
- */
-static void omap2xxx_clkt_vps_check_bootloader_rates(void)
-{
- const struct prcm_config *prcm = NULL;
- unsigned long rate;
-
- rate = omap2xxx_clk_get_core_rate();
- for (prcm = rate_table; prcm->mpu_speed; prcm++) {
- if (!(prcm->flags & cpu_mask))
- continue;
- if (prcm->xtal_speed != sys_ck_rate)
- continue;
- if (prcm->dpll_speed <= rate)
- break;
- }
- curr_prcm_set = prcm;
-}
-
-/**
- * omap2xxx_clkt_vps_late_init - store a copy of the sys_ck rate
- *
- * Store a copy of the sys_ck rate for later use by the OMAP2xxx DVFS
- * code. (The sys_ck rate does not -- or rather, must not -- change
- * during kernel runtime.) Must be called after we have a valid
- * sys_ck rate, but before the virt_prcm_set clock rate is
- * recalculated. No return value.
- */
-static void omap2xxx_clkt_vps_late_init(void)
-{
- struct clk *c;
-
- c = clk_get(NULL, "sys_ck");
- if (IS_ERR(c)) {
- WARN(1, "could not locate sys_ck\n");
- } else {
- sys_ck_rate = clk_get_rate(c);
- clk_put(c);
- }
-}
-
-#ifdef CONFIG_OF
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-
-static const struct clk_ops virt_prcm_set_ops = {
- .recalc_rate = &omap2_table_mpu_recalc,
- .set_rate = &omap2_select_table_rate,
- .determine_rate = &omap2_determine_rate_to_table,
-};
-
-/**
- * omap2xxx_clkt_vps_init - initialize virt_prcm_set clock
- *
- * Does a manual init for the virtual prcm DVFS clock for OMAP2. This
- * function is called only from omap2 DT clock init, as the virtual
- * node is not modelled in the DT clock data.
- */
-void omap2xxx_clkt_vps_init(void)
-{
- struct clk_init_data init = { NULL };
- struct clk_hw_omap *hw = NULL;
- struct clk *clk;
- const char *parent_name = "mpu_ck";
-
- omap2xxx_clkt_vps_late_init();
- omap2xxx_clkt_vps_check_bootloader_rates();
-
- hw = kzalloc_obj(*hw);
- if (!hw)
- return;
- init.name = "virt_prcm_set";
- init.ops = &virt_prcm_set_ops;
- init.parent_names = &parent_name;
- init.num_parents = 1;
-
- hw->hw.init = &init;
-
- clk = clk_register(NULL, &hw->hw);
- if (IS_ERR(clk)) {
- printk(KERN_ERR "Failed to register clock\n");
- kfree(hw);
- return;
- }
-
- clkdev_create(clk, "cpufreq_ck", NULL);
-}
-#endif
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 83fae51722a9..b73a80503da8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -30,9 +30,7 @@
#include "clockdomain.h"
#include "clock.h"
#include "cm.h"
-#include "cm2xxx.h"
#include "cm3xxx.h"
-#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
#include "common.h"
@@ -94,11 +92,7 @@ void __init ti_clk_init_features(void)
}
/* Bypass value setup for DPLLs */
- if (cpu_is_omap24xx()) {
- features.dpll_bypass_vals |=
- (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
- (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
- } else if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx()) {
features.dpll_bypass_vals |=
(1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
@@ -122,9 +116,7 @@ void __init ti_clk_init_features(void)
* 34xx reverses this, just to keep us on our toes
* AM35xx uses both, depending on the module.
*/
- if (cpu_is_omap24xx())
- features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
- else if (cpu_is_omap34xx())
+ if (cpu_is_omap34xx())
features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
/* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
deleted file mode 100644
index 73c011dadfd2..000000000000
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * OMAP2 clock function prototypes and macros
- *
- * Copyright (C) 2005-2010 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
-
-#include <linux/clk-provider.h>
-#include "clock.h"
-
-unsigned long omap2xxx_clk_get_core_rate(void);
-
-#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 69dc5b839335..4b5ae1f40d50 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -1213,7 +1213,7 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
{
/* The clkdm attribute does not exist yet prior OMAP4 */
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ if (cpu_is_omap34xx())
return 0;
/*
@@ -1244,7 +1244,7 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
{
/* The clkdm attribute does not exist yet prior OMAP4 */
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ if (cpu_is_omap34xx())
return 0;
if (!oh)
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 86a2f9e5d0ef..2d422b5f121f 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,8 +216,6 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
void clkdm_save_context(void);
void clkdm_restore_context(void);
-extern void __init omap242x_clockdomains_init(void);
-extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
extern void __init ti814x_clockdomains_init(void);
@@ -230,14 +228,11 @@ void am43xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
extern void clkdm_del_autodeps(struct clockdomain *clkdm);
-extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
extern struct clkdm_ops omap4_clkdm_operations;
extern struct clkdm_ops am33xx_clkdm_operations;
extern struct clkdm_ops am43xx_clkdm_operations;
-extern struct clkdm_dep gfx_24xx_wkdeps[];
-extern struct clkdm_dep dsp_24xx_wkdeps[];
extern struct clockdomain wkup_common_clkdm;
#endif
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
deleted file mode 100644
index ac4ffb5d2ffc..000000000000
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ /dev/null
@@ -1,154 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * OMAP2420 clockdomains
- *
- * Copyright (C) 2008-2011 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Paul Walmsley, Jouni Högander
- *
- * This file contains clockdomains and clockdomain wakeup dependencies
- * for OMAP2420 chips. Some notes:
- *
- * A useful validation rule for struct clockdomain: Any clockdomain
- * referenced by a wkdep_srcs must have a dep_bit assigned. So
- * wkdep_srcs are really just software-controllable dependencies.
- * Non-software-controllable dependencies do exist, but they are not
- * encoded below (yet).
- *
- * 24xx does not support programmable sleep dependencies (SLEEPDEP)
- *
- * The overly-specific dep_bit names are due to a bit name collision
- * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
- * value are the same for all powerdomains: 2
- *
- * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
- * sanity check?
- * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
- */
-
-/*
- * To-Do List
- * -> Port the Sleep/Wakeup dependencies for the domains
- * from the Power domain framework
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "clockdomain.h"
-#include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
-#include "prm-regbits-24xx.h"
-
-/*
- * Clockdomain dependencies for wkdeps
- *
- * XXX Hardware dependencies (e.g., dependencies that cannot be
- * changed in software) are not included here yet, but should be.
- */
-
-/* Wakeup dependency source arrays */
-
-/* 2420-specific possible wakeup dependencies */
-
-/* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
-static struct clkdm_dep mpu_2420_wkdeps[] = {
- { .clkdm_name = "core_l3_clkdm" },
- { .clkdm_name = "core_l4_clkdm" },
- { .clkdm_name = "dsp_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { NULL },
-};
-
-/* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
-static struct clkdm_dep core_2420_wkdeps[] = {
- { .clkdm_name = "dsp_clkdm" },
- { .clkdm_name = "gfx_clkdm" },
- { .clkdm_name = "mpu_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { NULL },
-};
-
-/*
- * 2420-only clockdomains
- */
-
-static struct clockdomain mpu_2420_clkdm = {
- .name = "mpu_clkdm",
- .pwrdm = { .name = "mpu_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .wkdep_srcs = mpu_2420_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
-};
-
-static struct clockdomain iva1_2420_clkdm = {
- .name = "iva1_clkdm",
- .pwrdm = { .name = "dsp_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
- .wkdep_srcs = dsp_24xx_wkdeps,
- .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
-};
-
-static struct clockdomain dsp_2420_clkdm = {
- .name = "dsp_clkdm",
- .pwrdm = { .name = "dsp_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-};
-
-static struct clockdomain gfx_2420_clkdm = {
- .name = "gfx_clkdm",
- .pwrdm = { .name = "gfx_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .wkdep_srcs = gfx_24xx_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-};
-
-static struct clockdomain core_l3_2420_clkdm = {
- .name = "core_l3_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .wkdep_srcs = core_2420_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-};
-
-static struct clockdomain core_l4_2420_clkdm = {
- .name = "core_l4_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .wkdep_srcs = core_2420_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-};
-
-static struct clockdomain dss_2420_clkdm = {
- .name = "dss_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-};
-
-static struct clockdomain *clockdomains_omap242x[] __initdata = {
- &wkup_common_clkdm,
- &mpu_2420_clkdm,
- &iva1_2420_clkdm,
- &dsp_2420_clkdm,
- &gfx_2420_clkdm,
- &core_l3_2420_clkdm,
- &core_l4_2420_clkdm,
- &dss_2420_clkdm,
- NULL,
-};
-
-void __init omap242x_clockdomains_init(void)
-{
- if (!cpu_is_omap242x())
- return;
-
- clkdm_register_platform_funcs(&omap2_clkdm_operations);
- clkdm_register_clkdms(clockdomains_omap242x);
- clkdm_complete_init();
-}
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
deleted file mode 100644
index 0e97e178abaa..000000000000
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ /dev/null
@@ -1,181 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * OMAP2xxx clockdomains
- *
- * Copyright (C) 2008-2009 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Paul Walmsley, Jouni Högander
- *
- * This file contains clockdomains and clockdomain wakeup dependencies
- * for OMAP2xxx chips. Some notes:
- *
- * A useful validation rule for struct clockdomain: Any clockdomain
- * referenced by a wkdep_srcs must have a dep_bit assigned. So
- * wkdep_srcs are really just software-controllable dependencies.
- * Non-software-controllable dependencies do exist, but they are not
- * encoded below (yet).
- *
- * 24xx does not support programmable sleep dependencies (SLEEPDEP)
- *
- * The overly-specific dep_bit names are due to a bit name collision
- * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
- * value are the same for all powerdomains: 2
- *
- * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
- * sanity check?
- * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
- */
-
-/*
- * To-Do List
- * -> Port the Sleep/Wakeup dependencies for the domains
- * from the Power domain framework
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "clockdomain.h"
-#include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
-#include "prm-regbits-24xx.h"
-
-/*
- * Clockdomain dependencies for wkdeps
- *
- * XXX Hardware dependencies (e.g., dependencies that cannot be
- * changed in software) are not included here yet, but should be.
- */
-
-/* Wakeup dependency source arrays */
-
-/* 2430-specific possible wakeup dependencies */
-
-/* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
-static struct clkdm_dep core_2430_wkdeps[] = {
- { .clkdm_name = "dsp_clkdm" },
- { .clkdm_name = "gfx_clkdm" },
- { .clkdm_name = "mpu_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { .clkdm_name = "mdm_clkdm" },
- { NULL },
-};
-
-/* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
-static struct clkdm_dep mpu_2430_wkdeps[] = {
- { .clkdm_name = "core_l3_clkdm" },
- { .clkdm_name = "core_l4_clkdm" },
- { .clkdm_name = "dsp_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { .clkdm_name = "mdm_clkdm" },
- { NULL },
-};
-
-/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
-static struct clkdm_dep mdm_2430_wkdeps[] = {
- { .clkdm_name = "core_l3_clkdm" },
- { .clkdm_name = "core_l4_clkdm" },
- { .clkdm_name = "mpu_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { NULL },
-};
-
-/*
- * 2430-only clockdomains
- */
-
-static struct clockdomain mpu_2430_clkdm = {
- .name = "mpu_clkdm",
- .pwrdm = { .name = "mpu_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .wkdep_srcs = mpu_2430_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
-};
-
-/* Another case of bit name collisions between several registers: EN_MDM */
-static struct clockdomain mdm_clkdm = {
- .name = "mdm_clkdm",
- .pwrdm = { .name = "mdm_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
- .wkdep_srcs = mdm_2430_wkdeps,
- .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
-};
-
-static struct clockdomain dsp_2430_clkdm = {
- .name = "dsp_clkdm",
- .pwrdm = { .name = "dsp_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
- .wkdep_srcs = dsp_24xx_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-};
-
-static struct clockdomain gfx_2430_clkdm = {
- .name = "gfx_clkdm",
- .pwrdm = { .name = "gfx_pwrdm" },
- .flags = CLKDM_CAN_HWSUP_SWSUP,
- .wkdep_srcs = gfx_24xx_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-};
-
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l3_2430_clkdm = {
- .name = "core_l3_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .dep_bit = OMAP24XX_EN_CORE_SHIFT,
- .wkdep_srcs = core_2430_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-};
-
-/*
- * XXX add usecounting for clkdm dependencies, otherwise the presence
- * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
- * could cause trouble
- */
-static struct clockdomain core_l4_2430_clkdm = {
- .name = "core_l4_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .dep_bit = OMAP24XX_EN_CORE_SHIFT,
- .wkdep_srcs = core_2430_wkdeps,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-};
-
-static struct clockdomain dss_2430_clkdm = {
- .name = "dss_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .flags = CLKDM_CAN_HWSUP,
- .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-};
-
-static struct clockdomain *clockdomains_omap243x[] __initdata = {
- &wkup_common_clkdm,
- &mpu_2430_clkdm,
- &mdm_clkdm,
- &dsp_2430_clkdm,
- &gfx_2430_clkdm,
- &core_l3_2430_clkdm,
- &core_l4_2430_clkdm,
- &dss_2430_clkdm,
- NULL,
-};
-
-void __init omap243x_clockdomains_init(void)
-{
- if (!cpu_is_omap243x())
- return;
-
- clkdm_register_platform_funcs(&omap2_clkdm_operations);
- clkdm_register_clkdms(clockdomains_omap243x);
- clkdm_complete_init();
-}
-
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 220c22f5e0f5..4d20c2720660 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -8,7 +8,7 @@
* Paul Walmsley, Jouni Högander
*
* This file contains clockdomains and clockdomain wakeup/sleep
- * dependencies for the OMAP2/3 chips. Some notes:
+ * dependencies for the OMAP3 chips. Some notes:
*
* A useful validation rule for struct clockdomain: Any clockdomain
* referenced by a wkdep_srcs or sleepdep_srcs array must have a
@@ -16,8 +16,6 @@
* software-controllable dependencies. Non-software-controllable
* dependencies do exist, but they are not encoded below (yet).
*
- * 24xx does not support programmable sleep dependencies (SLEEPDEP)
- *
* The overly-specific dep_bit names are due to a bit name collision
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
* value are the same for all powerdomains: 2
@@ -39,10 +37,8 @@
#include "clockdomain.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
#include "cm-regbits-44xx.h"
-#include "prm-regbits-24xx.h"
#include "prm-regbits-34xx.h"
/*
@@ -54,29 +50,8 @@
/* Wakeup dependency source arrays */
-/* 2xxx-specific possible dependencies */
-
-/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */
-struct clkdm_dep gfx_24xx_wkdeps[] = {
- { .clkdm_name = "core_l3_clkdm" },
- { .clkdm_name = "core_l4_clkdm" },
- { .clkdm_name = "mpu_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { NULL },
-};
-
-/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */
-struct clkdm_dep dsp_24xx_wkdeps[] = {
- { .clkdm_name = "core_l3_clkdm" },
- { .clkdm_name = "core_l4_clkdm" },
- { .clkdm_name = "mpu_clkdm" },
- { .clkdm_name = "wkup_clkdm" },
- { NULL },
-};
-
-
/*
- * OMAP2/3-common clockdomains
+ * OMAP3-common clockdomains
*
* Even though the 2420 has a single PRCM module from the
* interconnect's perspective, internally it does appear to have
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
deleted file mode 100644
index 59c14dbb6f87..000000000000
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
-#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
-
-/*
- * OMAP24XX Clock Management register bits
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
- *
- * Written by Paul Walmsley
- */
-
-#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
-#define OMAP24XX_EN_DSS1_MASK (1 << 0)
-#define OMAP24XX_ST_MAILBOXES_SHIFT 30
-#define OMAP24XX_ST_HDQ_SHIFT 23
-#define OMAP2420_ST_I2C2_SHIFT 20
-#define OMAP2430_ST_I2CHS1_SHIFT 19
-#define OMAP2420_ST_I2C1_SHIFT 19
-#define OMAP2430_ST_I2CHS2_SHIFT 20
-#define OMAP24XX_ST_MCBSP2_SHIFT 16
-#define OMAP24XX_ST_MCBSP1_SHIFT 15
-#define OMAP2430_ST_MCBSP5_SHIFT 5
-#define OMAP2430_ST_MCBSP4_SHIFT 4
-#define OMAP2430_ST_MCBSP3_SHIFT 3
-#define OMAP24XX_ST_AES_SHIFT 3
-#define OMAP24XX_ST_RNG_SHIFT 2
-#define OMAP24XX_ST_SHA_SHIFT 1
-#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
-#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
-#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
-#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
-#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
-#define OMAP24XX_ST_MPU_WDT_SHIFT 3
-#define OMAP24XX_ST_32KSYNC_SHIFT 1
-#define OMAP24XX_EN_54M_PLL_SHIFT 6
-#define OMAP24XX_EN_96M_PLL_SHIFT 2
-#define OMAP24XX_ST_54M_APLL_SHIFT 9
-#define OMAP24XX_ST_96M_APLL_SHIFT 8
-#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
-#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
-#define OMAP24XX_AUTO_DPLL_SHIFT 0
-#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
-#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
-#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
-#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
-#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
-#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
-#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
-#endif
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
deleted file mode 100644
index 1c6d69f4bf49..000000000000
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ /dev/null
@@ -1,302 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2xxx CM module functions
- *
- * Copyright (C) 2009 Nokia Corporation
- * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
- * Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include "prm2xxx.h"
-#include "cm.h"
-#include "cm2xxx.h"
-#include "cm-regbits-24xx.h"
-#include "clockdomain.h"
-
-/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
-#define DPLL_AUTOIDLE_DISABLE 0x0
-#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
-
-/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
-#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
-#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
-
-/* CM_IDLEST_PLL bit value offset for APLLs (OMAP2xxx only) */
-#define EN_APLL_LOCKED 3
-
-static const u8 omap2xxx_cm_idlest_offs[] = {
- CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
-};
-
-/*
- *
- */
-
-static void _write_clktrctrl(u8 c, s16 module, u32 mask)
-{
- u32 v;
-
- v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
- v &= ~mask;
- v |= c << __ffs(mask);
- omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
-}
-
-static bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
-{
- u32 v;
-
- v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
- v &= mask;
- v >>= __ffs(mask);
-
- return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
-}
-
-static void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
-{
- _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
-}
-
-static void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
-{
- _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
-}
-
-/*
- * DPLL autoidle control
- */
-
-static void _omap2xxx_set_dpll_autoidle(u8 m)
-{
- u32 v;
-
- v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
- v &= ~OMAP24XX_AUTO_DPLL_MASK;
- v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
- omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
-}
-
-void omap2xxx_cm_set_dpll_disable_autoidle(void)
-{
- _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
-}
-
-void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
-{
- _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
-}
-
-/**
- * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
- * @idlest_reg: CM_IDLEST* virtual address
- * @prcm_inst: pointer to an s16 to return the PRCM instance offset
- * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
- *
- * XXX This function is only needed until absolute register addresses are
- * removed from the OMAP struct clk records.
- */
-static int omap2xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
- s16 *prcm_inst,
- u8 *idlest_reg_id)
-{
- unsigned long offs;
- u8 idlest_offs;
- int i;
-
- idlest_offs = idlest_reg->offset & 0xff;
- for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) {
- if (idlest_offs == omap2xxx_cm_idlest_offs[i]) {
- *idlest_reg_id = i + 1;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs))
- return -EINVAL;
-
- offs = idlest_reg->offset;
- offs &= 0xff00;
- *prcm_inst = offs;
-
- return 0;
-}
-
-/*
- *
- */
-
-/**
- * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
- * @part: PRCM partition, ignored for OMAP2
- * @prcm_mod: PRCM module offset
- * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
- * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
- *
- * Wait for the PRCM to indicate that the module identified by
- * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
- * success or -EBUSY if the module doesn't enable in time.
- */
-static int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
- u8 idlest_shift)
-{
- int ena = 0, i = 0;
- u8 cm_idlest_reg;
- u32 mask;
-
- if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
- return -EINVAL;
-
- cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];
-
- mask = 1 << idlest_shift;
- ena = mask;
-
- omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
- mask) == ena), MAX_MODULE_READY_TIME, i);
-
- return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
-}
-
-/* Clockdomain low-level functions */
-
-static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
-{
- omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- clkdm->clktrctrl_mask);
-}
-
-static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
-{
- omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- clkdm->clktrctrl_mask);
-}
-
-static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
-{
- bool hwsup = false;
-
- if (!clkdm->clktrctrl_mask)
- return 0;
-
- hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- clkdm->clktrctrl_mask);
- if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
- omap2xxx_clkdm_wakeup(clkdm);
-
- return 0;
-}
-
-static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
-{
- bool hwsup = false;
-
- if (!clkdm->clktrctrl_mask)
- return 0;
-
- hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- clkdm->clktrctrl_mask);
-
- if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
- omap2xxx_clkdm_sleep(clkdm);
-
- return 0;
-}
-
-struct clkdm_ops omap2_clkdm_operations = {
- .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
- .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
- .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
- .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
- .clkdm_sleep = omap2xxx_clkdm_sleep,
- .clkdm_wakeup = omap2xxx_clkdm_wakeup,
- .clkdm_allow_idle = omap2xxx_clkdm_allow_idle,
- .clkdm_deny_idle = omap2xxx_clkdm_deny_idle,
- .clkdm_clk_enable = omap2xxx_clkdm_clk_enable,
- .clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
-};
-
-int omap2xxx_cm_fclks_active(void)
-{
- u32 f1, f2;
-
- f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
- f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-
- return (f1 | f2) ? 1 : 0;
-}
-
-int omap2xxx_cm_mpu_retention_allowed(void)
-{
- u32 l;
-
- /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
- l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
- if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
- OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
- OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
- return 0;
- /* Check for UART3. */
- l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
- if (l & OMAP24XX_EN_UART3_MASK)
- return 0;
-
- return 1;
-}
-
-u32 omap2xxx_cm_get_core_clk_src(void)
-{
- u32 v;
-
- v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
- v &= OMAP24XX_CORE_CLK_SRC_MASK;
-
- return v;
-}
-
-u32 omap2xxx_cm_get_core_pll_config(void)
-{
- return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-}
-
-void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
-{
- u32 tmp;
-
- omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
- omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
- omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
- tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
- OMAP24XX_CLKSEL_DSS2_MASK;
- omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
- if (mdm)
- omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
-}
-
-/*
- *
- */
-
-static const struct cm_ll_data omap2xxx_cm_ll_data = {
- .split_idlest_reg = &omap2xxx_cm_split_idlest_reg,
- .wait_module_ready = &omap2xxx_cm_wait_module_ready,
-};
-
-int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
-{
- return cm_register(&omap2xxx_cm_ll_data);
-}
-
-static void __exit omap2xxx_cm_exit(void)
-{
- cm_unregister(&omap2xxx_cm_ll_data);
-}
-__exitcall(omap2xxx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
deleted file mode 100644
index 7cbeff15ffb0..000000000000
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * OMAP2xxx Clock Management (CM) register definitions
- *
- * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
- * Paul Walmsley
- *
- * The CM hardware modules on the OMAP2/3 are quite similar to each
- * other. The CM modules/instances on OMAP4 are quite different, so
- * they are handled in a separate file.
- */
-#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
-#define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
-
-#include "prcm-common.h"
-#include "cm2xxx_3xxx.h"
-
-#define OMAP2420_CM_REGADDR(module, reg) \
- OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
-#define OMAP2430_CM_REGADDR(module, reg) \
- OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
-
-/*
- * Module specific CM register offsets from CM_BASE + domain offset
- * Use cm_{read,write}_mod_reg() with these registers.
- * These register offsets generally appear in more than one PRCM submodule.
- */
-
-/* OMAP2-specific register offsets */
-
-#define OMAP24XX_CM_FCLKEN2 0x0004
-#define OMAP24XX_CM_ICLKEN4 0x001c
-#define OMAP24XX_CM_AUTOIDLE4 0x003c
-#define OMAP24XX_CM_IDLEST4 0x002c
-
-/* CM_IDLEST bit field values to indicate deasserted IdleReq */
-
-#define OMAP24XX_CM_IDLEST_VAL 0
-
-
-/* Clock management domain register get/set */
-
-#ifndef __ASSEMBLER__
-
-extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
-extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
-
-extern int omap2xxx_cm_fclks_active(void);
-extern int omap2xxx_cm_mpu_retention_allowed(void);
-extern u32 omap2xxx_cm_get_core_clk_src(void);
-extern u32 omap2xxx_cm_get_core_pll_config(void);
-extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
- u32 mdm);
-
-int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 87f2c2d2d754..fc16cd1fd2d5 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -15,7 +15,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
-#include "cm2xxx.h"
#include "cm3xxx.h"
#include "cm33xx.h"
#include "cm44xx.h"
@@ -230,14 +229,6 @@ static struct omap_prcm_init_data cm2_data __initdata = {
};
#endif
-#ifdef CONFIG_ARCH_OMAP2
-static struct omap_prcm_init_data omap2_prcm_data __initdata = {
- .index = TI_CLKM_CM,
- .init = omap2xxx_cm_init,
- .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
-};
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
static struct omap_prcm_init_data omap3_cm_data __initdata = {
.index = TI_CLKM_CM,
@@ -269,9 +260,6 @@ static struct omap_prcm_init_data am4_prcm_data __initdata = {
#endif
static const struct of_device_id omap_cm_dt_match_table[] __initconst = {
-#ifdef CONFIG_ARCH_OMAP2
- { .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data },
-#endif
#ifdef CONFIG_ARCH_OMAP3
{ .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
deleted file mode 100644
index 69694af71475..000000000000
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __OMAP_COMMON_BOARD_DEVICES__
-#define __OMAP_COMMON_BOARD_DEVICES__
-
-#include <linux/mfd/menelaus.h>
-
-void *n8x0_legacy_init(void);
-
-extern struct menelaus_platform_data n8x0_menelaus_platform_data;
-
-#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 9d60799e9752..f8ed97044ade 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -102,8 +102,6 @@ static inline void omap5_realtime_timer_init(void)
}
#endif
-void omap2420_init_early(void);
-void omap2430_init_early(void);
void omap3430_init_early(void);
void omap3630_init_early(void);
void am33xx_init_early(void);
@@ -130,14 +128,6 @@ static inline void omap_soc_device_init(void)
}
#endif
-#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
-#else
-static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
-{
-}
-#endif
-
#ifdef CONFIG_SOC_AM33XX
void am33xx_restart(enum reboot_mode mode, const char *cmd);
#else
@@ -183,8 +173,6 @@ static inline void omap_barrier_reserve_memblock(void)
/* This gets called from mach-omap2/io.c, do not call this */
void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
-void __init omap242x_map_io(void);
-void __init omap243x_map_io(void);
void __init omap3_map_io(void);
void __init am33xx_map_io(void);
void __init omap4_map_io(void);
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 7e7440533bf9..3ab1c6e6dde6 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -19,19 +19,11 @@
#include "am33xx.h"
#ifndef __ASSEMBLY__
-#define OMAP242X_CTRL_REGADDR(reg) \
- OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg) \
- OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
#define AM33XX_CTRL_REGADDR(reg) \
AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
#else
-#define OMAP242X_CTRL_REGADDR(reg) \
- OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg) \
- OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
#define AM33XX_CTRL_REGADDR(reg) \
@@ -74,52 +66,6 @@
#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
-/* 242x-only CONTROL_GENERAL register offsets */
-#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
-#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
-
-/* 243x-only CONTROL_GENERAL register offsets */
-/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
-#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
-#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
-#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
-#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
-#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
-#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
-
-/* 24xx-only CONTROL_GENERAL register offsets */
-#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
-#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
-#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
-#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
-#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
-#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
-#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
-#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
-#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
-#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
-#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
-#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
-#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
-#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
-#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
-#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
-#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
-#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
-#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
-#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
-#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
-#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
-#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
-#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
-#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
-#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
-#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
-#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
-#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
-#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
-#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
-
#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
/* 34xx-only CONTROL_GENERAL register offsets */
@@ -311,14 +257,12 @@
*/
/* CONTROL_DEVCONF0 bits */
#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
-#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
#define OMAP2_MCBSP1_FSR_MASK (1 << 4)
#define OMAP2_MCBSP1_CLKR_MASK (1 << 3)
#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
/* CONTROL_DEVCONF1 bits */
-#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index dbec3bb9fbf4..addc14898bd5 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -124,9 +124,7 @@ static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
static enum omapdss_version __init omap_display_get_version(void)
{
- if (cpu_is_omap24xx())
- return OMAPDSS_VER_OMAP24xx;
- else if (cpu_is_omap3630())
+ if (cpu_is_omap3630())
return OMAPDSS_VER_OMAP3630;
else if (cpu_is_omap34xx()) {
if (soc_is_am35xx()) {
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 830cd4e7eb44..3a6b7b4620ca 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -82,39 +82,6 @@ static unsigned configure_dma_errata(void)
{
unsigned errata = 0;
- /*
- * Errata applicable for OMAP2430ES1.0 and all omap2420
- *
- * I.
- * Erratum ID: Not Available
- * Inter Frame DMA buffering issue DMA will wrongly
- * buffer elements if packing and bursting is enabled. This might
- * result in data gets stalled in FIFO at the end of the block.
- * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
- * guarantee no data will stay in the DMA FIFO in case inter frame
- * buffering occurs
- *
- * II.
- * Erratum ID: Not Available
- * DMA may hang when several channels are used in parallel
- * In the following configuration, DMA channel hanging can occur:
- * a. Channel i, hardware synchronized, is enabled
- * b. Another channel (Channel x), software synchronized, is enabled.
- * c. Channel i is disabled before end of transfer
- * d. Channel i is reenabled.
- * e. Steps 1 to 4 are repeated a certain number of times.
- * f. A third channel (Channel y), software synchronized, is enabled.
- * Channel x and Channel y may hang immediately after step 'f'.
- * Workaround:
- * For any channel used - make sure NextLCH_ID is set to the value j.
- */
- if (cpu_is_omap2420() || (cpu_is_omap2430() &&
- (omap_type() == OMAP2430_REV_ES1_0))) {
-
- SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
- SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
- }
-
/*
* Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
* after a transaction error.
@@ -162,16 +129,6 @@ static unsigned configure_dma_errata(void)
return errata;
}
-static const struct dma_slave_map omap24xx_sdma_dt_map[] = {
- /* external DMA requests when tusb6010 is used */
- { "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) },
- { "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) },
- { "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */
- { "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */
- { "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */
- { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
-};
-
static struct omap_dma_dev_attr dma_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32,
@@ -188,15 +145,7 @@ struct omap_system_dma_plat_info dma_plat_info = {
static int __init omap2_system_dma_init(void)
{
dma_plat_info.errata = configure_dma_errata();
-
- if (soc_is_omap24xx()) {
- /* DMA slave map for drivers not yet converted to DT */
- dma_plat_info.slave_map = omap24xx_sdma_dt_map;
- dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
- }
-
- if (!soc_is_omap242x())
- dma_attr.dev_caps |= IS_RW_PRIORITY;
+ dma_attr.dev_caps |= IS_RW_PRIORITY;
if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c
index 0f8c8efe3ae8..9a425c36f996 100644
--- a/arch/arm/mach-omap2/fb.c
+++ b/arch/arm/mach-omap2/fb.c
@@ -27,15 +27,6 @@
* The first memory resource is the register region for VRFB,
* the rest are VRFB virtual memory areas for each VRFB context.
*/
-
-static const struct resource omap2_vrfb_resources[] = {
- DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
- DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
- DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
- DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
- DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
-};
-
static const struct resource omap3_vrfb_resources[] = {
DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
@@ -58,10 +49,7 @@ int __init omap_init_vrfb(void)
const struct resource *res;
unsigned int num_res;
- if (cpu_is_omap24xx()) {
- res = omap2_vrfb_resources;
- num_res = ARRAY_SIZE(omap2_vrfb_resources);
- } else if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx()) {
res = omap3_vrfb_resources;
num_res = ARRAY_SIZE(omap3_vrfb_resources);
} else {
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
deleted file mode 100644
index e060f1b5c27d..000000000000
--- a/arch/arm/mach-omap2/gpmc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * General-Purpose Memory Controller for OMAP2
- *
- * Copyright (C) 2005-2006 Nokia Corporation
- *
- * Do not include this file in any new code, this will get removed
- * once omap3 boots in device tree only mode.
- */
-#include <linux/omap-gpmc.h>
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index 3b4b9514f4fa..d956c70f8899 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -39,7 +39,7 @@ int omap_i2c_reset(struct omap_hwmod *oh)
u16 i2c_con;
int c = 0;
- if (soc_is_omap24xx() || soc_is_omap34xx() || soc_is_am35xx())
+ if (soc_is_omap34xx() || soc_is_am35xx())
i2c_con = OMAP2_I2C_CON_OFFSET;
else
i2c_con = OMAP4_I2C_CON_OFFSET;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index cf2bfb447ee2..3e731dd21311 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -55,9 +55,7 @@ int omap_type(void)
if (val < OMAP2_DEVICETYPE_MASK)
return val;
- if (soc_is_omap24xx()) {
- val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
- } else if (soc_is_ti81xx()) {
+ if (soc_is_ti81xx()) {
val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
} else if (soc_is_am33xx() || soc_is_am43xx()) {
val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
@@ -99,22 +97,6 @@ EXPORT_SYMBOL(omap_type);
#define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
-struct omap_id {
- u16 hawkeye; /* Silicon type (Hawkeye id) */
- u8 dev; /* Device type from production_id reg */
- u32 type; /* Combined type id copied to omap_revision */
-};
-
-/* Register values to detect the OMAP version */
-static struct omap_id omap_ids[] __initdata = {
- { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
- { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
- { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
- { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
- { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
- { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
-};
-
static void __iomem *tap_base;
static u16 tap_prod_id;
@@ -145,62 +127,6 @@ static int __init omap_feed_randpool(void)
}
omap_device_initcall(omap_feed_randpool);
-void __init omap2xxx_check_revision(void)
-{
- int i, j;
- u32 idcode, prod_id;
- u16 hawkeye;
- u8 dev_type, rev;
- struct omap_die_id odi;
-
- idcode = read_tap_reg(OMAP_TAP_IDCODE);
- prod_id = read_tap_reg(tap_prod_id);
- hawkeye = (idcode >> 12) & 0xffff;
- rev = (idcode >> 28) & 0x0f;
- dev_type = (prod_id >> 16) & 0x0f;
- omap_get_die_id(&odi);
-
- pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
- idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
- pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
- pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
- odi.id_1, (odi.id_1 >> 28) & 0xf);
- pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
- pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
- pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
- prod_id, dev_type);
-
- /* Check hawkeye ids */
- for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
- if (hawkeye == omap_ids[i].hawkeye)
- break;
- }
-
- if (i == ARRAY_SIZE(omap_ids)) {
- printk(KERN_ERR "Unknown OMAP CPU id\n");
- return;
- }
-
- for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
- if (dev_type == omap_ids[j].dev)
- break;
- }
-
- if (j == ARRAY_SIZE(omap_ids)) {
- pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
- omap_ids[i].type >> 16);
- j = i;
- }
-
- sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
- sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
-
- pr_info("%s", soc_name);
- if ((omap_rev() >> 8) & 0x0f)
- pr_cont("%s", soc_rev);
- pr_cont("\n");
-}
-
#define OMAP3_SHOW_FEATURE(feat) \
if (omap3_has_ ##feat()) \
n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
@@ -750,9 +676,7 @@ static const char * const omap_types[] = {
static const char * __init omap_get_family(void)
{
- if (soc_is_omap24xx())
- return kasprintf(GFP_KERNEL, "OMAP2");
- else if (soc_is_omap34xx())
+ if (soc_is_omap34xx())
return kasprintf(GFP_KERNEL, "OMAP3");
else if (soc_is_omap44xx())
return kasprintf(GFP_KERNEL, "OMAP4");
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 14ec3f78000b..1c945be5e7cc 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -35,7 +35,6 @@
#include "sdrc.h"
#include "control.h"
#include "sram.h"
-#include "cm2xxx.h"
#include "cm3xxx.h"
#include "cm33xx.h"
#include "cm44xx.h"
@@ -43,11 +42,9 @@
#include "cm.h"
#include "prcm_mpu44xx.h"
#include "prminst44xx.h"
-#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm33xx.h"
#include "prm44xx.h"
-#include "opp2xxx.h"
#include "omap-secure.h"
/*
@@ -61,76 +58,6 @@ static int (*omap_clk_soc_init)(void);
* default mapping provided here.
*/
-#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-static struct map_desc omap24xx_io_desc[] __initdata = {
- {
- .virtual = L3_24XX_VIRT,
- .pfn = __phys_to_pfn(L3_24XX_PHYS),
- .length = L3_24XX_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = L4_24XX_VIRT,
- .pfn = __phys_to_pfn(L4_24XX_PHYS),
- .length = L4_24XX_SIZE,
- .type = MT_DEVICE
- },
-};
-
-#ifdef CONFIG_SOC_OMAP2420
-static struct map_desc omap242x_io_desc[] __initdata = {
- {
- .virtual = DSP_MEM_2420_VIRT,
- .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
- .length = DSP_MEM_2420_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = DSP_IPI_2420_VIRT,
- .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
- .length = DSP_IPI_2420_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = DSP_MMU_2420_VIRT,
- .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
- .length = DSP_MMU_2420_SIZE,
- .type = MT_DEVICE
- },
-};
-
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-static struct map_desc omap243x_io_desc[] __initdata = {
- {
- .virtual = L4_WK_243X_VIRT,
- .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
- .length = L4_WK_243X_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = OMAP243X_GPMC_VIRT,
- .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
- .length = OMAP243X_GPMC_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = OMAP243X_SDRC_VIRT,
- .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
- .length = OMAP243X_SDRC_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = OMAP243X_SMS_VIRT,
- .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
- .length = OMAP243X_SMS_SIZE,
- .type = MT_DEVICE
- },
-};
-#endif
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
static struct map_desc omap34xx_io_desc[] __initdata = {
{
@@ -305,22 +232,6 @@ static struct map_desc dra7xx_io_desc[] __initdata = {
};
#endif
-#ifdef CONFIG_SOC_OMAP2420
-void __init omap242x_map_io(void)
-{
- iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
- iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
-}
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-void __init omap243x_map_io(void)
-{
- iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
- iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
-}
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
void __init omap3_map_io(void)
{
@@ -365,6 +276,8 @@ void __init dra7xx_map_io(void)
omap_barriers_init();
}
#endif
+
+#ifdef CONFIG_ARCH_OMAP3
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
*
@@ -399,7 +312,6 @@ static int __init _omap2_init_reprogram_sdrc(void)
return v;
}
-#ifdef CONFIG_OMAP_HWMOD
static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
{
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
@@ -412,55 +324,11 @@ static void __init __maybe_unused omap_hwmod_init_postsetup(void)
/* Set the default postsetup state for all hwmods */
omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
}
-#else
-static inline void omap_hwmod_init_postsetup(void)
-{
-}
-#endif
-
-#ifdef CONFIG_SOC_OMAP2420
-void __init omap2420_init_early(void)
-{
- omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
- omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
- OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
- omap2_control_base_init();
- omap2xxx_check_revision();
- omap2_prcm_base_init();
- omap2xxx_voltagedomains_init();
- omap242x_powerdomains_init();
- omap242x_clockdomains_init();
- omap2420_hwmod_init();
- omap_hwmod_init_postsetup();
- omap_clk_soc_init = omap2420_dt_clk_init;
- rate_table = omap2420_rate_table;
-}
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-void __init omap2430_init_early(void)
-{
- omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
- omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
- OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
- omap2_control_base_init();
- omap2xxx_check_revision();
- omap2_prcm_base_init();
- omap2xxx_voltagedomains_init();
- omap243x_powerdomains_init();
- omap243x_clockdomains_init();
- omap2430_hwmod_init();
- omap_hwmod_init_postsetup();
- omap_clk_soc_init = omap2430_dt_clk_init;
- rate_table = omap2430_rate_table;
-}
-#endif
/*
* Currently only board-omap3beagle.c should call this because of the
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
*/
-#ifdef CONFIG_ARCH_OMAP3
static void __init omap3_init_early(void)
{
omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
@@ -661,16 +529,18 @@ void __init dra7xx_init_late(void)
#endif
+#ifdef CONFIG_ARCH_OMAP3
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
omap_sram_init();
- if (cpu_is_omap24xx() || omap3_has_sdrc()) {
+ if (omap3_has_sdrc()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
}
+#endif
int __init omap_clk_init(void)
{
diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
index 6191d244438a..403444bb6924 100644
--- a/arch/arm/mach-omap2/iomap.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -48,52 +48,6 @@
#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
-/*
- * ----------------------------------------------------------------------------
- * Omap2 specific IO mapping
- * ----------------------------------------------------------------------------
- */
-
-/* We map both L3 and L4 on OMAP2 */
-#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
-#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
-#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
-#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
-#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
-
-#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
-#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
-#define L4_WK_243X_SIZE SZ_1M
-#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
-#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
- /* 0x6e000000 --> 0xfe000000 */
-#define OMAP243X_GPMC_SIZE SZ_1M
-#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
- /* 0x6D000000 --> 0xfd000000 */
-#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
-#define OMAP243X_SDRC_SIZE SZ_1M
-#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
- /* 0x6c000000 --> 0xfc000000 */
-#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
-#define OMAP243X_SMS_SIZE SZ_1M
-
-/* 2420 IVA */
-#define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE
- /* 0x58000000 --> 0xfc100000 */
-#define DSP_MEM_2420_VIRT 0xfc100000
-#define DSP_MEM_2420_SIZE 0x28000
-#define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE
- /* 0x59000000 --> 0xfc128000 */
-#define DSP_IPI_2420_VIRT 0xfc128000
-#define DSP_IPI_2420_SIZE SZ_4K
-#define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE
- /* 0x5a000000 --> 0xfc129000 */
-#define DSP_MMU_2420_VIRT 0xfc129000
-#define DSP_MMU_2420_SIZE SZ_4K
-
-/* 2430 IVA2.1 - currently unmapped */
-
/*
* ----------------------------------------------------------------------------
* Omap3 specific IO mapping
diff --git a/arch/arm/mach-omap2/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h
deleted file mode 100644
index 6297c62428ac..000000000000
--- a/arch/arm/mach-omap2/l3_2xxx.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
- * Sumit Semwal
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
-
-/* L3 CONNIDs */
-/* Display Sub system (DSS) */
-#define OMAP2_L3_CORE_FW_CONNID_DSS 8
-
-#endif
diff --git a/arch/arm/mach-omap2/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h
deleted file mode 100644
index 418e1072d730..000000000000
--- a/arch/arm/mach-omap2/l4_2xxx.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
- * Sumit Semwal
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
-
-/* L4 CORE */
-/* Display Sub system (DSS) */
-#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28
-#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29
-#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30
-#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31
-#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32
-
-#endif
diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h
deleted file mode 100644
index b5533e93cb63..000000000000
--- a/arch/arm/mach-omap2/mmc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#define OMAP24XX_NR_MMC 2
-#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
-#define OMAP2_MMC1_BASE 0x4809c000
-
-#define OMAP4_MMC_REG_OFFSET 0x100
-
-struct omap_hwmod;
-
-#ifdef CONFIG_SOC_OMAP2420
-int omap_msdi_reset(struct omap_hwmod *oh);
-#else
-static inline int omap_msdi_reset(struct omap_hwmod *oh)
-{
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
deleted file mode 100644
index 552b2fa4e4f1..000000000000
--- a/arch/arm/mach-omap2/msdi.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * MSDI IP block reset
- *
- * Copyright (C) 2012 Texas Instruments, Inc.
- * Paul Walmsley
- *
- * XXX What about pad muxing?
- */
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-
-#include "prm.h"
-#include "common.h"
-#include "control.h"
-#include "omap_hwmod.h"
-#include "omap_device.h"
-#include "mmc.h"
-
-/*
- * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
- * from the IP block's base address
- */
-#define MSDI_CON_OFFSET 0x0c
-
-/* Register bitfields in the CON register */
-#define MSDI_CON_POW_MASK BIT(11)
-#define MSDI_CON_CLKD_MASK (0x3f << 0)
-#define MSDI_CON_CLKD_SHIFT 0
-
-/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
-#define MSDI_TARGET_RESET_CLKD 0x3ff
-
-/**
- * omap_msdi_reset - reset the MSDI IP block
- * @oh: struct omap_hwmod *
- *
- * The MSDI IP block on OMAP2420 has to have both the POW and CLKD
- * fields set inside its CON register for a reset to complete
- * successfully. This is not documented in the TRM. For CLKD, we use
- * the value that results in the lowest possible clock rate, to attempt
- * to avoid disturbing any cards.
- */
-int omap_msdi_reset(struct omap_hwmod *oh)
-{
- u16 v = 0;
- int c = 0;
-
- /* Write to the SOFTRESET bit */
- omap_hwmod_softreset(oh);
-
- /* Enable the MSDI core and internal clock */
- v |= MSDI_CON_POW_MASK;
- v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
- omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
-
- /* Poll on RESETDONE bit */
- omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
- & SYSS_RESETDONE_MASK),
- MAX_MODULE_SOFTRESET_WAIT, c);
-
- if (c == MAX_MODULE_SOFTRESET_WAIT)
- pr_warn("%s: %s: softreset failed (waited %d usec)\n",
- __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
- else
- pr_debug("%s: %s: softreset in %d usec\n", __func__,
- oh->name, c);
-
- /* Disable the MSDI internal clock */
- v &= ~MSDI_CON_CLKD_MASK;
- omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
-
- return 0;
-}
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
deleted file mode 100644
index fdcc75c97d70..000000000000
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * omap2-restart.c - code common to all OMAP2xxx machines.
- *
- * Copyright (C) 2012 Texas Instruments
- * Paul Walmsley
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "common.h"
-#include "prm.h"
-
-/*
- * reset_virt_prcm_set_ck, reset_sys_ck: pointers to the virt_prcm_set
- * clock and the sys_ck. Used during the reset process
- */
-static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
-
-/* Reboot handling */
-
-/**
- * omap2xxx_restart - Set DPLL to bypass mode for reboot to work
- *
- * Set the DPLL to bypass so that reboot completes successfully. No
- * return value.
- */
-void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
-{
- u32 rate;
-
- rate = clk_get_rate(reset_sys_ck);
- clk_set_rate(reset_virt_prcm_set_ck, rate);
-
- /* XXX Should save the cmd argument for use after the reboot */
-
- omap_prm_reset_system();
-}
-
-/**
- * omap2xxx_common_look_up_clks_for_reset - look up clocks needed for restart
- *
- * Some clocks need to be looked up in advance for the SoC restart
- * operation to work - see omap2xxx_restart(). Returns -EINVAL upon
- * error or 0 upon success.
- */
-static int __init omap2xxx_common_look_up_clks_for_reset(void)
-{
- reset_virt_prcm_set_ck = clk_get(NULL, "virt_prcm_set");
- if (IS_ERR(reset_virt_prcm_set_ck))
- return -EINVAL;
-
- reset_sys_ck = clk_get(NULL, "sys_ck");
- if (IS_ERR(reset_sys_ck))
- return -EINVAL;
-
- return 0;
-}
-omap_postcore_initcall(omap2xxx_common_look_up_clks_for_reset);
diff --git a/arch/arm/mach-omap2/omap24xx.h b/arch/arm/mach-omap2/omap24xx.h
deleted file mode 100644
index d9ecc0578292..000000000000
--- a/arch/arm/mach-omap2/omap24xx.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * This file contains the processor specific definitions
- * of the TI OMAP24XX.
- *
- * Copyright (C) 2007 Texas Instruments.
- * Copyright (C) 2007 Nokia Corporation.
- */
-
-#ifndef __ASM_ARCH_OMAP2_H
-#define __ASM_ARCH_OMAP2_H
-
-/*
- * Please place only base defines here and put the rest in device
- * specific headers. Note also that some of these defines are needed
- * for omap1 to compile without adding ifdefs.
- */
-
-#define L4_24XX_BASE 0x48000000
-#define L4_WK_243X_BASE 0x49000000
-#define L3_24XX_BASE 0x68000000
-
-/* interrupt controller */
-#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
-#define OMAP24XX_IVA_INTC_BASE 0x40000000
-
-#define OMAP242X_CTRL_BASE L4_24XX_BASE
-#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
-#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
-#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
-#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
-#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
-#define OMAP2420_SMS_BASE 0x68008000
-#define OMAP2420_GPMC_BASE 0x6800a000
-
-#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
-#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
-#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
-#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
-
-#define OMAP243X_SMS_BASE 0x6C000000
-#define OMAP243X_SDRC_BASE 0x6D000000
-#define OMAP243X_GPMC_BASE 0x6E000000
-#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
-#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
-#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
-
-/* DSP SS */
-#define OMAP2420_DSP_BASE 0x58000000
-#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
-#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
-#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
-
-#define OMAP243X_DSP_BASE 0x5C000000
-#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
-#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
-
-/* Mailbox */
-#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
-
-/* Camera */
-#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
-
-/* Security */
-#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
-#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
-#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
-#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
-#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
-#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
-
-#endif /* __ASM_ARCH_OMAP2_H */
-
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 03cd523dff87..cde357acf038 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -153,9 +153,7 @@
#include "common.h"
#include "clockdomain.h"
#include "hdq1w.h"
-#include "mmc.h"
#include "powerdomain.h"
-#include "cm2xxx.h"
#include "cm3xxx.h"
#include "cm33xx.h"
#include "prm.h"
@@ -3437,7 +3435,7 @@ static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
/*
* Note that we assume interconnect interface clocks will be
* managed by the interconnect driver for OCPIF_SWSUP_IDLE case
- * on omap24xx and omap3.
+ * on omap3.
*/
oi->slave = oh;
oi->user = OCP_USER_MPU | OCP_USER_SDMA;
@@ -3469,10 +3467,6 @@ static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
return -ENOMEM;
}
-static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
- { .match = "msdi", .len = 4, .reset = omap_msdi_reset, },
-};
-
static const struct omap_hwmod_reset omap_reset_quirks[] = {
{ .match = "dss_core", .len = 8, .reset = omap_dss_reset, },
{ .match = "hdq1w", .len = 5, .reset = omap_hdq1w_reset, },
@@ -3503,11 +3497,6 @@ static void
omap_hwmod_init_reset_quirks(struct device *dev, struct omap_hwmod *oh,
const struct ti_sysc_module_data *data)
{
- if (soc_is_omap24xx())
- omap_hwmod_init_reset_quirk(dev, oh, data,
- omap24xx_reset_quirks,
- ARRAY_SIZE(omap24xx_reset_quirks));
-
omap_hwmod_init_reset_quirk(dev, oh, data, omap_reset_quirks,
ARRAY_SIZE(omap_reset_quirks));
}
@@ -3914,12 +3903,7 @@ int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
*/
void __init omap_hwmod_init(void)
{
- if (cpu_is_omap24xx()) {
- soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
- soc_ops.assert_hardreset = _omap2_assert_hardreset;
- soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
- soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
- } else if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx()) {
soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index dcab7a01c10e..b60cd09c1997 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -663,8 +663,6 @@ omap_hwmod_for_each_by_class(const char *classname,
* Chip variant-specific hwmod init routines - XXX should be converted
* to use initcalls once the initial boot ordering is straightened out
*/
-extern int omap2420_hwmod_init(void);
-extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int dm814x_hwmod_init(void);
extern int dm816x_hwmod_init(void);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
deleted file mode 100644
index dbd9dc9f0962..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ /dev/null
@@ -1,402 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
- *
- * Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2012 Texas Instruments, Inc.
- * Paul Walmsley
- *
- * XXX handle crossbar/shared link difference for L3?
- * XXX these should be marked initdata for multi-OMAP kernels
- */
-
-#include <linux/platform_data/i2c-omap.h>
-
-#include "omap_hwmod.h"
-#include "l3_2xxx.h"
-#include "l4_2xxx.h"
-
-#include "omap_hwmod_common_data.h"
-
-#include "cm-regbits-24xx.h"
-#include "prm-regbits-24xx.h"
-#include "i2c.h"
-#include "mmc.h"
-#include "wd_timer.h"
-
-/*
- * OMAP2420 hardware module integration data
- *
- * All of the data in this section should be autogeneratable from the
- * TI hardware database or other technical documentation. Data that
- * is driver-specific or driver-kernel integration-specific belongs
- * elsewhere.
- */
-
-/*
- * IP blocks
- */
-
-/* IVA1 (IVA1) */
-static struct omap_hwmod_class iva1_hwmod_class = {
- .name = "iva1",
-};
-
-static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
- { .name = "iva", .rst_shift = 8 },
-};
-
-static struct omap_hwmod omap2420_iva_hwmod = {
- .name = "iva",
- .class = &iva1_hwmod_class,
- .clkdm_name = "iva1_clkdm",
- .rst_lines = omap2420_iva_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
- .main_clk = "iva1_ifck",
-};
-
-/* DSP */
-static struct omap_hwmod_class dsp_hwmod_class = {
- .name = "dsp",
-};
-
-static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
- { .name = "logic", .rst_shift = 0 },
- { .name = "mmu", .rst_shift = 1 },
-};
-
-static struct omap_hwmod omap2420_dsp_hwmod = {
- .name = "dsp",
- .class = &dsp_hwmod_class,
- .clkdm_name = "dsp_clkdm",
- .rst_lines = omap2420_dsp_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
- .main_clk = "dsp_fck",
-};
-
-/* I2C common */
-static struct omap_hwmod_class_sysconfig i2c_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x20,
- .syss_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class i2c_class = {
- .name = "i2c",
- .sysc = &i2c_sysc,
- .reset = &omap_i2c_reset,
-};
-
-/* I2C1 */
-static struct omap_hwmod omap2420_i2c1_hwmod = {
- .name = "i2c1",
- .main_clk = "i2c1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
- },
- },
- .class = &i2c_class,
- /*
- * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
- * while a transfer is active seems to cause the I2C block to
- * timeout. Why? Good question."
- */
- .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
-};
-
-/* I2C2 */
-static struct omap_hwmod omap2420_i2c2_hwmod = {
- .name = "i2c2",
- .main_clk = "i2c2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
- },
- },
- .class = &i2c_class,
- .flags = HWMOD_16BIT_REG,
-};
-
-/* mailbox */
-static struct omap_hwmod omap2420_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap2xxx_mailbox_hwmod_class,
- .main_clk = "mailboxes_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
- },
- },
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
- .name = "mcbsp",
-};
-
-static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
- { .role = "pad_fck", .clk = "mcbsp_clks" },
- { .role = "prcm_fck", .clk = "func_96m_ck" },
-};
-
-/* mcbsp1 */
-static struct omap_hwmod omap2420_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap2420_mcbsp_hwmod_class,
- .main_clk = "mcbsp1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* mcbsp2 */
-static struct omap_hwmod omap2420_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap2420_mcbsp_hwmod_class,
- .main_clk = "mcbsp2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
- .rev_offs = 0x3c,
- .sysc_offs = 0x64,
- .syss_offs = 0x68,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
- .name = "msdi",
- .sysc = &omap2420_msdi_sysc,
- .reset = &omap_msdi_reset,
-};
-
-/* msdi1 */
-static struct omap_hwmod omap2420_msdi1_hwmod = {
- .name = "msdi1",
- .class = &omap2420_msdi_hwmod_class,
- .main_clk = "mmc_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
- },
- },
- .flags = HWMOD_16BIT_REG,
-};
-
-/* HDQ1W/1-wire */
-static struct omap_hwmod omap2420_hdq1w_hwmod = {
- .name = "hdq1w",
- .main_clk = "hdq_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
- },
- },
- .class = &omap2_hdq1w_class,
-};
-
-/*
- * interfaces
- */
-
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_i2c1_hwmod,
- .clk = "i2c1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_i2c2_hwmod,
- .clk = "i2c2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* IVA <- L3 interface */
-static struct omap_hwmod_ocp_if omap2420_l3__iva = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2420_iva_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* DSP <- L3 interface */
-static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2420_dsp_hwmod,
- .clk = "dsp_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_wd_timer2_hwmod,
- .clk = "mpu_wdt_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio1_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio2 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio2_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio3 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio3_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio4 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio4_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mailbox */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_mailbox_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_mcbsp1_hwmod,
- .clk = "mcbsp1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_mcbsp2_hwmod,
- .clk = "mcbsp2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> msdi1 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_msdi1_hwmod,
- .clk = "mmc_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> hdq1w interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_hdq1w_hwmod,
- .clk = "hdq_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
- .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
-};
-
-static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2xxx_gpmc_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
- &omap2xxx_l3_main__l4_core,
- &omap2xxx_mpu__l3_main,
- &omap2xxx_dss__l3,
- &omap2xxx_l4_core__mcspi1,
- &omap2xxx_l4_core__mcspi2,
- &omap2xxx_l4_core__l4_wkup,
- &omap2_l4_core__uart1,
- &omap2_l4_core__uart2,
- &omap2_l4_core__uart3,
- &omap2420_l4_core__i2c1,
- &omap2420_l4_core__i2c2,
- &omap2420_l3__iva,
- &omap2420_l3__dsp,
- &omap2xxx_l4_core__timer3,
- &omap2xxx_l4_core__timer4,
- &omap2xxx_l4_core__timer5,
- &omap2xxx_l4_core__timer6,
- &omap2xxx_l4_core__timer7,
- &omap2xxx_l4_core__timer8,
- &omap2xxx_l4_core__timer9,
- &omap2xxx_l4_core__timer10,
- &omap2xxx_l4_core__timer11,
- &omap2xxx_l4_core__timer12,
- &omap2420_l4_wkup__wd_timer2,
- &omap2xxx_l4_core__dss,
- &omap2xxx_l4_core__dss_dispc,
- &omap2xxx_l4_core__dss_rfbi,
- &omap2xxx_l4_core__dss_venc,
- &omap2420_l4_wkup__gpio1,
- &omap2420_l4_wkup__gpio2,
- &omap2420_l4_wkup__gpio3,
- &omap2420_l4_wkup__gpio4,
- &omap2420_l4_core__mailbox,
- &omap2420_l4_core__mcbsp1,
- &omap2420_l4_core__mcbsp2,
- &omap2420_l4_core__msdi1,
- &omap2xxx_l4_core__rng,
- &omap2xxx_l4_core__sham,
- &omap2xxx_l4_core__aes,
- &omap2420_l4_core__hdq1w,
- &omap2420_l3__gpmc,
- NULL,
-};
-
-int __init omap2420_hwmod_init(void)
-{
- omap_hwmod_init();
- return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
-}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
deleted file mode 100644
index c93200801b34..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ /dev/null
@@ -1,606 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
- *
- * Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2012 Texas Instruments, Inc.
- * Paul Walmsley
- *
- * XXX handle crossbar/shared link difference for L3?
- * XXX these should be marked initdata for multi-OMAP kernels
- */
-
-#include <linux/platform_data/i2c-omap.h>
-#include <linux/platform_data/hsmmc-omap.h>
-
-#include "omap_hwmod.h"
-#include "l3_2xxx.h"
-
-#include "soc.h"
-#include "omap_hwmod_common_data.h"
-#include "prm-regbits-24xx.h"
-#include "cm-regbits-24xx.h"
-#include "i2c.h"
-#include "wd_timer.h"
-
-/*
- * OMAP2430 hardware module integration data
- *
- * All of the data in this section should be autogeneratable from the
- * TI hardware database or other technical documentation. Data that
- * is driver-specific or driver-kernel integration-specific belongs
- * elsewhere.
- */
-
-/*
- * IP blocks
- */
-
-/* IVA2 (IVA2) */
-static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
- { .name = "logic", .rst_shift = 0 },
- { .name = "mmu", .rst_shift = 1 },
-};
-
-static struct omap_hwmod omap2430_iva_hwmod = {
- .name = "iva",
- .class = &iva_hwmod_class,
- .clkdm_name = "dsp_clkdm",
- .rst_lines = omap2430_iva_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
- .main_clk = "dsp_fck",
-};
-
-/* I2C common */
-static struct omap_hwmod_class_sysconfig i2c_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x20,
- .syss_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class i2c_class = {
- .name = "i2c",
- .sysc = &i2c_sysc,
- .reset = &omap_i2c_reset,
-};
-
-/* I2C1 */
-static struct omap_hwmod omap2430_i2c1_hwmod = {
- .name = "i2c1",
- .flags = HWMOD_16BIT_REG,
- .main_clk = "i2chs1_fck",
- .prcm = {
- .omap2 = {
- /*
- * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
- * I2CHS IP's do not follow the usual pattern.
- * prcm_reg_id alone cannot be used to program
- * the iclk and fclk. Needs to be handled using
- * additional flags when clk handling is moved
- * to hwmod framework.
- */
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
- },
- },
- .class = &i2c_class,
-};
-
-/* I2C2 */
-static struct omap_hwmod omap2430_i2c2_hwmod = {
- .name = "i2c2",
- .flags = HWMOD_16BIT_REG,
- .main_clk = "i2chs2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
- },
- },
- .class = &i2c_class,
-};
-
-/* gpio5 */
-static struct omap_hwmod omap2430_gpio5_hwmod = {
- .name = "gpio5",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "gpio5_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
- },
- },
- .class = &omap2xxx_gpio_hwmod_class,
-};
-
-/* mailbox */
-static struct omap_hwmod omap2430_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap2xxx_mailbox_hwmod_class,
- .main_clk = "mailboxes_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
- },
- },
-};
-
-/* mcspi3 */
-static struct omap_hwmod omap2430_mcspi3_hwmod = {
- .name = "mcspi3",
- .main_clk = "mcspi3_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
- },
- },
- .class = &omap2xxx_mcspi_class,
-};
-
-/* usbhsotg */
-static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
- .rev_offs = 0x0400,
- .sysc_offs = 0x0404,
- .syss_offs = 0x0408,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class usbotg_class = {
- .name = "usbotg",
- .sysc = &omap2430_usbhsotg_sysc,
-};
-
-/* usb_otg_hs */
-static struct omap_hwmod omap2430_usbhsotg_hwmod = {
- .name = "usb_otg_hs",
- .main_clk = "usbhs_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
- },
- },
- .class = &usbotg_class,
- /*
- * Erratum ID: i479 idle_req / idle_ack mechanism potentially
- * broken when autoidle is enabled
- * workaround is to disable the autoidle bit at module level.
- */
- .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
- | HWMOD_SWSUP_MSTANDBY,
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
- .rev_offs = 0x007C,
- .sysc_offs = 0x008C,
- .sysc_flags = (SYSC_HAS_SOFTRESET),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
- .name = "mcbsp",
- .sysc = &omap2430_mcbsp_sysc,
-};
-
-static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
- { .role = "pad_fck", .clk = "mcbsp_clks" },
- { .role = "prcm_fck", .clk = "func_96m_ck" },
-};
-
-/* mcbsp1 */
-static struct omap_hwmod omap2430_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap2430_mcbsp_hwmod_class,
- .main_clk = "mcbsp1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* mcbsp2 */
-static struct omap_hwmod omap2430_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap2430_mcbsp_hwmod_class,
- .main_clk = "mcbsp2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* mcbsp3 */
-static struct omap_hwmod omap2430_mcbsp3_hwmod = {
- .name = "mcbsp3",
- .class = &omap2430_mcbsp_hwmod_class,
- .main_clk = "mcbsp3_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* mcbsp4 */
-static struct omap_hwmod omap2430_mcbsp4_hwmod = {
- .name = "mcbsp4",
- .class = &omap2430_mcbsp_hwmod_class,
- .main_clk = "mcbsp4_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* mcbsp5 */
-static struct omap_hwmod omap2430_mcbsp5_hwmod = {
- .name = "mcbsp5",
- .class = &omap2430_mcbsp_hwmod_class,
- .main_clk = "mcbsp5_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
- },
- },
- .opt_clks = mcbsp_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
-};
-
-/* MMC/SD/SDIO common */
-static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
- .rev_offs = 0x1fc,
- .sysc_offs = 0x10,
- .syss_offs = 0x14,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_mmc_class = {
- .name = "mmc",
- .sysc = &omap2430_mmc_sysc,
-};
-
-/* MMC/SD/SDIO1 */
-static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
- { .role = "dbck", .clk = "mmchsdb1_fck" },
-};
-
-static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
- .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-
-static struct omap_hwmod omap2430_mmc1_hwmod = {
- .name = "mmc1",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .opt_clks = omap2430_mmc1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
- .main_clk = "mmchs1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
- },
- },
- .dev_attr = &mmc1_dev_attr,
- .class = &omap2430_mmc_class,
-};
-
-/* MMC/SD/SDIO2 */
-static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
- { .role = "dbck", .clk = "mmchsdb2_fck" },
-};
-
-static struct omap_hwmod omap2430_mmc2_hwmod = {
- .name = "mmc2",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .opt_clks = omap2430_mmc2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
- .main_clk = "mmchs2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
- },
- },
- .class = &omap2430_mmc_class,
-};
-
-/* HDQ1W/1-wire */
-static struct omap_hwmod omap2430_hdq1w_hwmod = {
- .name = "hdq1w",
- .main_clk = "hdq_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
- },
- },
- .class = &omap2_hdq1w_class,
-};
-
-/*
- * interfaces
- */
-
-/* L3 -> L4_CORE interface */
-/* l3_core -> usbhsotg interface */
-static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
- .master = &omap2430_usbhsotg_hwmod,
- .slave = &omap2xxx_l3_main_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU,
-};
-
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_i2c1_hwmod,
- .clk = "i2c1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_i2c2_hwmod,
- .clk = "i2c2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core ->usbhsotg interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_usbhsotg_hwmod,
- .clk = "usb_l4_ick",
- .user = OCP_USER_MPU,
-};
-
-/* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mmc1_hwmod,
- .clk = "mmchs1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mmc2_hwmod,
- .clk = "mmchs2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi3 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcspi3_hwmod,
- .clk = "mcspi3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* IVA2 <- L3 interface */
-static struct omap_hwmod_ocp_if omap2430_l3__iva = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2430_iva_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_wd_timer2_hwmod,
- .clk = "mpu_wdt_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio1_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio2 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio2_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio3 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio3_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio4 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_gpio4_hwmod,
- .clk = "gpios_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> gpio5 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_gpio5_hwmod,
- .clk = "gpio5_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mailbox */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mailbox_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcbsp1_hwmod,
- .clk = "mcbsp1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcbsp2_hwmod,
- .clk = "mcbsp2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcbsp3_hwmod,
- .clk = "mcbsp3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcbsp4_hwmod,
- .clk = "mcbsp4_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> mcbsp5 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_mcbsp5_hwmod,
- .clk = "mcbsp5_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> hdq1w */
-static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_hdq1w_hwmod,
- .clk = "hdq_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
- .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
-};
-
-static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2xxx_gpmc_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
- &omap2xxx_l3_main__l4_core,
- &omap2xxx_mpu__l3_main,
- &omap2xxx_dss__l3,
- &omap2430_usbhsotg__l3,
- &omap2430_l4_core__i2c1,
- &omap2430_l4_core__i2c2,
- &omap2xxx_l4_core__l4_wkup,
- &omap2_l4_core__uart1,
- &omap2_l4_core__uart2,
- &omap2_l4_core__uart3,
- &omap2430_l4_core__usbhsotg,
- &omap2430_l4_core__mmc1,
- &omap2430_l4_core__mmc2,
- &omap2xxx_l4_core__mcspi1,
- &omap2xxx_l4_core__mcspi2,
- &omap2430_l4_core__mcspi3,
- &omap2430_l3__iva,
- &omap2xxx_l4_core__timer3,
- &omap2xxx_l4_core__timer4,
- &omap2xxx_l4_core__timer5,
- &omap2xxx_l4_core__timer6,
- &omap2xxx_l4_core__timer7,
- &omap2xxx_l4_core__timer8,
- &omap2xxx_l4_core__timer9,
- &omap2xxx_l4_core__timer10,
- &omap2xxx_l4_core__timer11,
- &omap2xxx_l4_core__timer12,
- &omap2430_l4_wkup__wd_timer2,
- &omap2xxx_l4_core__dss,
- &omap2xxx_l4_core__dss_dispc,
- &omap2xxx_l4_core__dss_rfbi,
- &omap2xxx_l4_core__dss_venc,
- &omap2430_l4_wkup__gpio1,
- &omap2430_l4_wkup__gpio2,
- &omap2430_l4_wkup__gpio3,
- &omap2430_l4_wkup__gpio4,
- &omap2430_l4_core__gpio5,
- &omap2430_l4_core__mailbox,
- &omap2430_l4_core__mcbsp1,
- &omap2430_l4_core__mcbsp2,
- &omap2430_l4_core__mcbsp3,
- &omap2430_l4_core__mcbsp4,
- &omap2430_l4_core__mcbsp5,
- &omap2430_l4_core__hdq1w,
- &omap2xxx_l4_core__rng,
- &omap2xxx_l4_core__sham,
- &omap2xxx_l4_core__aes,
- &omap2430_l3__gpmc,
- NULL,
-};
-
-int __init omap2430_hwmod_init(void)
-{
- omap_hwmod_init();
- return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
-}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
deleted file mode 100644
index 761d34914ed9..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ /dev/null
@@ -1,256 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
- *
- * Copyright (C) 2009-2011 Nokia Corporation
- * Paul Walmsley
- *
- * XXX handle crossbar/shared link difference for L3?
- * XXX these should be marked initdata for multi-OMAP kernels
- */
-#include <linux/sizes.h>
-
-#include "omap_hwmod.h"
-#include "l3_2xxx.h"
-#include "l4_2xxx.h"
-
-#include "omap_hwmod_common_data.h"
-
-/*
- * Common interconnect data
- */
-
-/* L3 -> L4_CORE interface */
-struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
- .master = &omap2xxx_l3_main_hwmod,
- .slave = &omap2xxx_l4_core_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* MPU -> L3 interface */
-struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
- .master = &omap2xxx_mpu_hwmod,
- .slave = &omap2xxx_l3_main_hwmod,
- .user = OCP_USER_MPU,
-};
-
-/* DSS -> l3 */
-struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
- .master = &omap2xxx_dss_core_hwmod,
- .slave = &omap2xxx_l3_main_hwmod,
- .fw = {
- .omap2 = {
- .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
- .flags = OMAP_FIREWALL_L3,
- },
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4_CORE -> L4_WKUP interface */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_l4_wkup_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART1 interface */
-struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_uart1_hwmod,
- .clk = "uart1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART2 interface */
-struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_uart2_hwmod,
- .clk = "uart2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 PER -> UART3 interface */
-struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_uart3_hwmod,
- .clk = "uart3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi1 interface */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_mcspi1_hwmod,
- .clk = "mcspi1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi2 interface */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_mcspi2_hwmod,
- .clk = "mcspi2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer3 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer3_hwmod,
- .clk = "gpt3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer4 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer4_hwmod,
- .clk = "gpt4_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer5 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer5_hwmod,
- .clk = "gpt5_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer6 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer6_hwmod,
- .clk = "gpt6_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer7 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer7_hwmod,
- .clk = "gpt7_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer8 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer8_hwmod,
- .clk = "gpt8_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer9 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer9_hwmod,
- .clk = "gpt9_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer10 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer10_hwmod,
- .clk = "gpt10_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer11 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer11_hwmod,
- .clk = "gpt11_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer12 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer12_hwmod,
- .clk = "gpt12_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_dss_core_hwmod,
- .clk = "dss_ick",
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
- .flags = OMAP_FIREWALL_L4,
- },
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_dispc */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_dss_dispc_hwmod,
- .clk = "dss_ick",
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
- .flags = OMAP_FIREWALL_L4,
- },
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_rfbi */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_dss_rfbi_hwmod,
- .clk = "dss_ick",
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
- .flags = OMAP_FIREWALL_L4,
- },
- },
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_venc */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_dss_venc_hwmod,
- .clk = "dss_ick",
- .fw = {
- .omap2 = {
- .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
- .flags = OMAP_FIREWALL_L4,
- },
- },
- .flags = OCPIF_SWSUP_IDLE,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> rng */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_rng_hwmod,
- .clk = "rng_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> sham interface */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_sham_hwmod,
- .clk = "sha_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> aes interface */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_aes_hwmod,
- .clk = "aes_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
deleted file mode 100644
index 4982e04ead53..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ /dev/null
@@ -1,668 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
- *
- * Copyright (C) 2011 Nokia Corporation
- * Paul Walmsley
- */
-
-#include <linux/types.h>
-
-#include "omap_hwmod.h"
-#include "omap_hwmod_common_data.h"
-#include "cm-regbits-24xx.h"
-#include "prm-regbits-24xx.h"
-#include "wd_timer.h"
-
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap2_dispc_sysc,
-};
-
-/* OMAP2xxx Timer Common */
-static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &omap2xxx_timer_sysc,
-};
-
-/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
- */
-
-static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &omap2xxx_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable,
- .reset = &omap2_wd_timer_reset,
-};
-
-/*
- * 'gpio' class
- * general purpose io module
- */
-static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
- .name = "gpio",
- .sysc = &omap2xxx_gpio_sysc,
-};
-
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors
- * using a queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
- .rev_offs = 0x000,
- .sysc_offs = 0x010,
- .syss_offs = 0x014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &omap2xxx_mailbox_sysc,
-};
-
-/*
- * 'mcspi' class
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
- * bus
- */
-
-static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2xxx_mcspi_class = {
- .name = "mcspi",
- .sysc = &omap2xxx_mcspi_sysc,
-};
-
-/*
- * 'gpmc' class
- * general purpose memory controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
- .name = "gpmc",
- .sysc = &omap2xxx_gpmc_sysc,
-};
-
-/*
- * IP blocks
- */
-
-/* L3 */
-struct omap_hwmod omap2xxx_l3_main_hwmod = {
- .name = "l3_main",
- .class = &l3_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* L4 CORE */
-struct omap_hwmod omap2xxx_l4_core_hwmod = {
- .name = "l4_core",
- .class = &l4_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* L4 WKUP */
-struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
- .name = "l4_wkup",
- .class = &l4_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* MPU */
-struct omap_hwmod omap2xxx_mpu_hwmod = {
- .name = "mpu",
- .class = &mpu_hwmod_class,
- .main_clk = "mpu_ck",
-};
-
-/* timer3 */
-struct omap_hwmod omap2xxx_timer3_hwmod = {
- .name = "timer3",
- .main_clk = "gpt3_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer4 */
-struct omap_hwmod omap2xxx_timer4_hwmod = {
- .name = "timer4",
- .main_clk = "gpt4_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer5 */
-struct omap_hwmod omap2xxx_timer5_hwmod = {
- .name = "timer5",
- .main_clk = "gpt5_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer6 */
-struct omap_hwmod omap2xxx_timer6_hwmod = {
- .name = "timer6",
- .main_clk = "gpt6_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer7 */
-struct omap_hwmod omap2xxx_timer7_hwmod = {
- .name = "timer7",
- .main_clk = "gpt7_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer8 */
-struct omap_hwmod omap2xxx_timer8_hwmod = {
- .name = "timer8",
- .main_clk = "gpt8_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer9 */
-struct omap_hwmod omap2xxx_timer9_hwmod = {
- .name = "timer9",
- .main_clk = "gpt9_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer10 */
-struct omap_hwmod omap2xxx_timer10_hwmod = {
- .name = "timer10",
- .main_clk = "gpt10_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer11 */
-struct omap_hwmod omap2xxx_timer11_hwmod = {
- .name = "timer11",
- .main_clk = "gpt11_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer12 */
-struct omap_hwmod omap2xxx_timer12_hwmod = {
- .name = "timer12",
- .main_clk = "gpt12_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* wd_timer2 */
-struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
- .name = "wd_timer2",
- .class = &omap2xxx_wd_timer_hwmod_class,
- .main_clk = "mpu_wdt_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
- },
- },
-};
-
-/* UART1 */
-
-struct omap_hwmod omap2xxx_uart1_hwmod = {
- .name = "uart1",
- .main_clk = "uart1_fck",
- .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
- },
- },
- .class = &omap2_uart_class,
-};
-
-/* UART2 */
-
-struct omap_hwmod omap2xxx_uart2_hwmod = {
- .name = "uart2",
- .main_clk = "uart2_fck",
- .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
- },
- },
- .class = &omap2_uart_class,
-};
-
-/* UART3 */
-
-struct omap_hwmod omap2xxx_uart3_hwmod = {
- .name = "uart3",
- .main_clk = "uart3_fck",
- .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 2,
- .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
- },
- },
- .class = &omap2_uart_class,
-};
-
-/* dss */
-
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- /*
- * The DSS HW needs all DSS clocks enabled during reset. The dss_core
- * driver does not use these clocks.
- */
- { .role = "tv_clk", .clk = "dss_54m_fck" },
- { .role = "sys_clk", .clk = "dss2_fck" },
-};
-
-struct omap_hwmod omap2xxx_dss_core_hwmod = {
- .name = "dss_core",
- .class = &omap2_dss_hwmod_class,
- .main_clk = "dss1_fck", /* instead of dss_fck */
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- },
- },
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
- .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-};
-
-struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &omap2_dispc_hwmod_class,
- .main_clk = "dss1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- },
- },
- .flags = HWMOD_NO_IDLEST,
- .dev_attr = &omap2_3_dss_dispc_dev_attr,
-};
-
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
- { .role = "ick", .clk = "dss_ick" },
-};
-
-struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap2_rfbi_hwmod_class,
- .main_clk = "dss1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- },
- },
- .opt_clks = dss_rfbi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
- .flags = HWMOD_NO_IDLEST,
-};
-
-struct omap_hwmod omap2xxx_dss_venc_hwmod = {
- .name = "dss_venc",
- .class = &omap2_venc_hwmod_class,
- .main_clk = "dss_54m_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- },
- },
- .flags = HWMOD_NO_IDLEST,
-};
-
-/* gpio1 */
-struct omap_hwmod omap2xxx_gpio1_hwmod = {
- .name = "gpio1",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .class = &omap2xxx_gpio_hwmod_class,
-};
-
-/* gpio2 */
-struct omap_hwmod omap2xxx_gpio2_hwmod = {
- .name = "gpio2",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .class = &omap2xxx_gpio_hwmod_class,
-};
-
-/* gpio3 */
-struct omap_hwmod omap2xxx_gpio3_hwmod = {
- .name = "gpio3",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .class = &omap2xxx_gpio_hwmod_class,
-};
-
-/* gpio4 */
-struct omap_hwmod omap2xxx_gpio4_hwmod = {
- .name = "gpio4",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "gpios_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
- },
- },
- .class = &omap2xxx_gpio_hwmod_class,
-};
-
-/* mcspi1 */
-struct omap_hwmod omap2xxx_mcspi1_hwmod = {
- .name = "mcspi1",
- .main_clk = "mcspi1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
- },
- },
- .class = &omap2xxx_mcspi_class,
-};
-
-/* mcspi2 */
-struct omap_hwmod omap2xxx_mcspi2_hwmod = {
- .name = "mcspi2",
- .main_clk = "mcspi2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
- },
- },
- .class = &omap2xxx_mcspi_class,
-};
-
-/* gpmc */
-struct omap_hwmod omap2xxx_gpmc_hwmod = {
- .name = "gpmc",
- .class = &omap2xxx_gpmc_hwmod_class,
- .main_clk = "gpmc_fck",
- /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
- .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- },
- },
-};
-
-/* RNG */
-
-static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
- .rev_offs = 0x3c,
- .sysc_offs = 0x40,
- .syss_offs = 0x44,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2_rng_hwmod_class = {
- .name = "rng",
- .sysc = &omap2_rng_sysc,
-};
-
-struct omap_hwmod omap2xxx_rng_hwmod = {
- .name = "rng",
- .main_clk = "l4_ck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 4,
- .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
- },
- },
- /*
- * XXX The first read from the SYSSTATUS register of the RNG
- * after the SYSCONFIG SOFTRESET bit is set triggers an
- * imprecise external abort. It's unclear why this happens.
- * Until this is analyzed, skip the IP block reset.
- */
- .flags = HWMOD_INIT_NO_RESET,
- .class = &omap2_rng_hwmod_class,
-};
-
-/* SHAM */
-
-static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
- .rev_offs = 0x5c,
- .sysc_offs = 0x60,
- .syss_offs = 0x64,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2xxx_sham_class = {
- .name = "sham",
- .sysc = &omap2_sham_sysc,
-};
-
-struct omap_hwmod omap2xxx_sham_hwmod = {
- .name = "sham",
- .main_clk = "l4_ck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 4,
- .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
- },
- },
- .class = &omap2xxx_sham_class,
-};
-
-/* AES */
-
-static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
- .rev_offs = 0x44,
- .sysc_offs = 0x48,
- .syss_offs = 0x4c,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2xxx_aes_class = {
- .name = "aes",
- .sysc = &omap2_aes_sysc,
-};
-
-struct omap_hwmod omap2xxx_aes_hwmod = {
- .name = "aes",
- .main_clk = "l4_ck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 4,
- .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
- },
- },
- .class = &omap2xxx_aes_class,
-};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 69dddc53e1d8..8b270cb3f64b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -15,68 +15,6 @@
#include "common.h"
#include "display.h"
-/* Common IP block data across OMAP2xxx */
-extern struct omap_hwmod omap2xxx_l3_main_hwmod;
-extern struct omap_hwmod omap2xxx_l4_core_hwmod;
-extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
-extern struct omap_hwmod omap2xxx_mpu_hwmod;
-extern struct omap_hwmod omap2xxx_timer3_hwmod;
-extern struct omap_hwmod omap2xxx_timer4_hwmod;
-extern struct omap_hwmod omap2xxx_timer5_hwmod;
-extern struct omap_hwmod omap2xxx_timer6_hwmod;
-extern struct omap_hwmod omap2xxx_timer7_hwmod;
-extern struct omap_hwmod omap2xxx_timer8_hwmod;
-extern struct omap_hwmod omap2xxx_timer9_hwmod;
-extern struct omap_hwmod omap2xxx_timer10_hwmod;
-extern struct omap_hwmod omap2xxx_timer11_hwmod;
-extern struct omap_hwmod omap2xxx_timer12_hwmod;
-extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
-extern struct omap_hwmod omap2xxx_uart1_hwmod;
-extern struct omap_hwmod omap2xxx_uart2_hwmod;
-extern struct omap_hwmod omap2xxx_uart3_hwmod;
-extern struct omap_hwmod omap2xxx_dss_core_hwmod;
-extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
-extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
-extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
-extern struct omap_hwmod omap2xxx_gpio1_hwmod;
-extern struct omap_hwmod omap2xxx_gpio2_hwmod;
-extern struct omap_hwmod omap2xxx_gpio3_hwmod;
-extern struct omap_hwmod omap2xxx_gpio4_hwmod;
-extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
-extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
-extern struct omap_hwmod omap2xxx_gpmc_hwmod;
-extern struct omap_hwmod omap2xxx_rng_hwmod;
-extern struct omap_hwmod omap2xxx_sham_hwmod;
-extern struct omap_hwmod omap2xxx_aes_hwmod;
-
-/* Common interface data across OMAP2xxx */
-extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
-extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
-extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
-extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
-extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
-extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes;
-
/* OMAP hwmod classes - forward declarations */
extern struct omap_hwmod_class l3_hwmod_class;
extern struct omap_hwmod_class l4_hwmod_class;
@@ -88,10 +26,6 @@ extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
extern struct omap_hwmod_class omap2_venc_hwmod_class;
extern struct omap_hwmod_class omap2_hdq1w_class;
-extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
-extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
-extern struct omap_hwmod_class omap2xxx_mcspi_class;
-
extern struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr;
#endif
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
deleted file mode 100644
index 18a448f938ea..000000000000
--- a/arch/arm/mach-omap2/opp2420_data.c
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * opp2420_data.c - old-style "OPP" table for OMAP2420
- *
- * Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2009 Nokia Corporation
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratios' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio.
- *
- * XXX Missing voltage data.
- * XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
- *
- * THe format described in this file is deprecated. Once a reasonable
- * OPP API exists, the data in this file should be converted to use it.
- *
- * This is technically part of the OMAP2xxx clock code.
- *
- * Considerable work is still needed to fully support dynamic frequency
- * changes on OMAP2xxx-series chips. Readers interested in such a
- * project are encouraged to review the Maemo Diablo RX-34 and RX-44
- * kernel source at:
- * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
- */
-
-#include <linux/kernel.h>
-
-#include "opp2xxx.h"
-#include "sdrc.h"
-#include "clock.h"
-
-/*
- * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
- * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
- * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * Filling in table based on H4 boards available. There are quite a
- * few more rate combinations which could be defined.
- *
- * When multiple values are defined the start up will try and choose
- * the fastest one. If a 'fast' value is defined, then automatically,
- * the /2 one should be included as it can be used. Generally having
- * more than one fast set does not make sense, as static timings need
- * to be changed to change the set. The exception is the bypass
- * setting which is available for low power bypass.
- *
- * Note: This table needs to be sorted, fastest to slowest.
- **/
-const struct prcm_config omap2420_rate_table[] = {
- /* PRCM I - FAST */
- {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
- RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
- RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
- RATE_IN_242X},
-
- /* PRCM II - FAST */
- {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- /* PRCM III - FAST */
- {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- /* PRCM II - SLOW */
- {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- /* PRCM III - SLOW */
- {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- /* PRCM-VII (boot-bypass) */
- {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
- RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
- RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
- RATE_IN_242X},
-
- /* PRCM-VII (boot-bypass) */
- {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
- RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
- RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
- RATE_IN_242X},
-
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
deleted file mode 100644
index ded8b566a23a..000000000000
--- a/arch/arm/mach-omap2/opp2430_data.c
+++ /dev/null
@@ -1,136 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * opp2430_data.c - old-style "OPP" table for OMAP2430
- *
- * Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2009 Nokia Corporation
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratios' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
- *
- * XXX Missing voltage data.
- * XXX Missing 19.2MHz sys_clk rate sets.
- *
- * THe format described in this file is deprecated. Once a reasonable
- * OPP API exists, the data in this file should be converted to use it.
- *
- * This is technically part of the OMAP2xxx clock code.
- */
-
-#include <linux/kernel.h>
-
-#include "opp2xxx.h"
-#include "sdrc.h"
-#include "clock.h"
-
-/*
- * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
- * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
- * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * Filling in table based on 2430-SDPs variants available. There are
- * quite a few more rate combinations which could be defined.
- *
- * When multiple values are defined the start up will try and choose
- * the fastest one. If a 'fast' value is defined, then automatically,
- * the /2 one should be included as it can be used. Generally having
- * more than one fast set does not make sense, as static timings need
- * to be changed to change the set. The exception is the bypass
- * setting which is available for low power bypass.
- *
- * Note: This table needs to be sorted, fastest to slowest.
- */
-const struct prcm_config omap2430_rate_table[] = {
- /* PRCM #4 - ratio2 (ES2.1) - FAST */
- {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
- R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
- R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_133MHz,
- RATE_IN_243X},
-
- /* PRCM #2 - ratio1 (ES2) - FAST */
- {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_165MHz,
- RATE_IN_243X},
-
- /* PRCM #5a - ratio1 - FAST */
- {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_133MHz,
- RATE_IN_243X},
-
- /* PRCM #5b - ratio1 - FAST */
- {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_100MHz,
- RATE_IN_243X},
-
- /* PRCM #4 - ratio1 (ES2.1) - SLOW */
- {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
- R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
- R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_133MHz,
- RATE_IN_243X},
-
- /* PRCM #2 - ratio1 (ES2) - SLOW */
- {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_165MHz,
- RATE_IN_243X},
-
- /* PRCM #5a - ratio1 - SLOW */
- {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_133MHz,
- RATE_IN_243X},
-
- /* PRCM #5b - ratio1 - SLOW*/
- {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_100MHz,
- RATE_IN_243X},
-
- /* PRCM-boot/bypass */
- {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13MHz */
- RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
- RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_BYPASS,
- RATE_IN_243X},
-
- /* PRCM-boot/bypass */
- {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12MHz */
- RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
- RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
- SDRC_RFR_CTRL_BYPASS,
- RATE_IN_243X},
-
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
deleted file mode 100644
index a451182cdc02..000000000000
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ /dev/null
@@ -1,430 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
- *
- * Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2009 Nokia Corporation
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
- *
- * XXX Missing voltage data.
- *
- * THe format described in this file is deprecated. Once a reasonable
- * OPP API exists, the data in this file should be converted to use it.
- *
- * This is technically part of the OMAP2xxx clock code.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
-#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
-
-/**
- * struct prcm_config - define clock rates on a per-OPP basis (24xx)
- *
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
- * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * This is deprecated. As soon as we have a decent OPP API, we should
- * move all this stuff to it.
- */
-struct prcm_config {
- unsigned long xtal_speed; /* crystal rate */
- unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
- unsigned long mpu_speed; /* speed of MPU */
- unsigned long cm_clksel_mpu; /* mpu divider */
- unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
- unsigned long cm_clksel_gfx; /* gfx dividers */
- unsigned long cm_clksel1_core; /* major subsystem dividers */
- unsigned long cm_clksel1_pll; /* m,n */
- unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
- unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
- unsigned long base_sdrc_rfr; /* base refresh timing for a set */
- unsigned short flags;
-};
-
-
-/* Core fields for cm_clksel, not ratio governed */
-#define RX_CLKSEL_DSS1 (0x10 << 8)
-#define RX_CLKSEL_DSS2 (0x0 << 13)
-#define RX_CLKSEL_SSI (0x5 << 20)
-
-/*-------------------------------------------------------------------------
- * Voltage/DPLL ratios
- *-------------------------------------------------------------------------*/
-
-/* 2430 Ratio's, 2430-Ratio Config 1 */
-#define R1_CLKSEL_L3 (4 << 0)
-#define R1_CLKSEL_L4 (2 << 5)
-#define R1_CLKSEL_USB (4 << 25)
-#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- R1_CLKSEL_L4 | R1_CLKSEL_L3)
-#define R1_CLKSEL_MPU (2 << 0)
-#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
-#define R1_CLKSEL_DSP (2 << 0)
-#define R1_CLKSEL_DSP_IF (2 << 5)
-#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
-#define R1_CLKSEL_GFX (2 << 0)
-#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
-#define R1_CLKSEL_MDM (4 << 0)
-#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
-
-/* 2430-Ratio Config 2 */
-#define R2_CLKSEL_L3 (6 << 0)
-#define R2_CLKSEL_L4 (2 << 5)
-#define R2_CLKSEL_USB (2 << 25)
-#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- R2_CLKSEL_L4 | R2_CLKSEL_L3)
-#define R2_CLKSEL_MPU (2 << 0)
-#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
-#define R2_CLKSEL_DSP (2 << 0)
-#define R2_CLKSEL_DSP_IF (3 << 5)
-#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
-#define R2_CLKSEL_GFX (2 << 0)
-#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
-#define R2_CLKSEL_MDM (6 << 0)
-#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
-
-/* 2430-Ratio Bootm (BYPASS) */
-#define RB_CLKSEL_L3 (1 << 0)
-#define RB_CLKSEL_L4 (1 << 5)
-#define RB_CLKSEL_USB (1 << 25)
-#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- RB_CLKSEL_L4 | RB_CLKSEL_L3)
-#define RB_CLKSEL_MPU (1 << 0)
-#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
-#define RB_CLKSEL_DSP (1 << 0)
-#define RB_CLKSEL_DSP_IF (1 << 5)
-#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
-#define RB_CLKSEL_GFX (1 << 0)
-#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
-#define RB_CLKSEL_MDM (1 << 0)
-#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
-
-/* 2420 Ratio Equivalents */
-#define RXX_CLKSEL_VLYNQ (0x12 << 15)
-#define RXX_CLKSEL_SSI (0x8 << 20)
-
-/* 2420-PRCM III 532MHz core */
-#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
-#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
-#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
-#define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
- RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
- RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
- RIII_CLKSEL_L3)
-#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
-#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
-#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
-#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
-#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
-#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
-#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
-#define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
- RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
- RIII_CLKSEL_DSP)
-#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
-#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
-
-/* 2420-PRCM II 600MHz core */
-#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
-#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
-#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
-#define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \
- RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
- RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \
- RII_CLKSEL_L3)
-#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
-#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
-#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
-#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
-#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
-#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
-#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
-#define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \
- RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
- RII_CLKSEL_DSP)
-#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
-#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
-
-/* 2420-PRCM I 660MHz core */
-#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
-#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
-#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
-#define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \
- RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- RI_CLKSEL_L4 | RI_CLKSEL_L3)
-#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
-#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
-#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
-#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
-#define RI_SYNC_DSP (1 << 7) /* Activate sync */
-#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
-#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
-#define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \
- RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
- RI_CLKSEL_DSP)
-#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
-#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
-
-/* 2420-PRCM VII (boot) */
-#define RVII_CLKSEL_L3 (1 << 0)
-#define RVII_CLKSEL_L4 (1 << 5)
-#define RVII_CLKSEL_DSS1 (1 << 8)
-#define RVII_CLKSEL_DSS2 (0 << 13)
-#define RVII_CLKSEL_VLYNQ (1 << 15)
-#define RVII_CLKSEL_SSI (1 << 20)
-#define RVII_CLKSEL_USB (1 << 25)
-
-#define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
- RVII_CLKSEL_VLYNQ | \
- RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \
- RVII_CLKSEL_L4 | RVII_CLKSEL_L3)
-
-#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
-#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
-
-#define RVII_CLKSEL_DSP (1 << 0)
-#define RVII_CLKSEL_DSP_IF (1 << 5)
-#define RVII_SYNC_DSP (0 << 7)
-#define RVII_CLKSEL_IVA (1 << 8)
-#define RVII_SYNC_IVA (0 << 13)
-#define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \
- RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \
- RVII_CLKSEL_DSP)
-
-#define RVII_CLKSEL_GFX (1 << 0)
-#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
-
-/*-------------------------------------------------------------------------
- * 2430 Target modes: Along with each configuration the CPU has several
- * modes which goes along with them. Modes mainly are the addition of
- * describe DPLL combinations to go along with a ratio.
- *-------------------------------------------------------------------------*/
-
-/* Hardware governed */
-#define MX_48M_SRC (0 << 3)
-#define MX_54M_SRC (0 << 5)
-#define MX_APLLS_CLIKIN_12 (3 << 23)
-#define MX_APLLS_CLIKIN_13 (2 << 23)
-#define MX_APLLS_CLIKIN_19_2 (0 << 23)
-
-/*
- * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
- * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
- */
-#define M5A_DPLL_MULT_12 (133 << 12)
-#define M5A_DPLL_DIV_12 (5 << 8)
-#define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-#define M5A_DPLL_MULT_13 (61 << 12)
-#define M5A_DPLL_DIV_13 (2 << 8)
-#define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-#define M5A_DPLL_MULT_19 (55 << 12)
-#define M5A_DPLL_DIV_19 (3 << 8)
-#define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2)
-/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
-#define M5B_DPLL_MULT_12 (50 << 12)
-#define M5B_DPLL_DIV_12 (2 << 8)
-#define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-#define M5B_DPLL_MULT_13 (200 << 12)
-#define M5B_DPLL_DIV_13 (12 << 8)
-
-#define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-#define M5B_DPLL_MULT_19 (125 << 12)
-#define M5B_DPLL_DIV_19 (31 << 8)
-#define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2)
-/*
- * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
- */
-#define M4_DPLL_MULT_12 (133 << 12)
-#define M4_DPLL_DIV_12 (3 << 8)
-#define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-
-#define M4_DPLL_MULT_13 (399 << 12)
-#define M4_DPLL_DIV_13 (12 << 8)
-#define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-
-#define M4_DPLL_MULT_19 (145 << 12)
-#define M4_DPLL_DIV_19 (6 << 8)
-#define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2)
-
-/*
- * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
- */
-#define M3_DPLL_MULT_12 (55 << 12)
-#define M3_DPLL_DIV_12 (1 << 8)
-#define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-#define M3_DPLL_MULT_13 (76 << 12)
-#define M3_DPLL_DIV_13 (2 << 8)
-#define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-#define M3_DPLL_MULT_19 (17 << 12)
-#define M3_DPLL_DIV_19 (0 << 8)
-#define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2)
-
-/*
- * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
- */
-#define M2_DPLL_MULT_12 (55 << 12)
-#define M2_DPLL_DIV_12 (1 << 8)
-#define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-
-/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
- * relock time issue */
-/* Core frequency changed from 330/165 to 329/164 MHz*/
-#define M2_DPLL_MULT_13 (76 << 12)
-#define M2_DPLL_DIV_13 (2 << 8)
-#define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-
-#define M2_DPLL_MULT_19 (17 << 12)
-#define M2_DPLL_DIV_19 (0 << 8)
-#define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2)
-
-/* boot (boot) */
-#define MB_DPLL_MULT (1 << 12)
-#define MB_DPLL_DIV (0 << 8)
-#define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- MB_DPLL_DIV | MB_DPLL_MULT | \
- MX_APLLS_CLIKIN_12)
-
-#define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- MB_DPLL_DIV | MB_DPLL_MULT | \
- MX_APLLS_CLIKIN_13)
-
-#define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
- MB_DPLL_DIV | MB_DPLL_MULT | \
- MX_APLLS_CLIKIN_19)
-
-/*
- * 2430 - chassis (sedna)
- * 165 (ratio1) same as above #2
- * 150 (ratio1)
- * 133 (ratio2) same as above #4
- * 110 (ratio2) same as above #3
- * 104 (ratio2)
- * boot (boot)
- */
-
-/* PRCM I target DPLL = 2*330MHz = 660MHz */
-#define MI_DPLL_MULT_12 (55 << 12)
-#define MI_DPLL_DIV_12 (1 << 8)
-#define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-
-/*
- * 2420 Equivalent - mode registers
- * PRCM II , target DPLL = 2*300MHz = 600MHz
- */
-#define MII_DPLL_MULT_12 (50 << 12)
-#define MII_DPLL_DIV_12 (1 << 8)
-#define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12)
-#define MII_DPLL_MULT_13 (300 << 12)
-#define MII_DPLL_DIV_13 (12 << 8)
-#define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13)
-
-/* PRCM III target DPLL = 2*266 = 532MHz*/
-#define MIII_DPLL_MULT_12 (133 << 12)
-#define MIII_DPLL_DIV_12 (5 << 8)
-#define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
- MIII_DPLL_DIV_12 | \
- MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12)
-#define MIII_DPLL_MULT_13 (266 << 12)
-#define MIII_DPLL_DIV_13 (12 << 8)
-#define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
- MIII_DPLL_DIV_13 | \
- MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13)
-
-/* PRCM VII (boot bypass) */
-#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
-#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
-
-/* High and low operation value */
-#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
-#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
-
-/* MPU speed defines */
-#define S12M 12000000
-#define S13M 13000000
-#define S19M 19200000
-#define S26M 26000000
-#define S100M 100000000
-#define S133M 133000000
-#define S150M 150000000
-#define S164M 164000000
-#define S165M 165000000
-#define S199M 199000000
-#define S200M 200000000
-#define S266M 266000000
-#define S300M 300000000
-#define S329M 329000000
-#define S330M 330000000
-#define S399M 399000000
-#define S400M 400000000
-#define S532M 532000000
-#define S600M 600000000
-#define S658M 658000000
-#define S660M 660000000
-#define S798M 798000000
-
-
-extern const struct prcm_config omap2420_rate_table[];
-
-#ifdef CONFIG_SOC_OMAP2430
-extern const struct prcm_config omap2430_rate_table[];
-#else
-#define omap2430_rate_table NULL
-#endif
-extern const struct prcm_config *rate_table;
-extern const struct prcm_config *curr_prcm_set;
-
-#endif
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index b947bacf23a3..5cbd0a29966c 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -27,7 +27,6 @@
#include "clockdomain.h"
#include "common.h"
-#include "common-board-devices.h"
#include "control.h"
#include "omap_device.h"
#include "omap-secure.h"
@@ -42,15 +41,6 @@ struct pdata_init {
static struct of_dev_auxdata omap_auxdata_lookup[];
-#ifdef CONFIG_MACH_NOKIA_N8X0
-static void __init omap2420_n8x0_legacy_init(void)
-{
- omap_auxdata_lookup[0].platform_data = n8x0_legacy_init();
-}
-#else
-#define omap2420_n8x0_legacy_init NULL
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
/*
* Configures GPIOs 126, 127 and 129 to 1.8V mode instead of 3.0V
@@ -431,26 +421,9 @@ static void __init omap3_mcbsp_init(void)
static void __init omap3_mcbsp_init(void) {}
#endif
-/*
- * Few boards still need auxdata populated before we populate
- * the dev entries in of_platform_populate().
- */
-static struct pdata_init auxdata_quirks[] __initdata = {
-#ifdef CONFIG_SOC_OMAP2420
- { "nokia,n800", omap2420_n8x0_legacy_init, },
- { "nokia,n810", omap2420_n8x0_legacy_init, },
- { "nokia,n810-wimax", omap2420_n8x0_legacy_init, },
-#endif
- { /* sentinel */ },
-};
-
struct omap_sr_data __maybe_unused omap_sr_pdata[OMAP_SR_NR];
static struct of_dev_auxdata omap_auxdata_lookup[] = {
-#ifdef CONFIG_MACH_NOKIA_N8X0
- OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
- OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data),
-#endif
#ifdef CONFIG_ARCH_OMAP3
OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",
&omap3_iommu_pdata),
@@ -557,16 +530,14 @@ pdata_quirks_init_clocks(const struct of_device_id *omap_dt_match_table)
void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
{
/*
- * We still need this for omap2420 and omap3 PM to work, others are
+ * We still need this for omap3 PM to work, others are
* using drivers/misc/sram.c already.
*/
- if (of_machine_is_compatible("ti,omap2420") ||
- of_machine_is_compatible("ti,omap3"))
+ if (IS_ENABLED(CONFIG_ARCH_OMAP3) &&
+ of_machine_is_compatible("ti,omap3")) {
omap_sdrc_init(NULL, NULL);
-
- if (of_machine_is_compatible("ti,omap3"))
omap3_mcbsp_init();
- pdata_quirks_check(auxdata_quirks);
+ }
pdata_quirks_init_clocks(omap_dt_match_table);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index f97ff93f2fb4..5751b85e9ffb 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -43,11 +43,6 @@ extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
#endif /* CONFIG_PM_DEBUG */
-/* 24xx */
-extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
- void __iomem *sdrc_power);
-extern unsigned int omap24xx_cpu_suspend_sz;
-
/* 3xxx */
extern void omap34xx_cpu_suspend(int save_state);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index fbc89999460b..eaf6d1104dc2 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -244,8 +244,6 @@ int pwrdm_post_transition(struct powerdomain *pwrdm);
extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
-extern void omap242x_powerdomains_init(void);
-extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
@@ -253,7 +251,6 @@ extern void omap54xx_powerdomains_init(void);
extern void dra7xx_powerdomains_init(void);
void am43xx_powerdomains_init(void);
-extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
extern struct pwrdm_ops am33xx_pwrdm_operations;
extern struct pwrdm_ops omap4_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
deleted file mode 100644
index fa259adbdc61..000000000000
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2XXX powerdomain definitions
- *
- * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
- * Copyright (C) 2007-2011 Nokia Corporation
- *
- * Paul Walmsley, Jouni Högander
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include "soc.h"
-#include "powerdomain.h"
-#include "powerdomains2xxx_3xxx_data.h"
-
-#include "prcm-common.h"
-#include "prm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
-
-/* 24XX powerdomains and dependencies */
-
-/* Powerdomains */
-
-static struct powerdomain dsp_pwrdm = {
- .name = "dsp_pwrdm",
- .prcm_offs = OMAP24XX_DSP_MOD,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_RET,
- .banks = 1,
- .pwrsts_mem_ret = {
- [0] = PWRSTS_RET,
- },
- .pwrsts_mem_on = {
- [0] = PWRSTS_ON,
- },
- .voltdm = { .name = "core" },
-};
-
-static struct powerdomain mpu_24xx_pwrdm = {
- .name = "mpu_pwrdm",
- .prcm_offs = MPU_MOD,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_OFF_RET,
- .banks = 1,
- .pwrsts_mem_ret = {
- [0] = PWRSTS_RET,
- },
- .pwrsts_mem_on = {
- [0] = PWRSTS_ON,
- },
- .voltdm = { .name = "core" },
-};
-
-static struct powerdomain core_24xx_pwrdm = {
- .name = "core_pwrdm",
- .prcm_offs = CORE_MOD,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_RET,
- .banks = 3,
- .pwrsts_mem_ret = {
- [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
- [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
- [2] = PWRSTS_OFF_RET, /* MEM3RETSTATE */
- },
- .pwrsts_mem_on = {
- [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
- [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
- [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
- },
- .voltdm = { .name = "core" },
-};
-
-
-/*
- * 2430-specific powerdomains
- */
-
-/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
-
-static struct powerdomain mdm_pwrdm = {
- .name = "mdm_pwrdm",
- .prcm_offs = OMAP2430_MDM_MOD,
- .pwrsts = PWRSTS_OFF_RET_ON,
- .pwrsts_logic_ret = PWRSTS_RET,
- .banks = 1,
- .pwrsts_mem_ret = {
- [0] = PWRSTS_RET, /* MEMRETSTATE */
- },
- .pwrsts_mem_on = {
- [0] = PWRSTS_ON, /* MEMONSTATE */
- },
- .voltdm = { .name = "core" },
-};
-
-/*
- *
- */
-
-static struct powerdomain *powerdomains_omap24xx[] __initdata = {
- &wkup_omap2_pwrdm,
- &gfx_omap2_pwrdm,
- &dsp_pwrdm,
- &mpu_24xx_pwrdm,
- &core_24xx_pwrdm,
- NULL
-};
-
-static struct powerdomain *powerdomains_omap2430[] __initdata = {
- &mdm_pwrdm,
- NULL
-};
-
-void __init omap242x_powerdomains_init(void)
-{
- if (!cpu_is_omap2420())
- return;
-
- pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
- pwrdm_register_pwrdms(powerdomains_omap24xx);
- pwrdm_complete_init();
-}
-
-void __init omap243x_powerdomains_init(void)
-{
- if (!cpu_is_omap2430())
- return;
-
- pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
- pwrdm_register_pwrdms(powerdomains_omap24xx);
- pwrdm_register_pwrdms(powerdomains_omap2430);
- pwrdm_complete_init();
-}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 5e3544a63526..e326bb6a09db 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -27,12 +27,6 @@
#define PLL_MOD 0x500
-/* Chip-specific module offsets */
-#define OMAP24XX_GR_MOD OCP_MOD
-#define OMAP24XX_DSP_MOD 0x800
-
-#define OMAP2430_MDM_MOD 0xc00
-
/* IVA2 module is < base on 3430 */
#define OMAP3430_IVA2_MOD -0x800
#define OMAP3430ES2_SGX_MOD GFX_MOD
@@ -63,147 +57,6 @@
#define TI816X_PRM_SGX_MOD 0x0f00
#define TI81XX_PRM_ALWON_MOD 0x1800
-/* 24XX register bits shared between CM & PRM registers */
-
-/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-#define OMAP2420_EN_MMC_SHIFT 26
-#define OMAP2420_EN_MMC_MASK (1 << 26)
-#define OMAP24XX_EN_UART2_SHIFT 22
-#define OMAP24XX_EN_UART2_MASK (1 << 22)
-#define OMAP24XX_EN_UART1_SHIFT 21
-#define OMAP24XX_EN_UART1_MASK (1 << 21)
-#define OMAP24XX_EN_MCSPI2_SHIFT 18
-#define OMAP24XX_EN_MCSPI2_MASK (1 << 18)
-#define OMAP24XX_EN_MCSPI1_SHIFT 17
-#define OMAP24XX_EN_MCSPI1_MASK (1 << 17)
-#define OMAP24XX_EN_MCBSP2_SHIFT 16
-#define OMAP24XX_EN_MCBSP2_MASK (1 << 16)
-#define OMAP24XX_EN_MCBSP1_SHIFT 15
-#define OMAP24XX_EN_MCBSP1_MASK (1 << 15)
-#define OMAP24XX_EN_GPT12_SHIFT 14
-#define OMAP24XX_EN_GPT12_MASK (1 << 14)
-#define OMAP24XX_EN_GPT11_SHIFT 13
-#define OMAP24XX_EN_GPT11_MASK (1 << 13)
-#define OMAP24XX_EN_GPT10_SHIFT 12
-#define OMAP24XX_EN_GPT10_MASK (1 << 12)
-#define OMAP24XX_EN_GPT9_SHIFT 11
-#define OMAP24XX_EN_GPT9_MASK (1 << 11)
-#define OMAP24XX_EN_GPT8_SHIFT 10
-#define OMAP24XX_EN_GPT8_MASK (1 << 10)
-#define OMAP24XX_EN_GPT7_SHIFT 9
-#define OMAP24XX_EN_GPT7_MASK (1 << 9)
-#define OMAP24XX_EN_GPT6_SHIFT 8
-#define OMAP24XX_EN_GPT6_MASK (1 << 8)
-#define OMAP24XX_EN_GPT5_SHIFT 7
-#define OMAP24XX_EN_GPT5_MASK (1 << 7)
-#define OMAP24XX_EN_GPT4_SHIFT 6
-#define OMAP24XX_EN_GPT4_MASK (1 << 6)
-#define OMAP24XX_EN_GPT3_SHIFT 5
-#define OMAP24XX_EN_GPT3_MASK (1 << 5)
-#define OMAP24XX_EN_GPT2_SHIFT 4
-#define OMAP24XX_EN_GPT2_MASK (1 << 4)
-#define OMAP2420_EN_VLYNQ_SHIFT 3
-#define OMAP2420_EN_VLYNQ_MASK (1 << 3)
-
-/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
-#define OMAP2430_EN_GPIO5_SHIFT 10
-#define OMAP2430_EN_GPIO5_MASK (1 << 10)
-#define OMAP2430_EN_MCSPI3_SHIFT 9
-#define OMAP2430_EN_MCSPI3_MASK (1 << 9)
-#define OMAP2430_EN_MMCHS2_SHIFT 8
-#define OMAP2430_EN_MMCHS2_MASK (1 << 8)
-#define OMAP2430_EN_MMCHS1_SHIFT 7
-#define OMAP2430_EN_MMCHS1_MASK (1 << 7)
-#define OMAP24XX_EN_UART3_SHIFT 2
-#define OMAP24XX_EN_UART3_MASK (1 << 2)
-#define OMAP24XX_EN_USB_SHIFT 0
-#define OMAP24XX_EN_USB_MASK (1 << 0)
-
-/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
-#define OMAP2430_EN_MDM_INTC_SHIFT 11
-#define OMAP2430_EN_MDM_INTC_MASK (1 << 11)
-#define OMAP2430_EN_USBHS_SHIFT 6
-#define OMAP2430_EN_USBHS_MASK (1 << 6)
-#define OMAP24XX_EN_GPMC_SHIFT 1
-#define OMAP24XX_EN_GPMC_MASK (1 << 1)
-
-/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
-#define OMAP2420_ST_MMC_SHIFT 26
-#define OMAP2420_ST_MMC_MASK (1 << 26)
-#define OMAP24XX_ST_UART2_SHIFT 22
-#define OMAP24XX_ST_UART2_MASK (1 << 22)
-#define OMAP24XX_ST_UART1_SHIFT 21
-#define OMAP24XX_ST_UART1_MASK (1 << 21)
-#define OMAP24XX_ST_MCSPI2_SHIFT 18
-#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
-#define OMAP24XX_ST_MCSPI1_SHIFT 17
-#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
-#define OMAP24XX_ST_MCBSP2_SHIFT 16
-#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
-#define OMAP24XX_ST_MCBSP1_SHIFT 15
-#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
-#define OMAP24XX_ST_GPT12_SHIFT 14
-#define OMAP24XX_ST_GPT12_MASK (1 << 14)
-#define OMAP24XX_ST_GPT11_SHIFT 13
-#define OMAP24XX_ST_GPT11_MASK (1 << 13)
-#define OMAP24XX_ST_GPT10_SHIFT 12
-#define OMAP24XX_ST_GPT10_MASK (1 << 12)
-#define OMAP24XX_ST_GPT9_SHIFT 11
-#define OMAP24XX_ST_GPT9_MASK (1 << 11)
-#define OMAP24XX_ST_GPT8_SHIFT 10
-#define OMAP24XX_ST_GPT8_MASK (1 << 10)
-#define OMAP24XX_ST_GPT7_SHIFT 9
-#define OMAP24XX_ST_GPT7_MASK (1 << 9)
-#define OMAP24XX_ST_GPT6_SHIFT 8
-#define OMAP24XX_ST_GPT6_MASK (1 << 8)
-#define OMAP24XX_ST_GPT5_SHIFT 7
-#define OMAP24XX_ST_GPT5_MASK (1 << 7)
-#define OMAP24XX_ST_GPT4_SHIFT 6
-#define OMAP24XX_ST_GPT4_MASK (1 << 6)
-#define OMAP24XX_ST_GPT3_SHIFT 5
-#define OMAP24XX_ST_GPT3_MASK (1 << 5)
-#define OMAP24XX_ST_GPT2_SHIFT 4
-#define OMAP24XX_ST_GPT2_MASK (1 << 4)
-#define OMAP2420_ST_VLYNQ_SHIFT 3
-#define OMAP2420_ST_VLYNQ_MASK (1 << 3)
-
-/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
-#define OMAP2430_ST_MDM_INTC_SHIFT 11
-#define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
-#define OMAP2430_ST_GPIO5_SHIFT 10
-#define OMAP2430_ST_GPIO5_MASK (1 << 10)
-#define OMAP2430_ST_MCSPI3_SHIFT 9
-#define OMAP2430_ST_MCSPI3_MASK (1 << 9)
-#define OMAP2430_ST_MMCHS2_SHIFT 8
-#define OMAP2430_ST_MMCHS2_MASK (1 << 8)
-#define OMAP2430_ST_MMCHS1_SHIFT 7
-#define OMAP2430_ST_MMCHS1_MASK (1 << 7)
-#define OMAP2430_ST_USBHS_SHIFT 6
-#define OMAP2430_ST_USBHS_MASK (1 << 6)
-#define OMAP24XX_ST_UART3_SHIFT 2
-#define OMAP24XX_ST_UART3_MASK (1 << 2)
-#define OMAP24XX_ST_USB_SHIFT 0
-#define OMAP24XX_ST_USB_MASK (1 << 0)
-
-/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP24XX_EN_GPIOS_SHIFT 2
-#define OMAP24XX_EN_GPIOS_MASK (1 << 2)
-#define OMAP24XX_EN_GPT1_SHIFT 0
-#define OMAP24XX_EN_GPT1_MASK (1 << 0)
-
-/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
-#define OMAP24XX_ST_GPIOS_SHIFT 2
-#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
-#define OMAP24XX_ST_32KSYNC_SHIFT 1
-#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
-#define OMAP24XX_ST_GPT1_SHIFT 0
-#define OMAP24XX_ST_GPT1_MASK (1 << 0)
-
-/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
-#define OMAP2430_ST_MDM_SHIFT 0
-#define OMAP2430_ST_MDM_MASK (1 << 0)
-
-
/* 3430 register bits shared between CM & PRM registers */
/* CM_REVISION, PRM_REVISION shared bits */
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
deleted file mode 100644
index ff83801f6439..000000000000
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
-
-/*
- * OMAP24XX Power/Reset Management register bits
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
- *
- * Written by Paul Walmsley
- */
-
-#include "prm2xxx.h"
-
-#define OMAP24XX_EN_CORE_SHIFT 0
-#define OMAP24XX_FORCESTATE_MASK (1 << 18)
-#define OMAP24XX_AUTOIDLE_MASK (1 << 0)
-#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15)
-#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
-#define OMAP24XX_MEMRETCTRL_MASK (1 << 8)
-#define OMAP24XX_SETRET_LEVEL_SHIFT 6
-#define OMAP24XX_VOLT_LEVEL_SHIFT 0
-#define OMAP2420_CLKOUT2_EN_SHIFT 15
-#define OMAP2420_CLKOUT2_DIV_SHIFT 11
-#define OMAP2420_CLKOUT2_DIV_WIDTH 3
-#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
-#define OMAP24XX_CLKOUT_EN_SHIFT 7
-#define OMAP24XX_CLKOUT_DIV_SHIFT 3
-#define OMAP24XX_CLKOUT_DIV_WIDTH 3
-#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
-#define OMAP24XX_EMULATION_EN_SHIFT 0
-#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
-#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
-#define OMAP24XX_EXTWMPU_RST_SHIFT 6
-#define OMAP24XX_SECU_WD_RST_SHIFT 5
-#define OMAP24XX_MPU_WD_RST_SHIFT 4
-#define OMAP24XX_SECU_VIOL_RST_SHIFT 3
-#endif
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
deleted file mode 100644
index 35a58f54b528..000000000000
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ /dev/null
@@ -1,229 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2xxx PRM module functions
- *
- * Copyright (C) 2010-2012 Texas Instruments, Inc.
- * Copyright (C) 2010 Nokia Corporation
- * Benoît Cousson
- * Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-
-#include "powerdomain.h"
-#include "clockdomain.h"
-#include "prm2xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
-
-/*
- * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
- * these are reversed from the bits used on OMAP3+
- */
-#define OMAP24XX_PWRDM_POWER_ON 0x0
-#define OMAP24XX_PWRDM_POWER_RET 0x1
-#define OMAP24XX_PWRDM_POWER_OFF 0x3
-
-/*
- * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
- * hardware register (which are specific to the OMAP2xxx SoCs) to
- * reset source ID bit shifts (which is an OMAP SoC-independent
- * enumeration)
- */
-static struct prm_reset_src_map omap2xxx_prm_reset_src_map[] = {
- { OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
- { OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
- { OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
- { OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
- { OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
- { OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
- { -1, -1 },
-};
-
-/**
- * omap2xxx_prm_read_reset_sources - return the last SoC reset source
- *
- * Return a u32 representing the last reset sources of the SoC. The
- * returned reset source bits are standardized across OMAP SoCs.
- */
-static u32 omap2xxx_prm_read_reset_sources(void)
-{
- struct prm_reset_src_map *p;
- u32 r = 0;
- u32 v;
-
- v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
-
- p = omap2xxx_prm_reset_src_map;
- while (p->reg_shift >= 0 && p->std_shift >= 0) {
- if (v & (1 << p->reg_shift))
- r |= 1 << p->std_shift;
- p++;
- }
-
- return r;
-}
-
-/**
- * omap2xxx_pwrst_to_common_pwrst - convert OMAP2xxx pwrst to common pwrst
- * @omap2xxx_pwrst: OMAP2xxx hardware power state to convert
- *
- * Return the common power state bits corresponding to the OMAP2xxx
- * hardware power state bits @omap2xxx_pwrst, or -EINVAL upon error.
- */
-static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
-{
- u8 pwrst;
-
- switch (omap2xxx_pwrst) {
- case OMAP24XX_PWRDM_POWER_OFF:
- pwrst = PWRDM_POWER_OFF;
- break;
- case OMAP24XX_PWRDM_POWER_RET:
- pwrst = PWRDM_POWER_RET;
- break;
- case OMAP24XX_PWRDM_POWER_ON:
- pwrst = PWRDM_POWER_ON;
- break;
- default:
- return -EINVAL;
- }
-
- return pwrst;
-}
-
-/**
- * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
- *
- * Set the DPLL reset bit, which should reboot the SoC. This is the
- * recommended way to restart the SoC. No return value.
- */
-static void omap2xxx_prm_dpll_reset(void)
-{
- omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
- OMAP2_RM_RSTCTRL);
- /* OCP barrier */
- omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
-}
-
-/**
- * omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module
- * @module: PRM module to clear wakeups from
- * @regs: register offset to clear
- * @wkst_mask: wakeup status mask to clear
- *
- * Clears wakeup status bits for a given module, so that the device can
- * re-enter idle.
- */
-static int omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
-{
- u32 wkst;
-
- wkst = omap2_prm_read_mod_reg(module, regs);
- wkst &= wkst_mask;
- omap2_prm_write_mod_reg(wkst, module, regs);
- return 0;
-}
-
-int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
-{
- omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
- clkdm->pwrdm.ptr->prcm_offs,
- OMAP2_PM_PWSTCTRL);
- return 0;
-}
-
-int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
-{
- omap2_prm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
- clkdm->pwrdm.ptr->prcm_offs,
- OMAP2_PM_PWSTCTRL);
- return 0;
-}
-
-static int omap2xxx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
-{
- u8 omap24xx_pwrst;
-
- switch (pwrst) {
- case PWRDM_POWER_OFF:
- omap24xx_pwrst = OMAP24XX_PWRDM_POWER_OFF;
- break;
- case PWRDM_POWER_RET:
- omap24xx_pwrst = OMAP24XX_PWRDM_POWER_RET;
- break;
- case PWRDM_POWER_ON:
- omap24xx_pwrst = OMAP24XX_PWRDM_POWER_ON;
- break;
- default:
- return -EINVAL;
- }
-
- omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
- (omap24xx_pwrst << OMAP_POWERSTATE_SHIFT),
- pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
- return 0;
-}
-
-static int omap2xxx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
-{
- u8 omap2xxx_pwrst;
-
- omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
- OMAP2_PM_PWSTCTRL,
- OMAP_POWERSTATE_MASK);
-
- return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
-}
-
-static int omap2xxx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
-{
- u8 omap2xxx_pwrst;
-
- omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
- OMAP2_PM_PWSTST,
- OMAP_POWERSTATEST_MASK);
-
- return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
-}
-
-struct pwrdm_ops omap2_pwrdm_operations = {
- .pwrdm_set_next_pwrst = omap2xxx_pwrdm_set_next_pwrst,
- .pwrdm_read_next_pwrst = omap2xxx_pwrdm_read_next_pwrst,
- .pwrdm_read_pwrst = omap2xxx_pwrdm_read_pwrst,
- .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
- .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
- .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
- .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
- .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
- .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
-};
-
-/*
- *
- */
-
-static struct prm_ll_data omap2xxx_prm_ll_data = {
- .read_reset_sources = &omap2xxx_prm_read_reset_sources,
- .assert_hardreset = &omap2_prm_assert_hardreset,
- .deassert_hardreset = &omap2_prm_deassert_hardreset,
- .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
- .reset_system = &omap2xxx_prm_dpll_reset,
- .clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
-};
-
-int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
-{
- return prm_register(&omap2xxx_prm_ll_data);
-}
-
-static void __exit omap2xxx_prm_exit(void)
-{
- prm_unregister(&omap2xxx_prm_ll_data);
-}
-__exitcall(omap2xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
deleted file mode 100644
index 659b917348f8..000000000000
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * OMAP2xxx Power/Reset Management (PRM) register definitions
- *
- * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- * Paul Walmsley
- *
- * The PRM hardware modules on the OMAP2/3 are quite similar to each
- * other. The PRM on OMAP4 has a new register layout, and is handled
- * in a separate file.
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
-
-#include "prcm-common.h"
-#include "prm.h"
-#include "prm2xxx_3xxx.h"
-
-#define OMAP2420_PRM_REGADDR(module, reg) \
- OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
-#define OMAP2430_PRM_REGADDR(module, reg) \
- OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
-
-/*
- * OMAP2-specific global PRM registers
- * Use {read,write}l_relaxed() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
- * bits.)
- *
- */
-
-#define OMAP2_PRCM_REVISION_OFFSET 0x0000
-#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
-#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
-
-#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
-#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
-#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
-
-#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
-#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
-#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
-#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
-#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
-#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
-#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
-#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
-#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
-#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
-#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
-
-#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
-
-#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
-
-#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
-
-/*
- * Module specific PRM register offsets from PRM_BASE + domain offset
- *
- * Use prm_{read,write}_mod_reg() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
- * IRQSTATUS and IRQENABLE bits.)
- */
-
-/* Register offsets appearing on both OMAP2 and OMAP3 */
-
-#define OMAP2_RM_RSTCTRL 0x0050
-#define OMAP2_RM_RSTTIME 0x0054
-#define OMAP2_RM_RSTST 0x0058
-#define OMAP2_PM_PWSTCTRL 0x00e0
-#define OMAP2_PM_PWSTST 0x00e4
-
-#define PM_WKEN 0x00a0
-#define PM_WKEN1 PM_WKEN
-#define PM_WKST 0x00b0
-#define PM_WKST1 PM_WKST
-#define PM_WKDEP 0x00c8
-#define PM_EVGENCTRL 0x00d4
-#define PM_EVGENONTIM 0x00d8
-#define PM_EVGENOFFTIM 0x00dc
-
-/* OMAP2xxx specific register offsets */
-#define OMAP24XX_PM_WKEN2 0x00a4
-#define OMAP24XX_PM_WKST2 0x00b4
-
-#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
-#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
-#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
-#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
-
-#ifndef __ASSEMBLER__
-/* Function prototypes */
-extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
-extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
-
-int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index d983efac6f4f..afaba7153ece 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -15,7 +15,6 @@
#include "powerdomain.h"
#include "prm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
#include "clockdomain.h"
/**
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index ee4588acda50..3546e7292bfb 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -26,7 +26,6 @@
#include "soc.h"
#include "prm2xxx_3xxx.h"
-#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm33xx.h"
#include "prm44xx.h"
@@ -582,13 +581,6 @@ int prm_unregister(struct prm_ll_data *pld)
return 0;
}
-#ifdef CONFIG_ARCH_OMAP2
-static struct omap_prcm_init_data omap2_prm_data __initdata = {
- .index = TI_CLKM_PRM,
- .init = omap2xxx_prm_init,
-};
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
static struct omap_prcm_init_data omap3_prm_data __initdata = {
.index = TI_CLKM_PRM,
@@ -670,9 +662,6 @@ static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
{ .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data },
{ .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
#endif
-#ifdef CONFIG_ARCH_OMAP2
- { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
-#endif
#ifdef CONFIG_ARCH_OMAP3
{ .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
#endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 45b35422b587..c34fba4d2f1a 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -90,17 +90,7 @@ struct memory_timings {
u32 base_cs; /* base chip select to use for calculations */
};
-extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
-
-u32 omap2xxx_sdrc_dll_is_unlocked(void);
-u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
-
-
#else
-#define OMAP242X_SDRC_REGADDR(reg) \
- OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
-#define OMAP243X_SDRC_REGADDR(reg) \
- OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
#define OMAP34XX_SDRC_REGADDR(reg) \
OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
@@ -184,17 +174,6 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
-/*
- * SMS register access
- */
-
-#define OMAP242X_SMS_REGADDR(reg) \
- (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
-#define OMAP243X_SMS_REGADDR(reg) \
- (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
-#define OMAP343X_SMS_REGADDR(reg) \
- (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
-
/* SMS register offsets - read/write with sms_{read,write}_reg() */
#define SMS_SYSCONFIG 0x010
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
deleted file mode 100644
index 5a275b4fd404..000000000000
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ /dev/null
@@ -1,164 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * SDRAM timing related functions for OMAP2xxx
- *
- * Copyright (C) 2005, 2008 Texas Instruments Inc.
- * Copyright (C) 2005, 2008 Nokia Corporation
- *
- * Tony Lindgren <tony@atomide.com>
- * Paul Walmsley
- * Richard Woodruff <r-woodruff2@ti.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "common.h"
-#include "prm2xxx.h"
-#include "clock.h"
-#include "sdrc.h"
-#include "sram.h"
-
-/* Memory timing, DLL mode flags */
-#define M_DDR 1
-#define M_LOCK_CTRL (1 << 2)
-#define M_UNLOCK 0
-#define M_LOCK 1
-
-
-static struct memory_timings mem_timings;
-static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
-
-static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
-{
- return mem_timings.slow_dll_ctrl;
-}
-
-static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
-{
- return mem_timings.fast_dll_ctrl;
-}
-
-static u32 omap2xxx_sdrc_get_type(void)
-{
- return mem_timings.m_type;
-}
-
-/*
- * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compensate for the shifted DLL value in unlock mode.
- */
-u32 omap2xxx_sdrc_dll_is_unlocked(void)
-{
- /* dlla and dllb are a set */
- u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
-
- if ((dll_state & (1 << 2)) == (1 << 2))
- return 1;
- else
- return 0;
-}
-
-/*
- * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
- * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
- * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
- *
- * Used by the clock framework during CORE DPLL changes
- */
-u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
-{
- u32 dll_ctrl, m_type;
- u32 prev = curr_perf_level;
- unsigned long flags;
-
- if ((curr_perf_level == level) && !force)
- return prev;
-
- if (level == CORE_CLK_SRC_DPLL)
- dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
- else if (level == CORE_CLK_SRC_DPLL_X2)
- dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
- else
- return prev;
-
- m_type = omap2xxx_sdrc_get_type();
-
- local_irq_save(flags);
- /*
- * XXX These calls should be abstracted out through a
- * prm2xxx.c function
- */
- if (cpu_is_omap2420())
- writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
- else
- writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
- omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
- curr_perf_level = level;
- local_irq_restore(flags);
-
- return prev;
-}
-
-/* Used by the clock framework during CORE DPLL changes */
-void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
-{
- unsigned long dll_cnt;
- u32 fast_dll = 0;
-
- /* DDR = 1, SDR = 0 */
- mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
-
- /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
- * In the case of 2422, its ok to use CS1 instead of CS0.
- */
- if (cpu_is_omap2422())
- mem_timings.base_cs = 1;
- else
- mem_timings.base_cs = 0;
-
- if (mem_timings.m_type != M_DDR)
- return;
-
- /* With DDR we need to determine the low frequency DLL value */
- if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
- mem_timings.dll_mode = M_UNLOCK;
- else
- mem_timings.dll_mode = M_LOCK;
-
- if (mem_timings.base_cs == 0) {
- fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
- dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
- } else {
- fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
- dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
- }
- if (force_lock_to_unlock_mode) {
- fast_dll &= ~0xff00;
- fast_dll |= dll_cnt; /* Current lock mode */
- }
- /* set fast timings with DLL filter disabled */
- mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
-
- /* No disruptions, DDR will be offline & C-ABI not followed */
- omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
- mem_timings.fast_dll_ctrl,
- mem_timings.base_cs,
- force_lock_to_unlock_mode);
- mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
-
- /* Turn status into unlock ctrl */
- mem_timings.slow_dll_ctrl |=
- ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
-
- /* 90 degree phase for anything below 133MHz + disable DLL filter */
- mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
-}
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
deleted file mode 100644
index 84d8c43ad382..000000000000
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * linux/arch/arm/mach-omap2/sleep.S
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * (C) Copyright 2006 Nokia Corporation
- * Fixed idle loop sleep
- * Igor Stoppa <igor.stoppa@nokia.com>
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-#include "omap24xx.h"
-#include "sdrc.h"
-
-/* First address of reserved address space? apparently valid for OMAP2 & 3 */
-#define A_SDRC0_V (0xC0000000)
-
- .text
-
-/*
- * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
- * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
- * SDRC.
- *
- * Input:
- * R0 : DLL ctrl value pre-Sleep
- * R1 : SDRC_DLLA_CTRL
- * R2 : SDRC_POWER
- *
- * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
- * when we get called, but the DLL probably isn't. We will wait a bit more in
- * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
- * if in unlocked mode.
- *
- * For less than 242x-ES2.2 upon wake from a sleep mode where the external
- * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
- * clock can pass into the PRCM can cause problems at DSP and IVA.
- * To work around this the code will switch to the 32kHz source prior to sleep.
- * Post sleep we will shift back to using the DPLL. Apparently,
- * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait
- * 3x12MHz + 3x32kHz clocks for a full switch.
- *
- * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
- * at wake
- */
- .align 3
-ENTRY(omap24xx_cpu_suspend)
- stmfd sp!, {r0 - r12, lr} @ save registers on stack
- mov r3, #0x0 @ clear for mcr call
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
- nop
- nop
- ldr r4, [r2] @ read SDRC_POWER
- orr r4, r4, #0x40 @ enable self refresh on idle req
- mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
- str r4, [r2] @ make it so
- nop
- mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
- nop
-loop:
- subs r5, r5, #0x1 @ awake, wait just a bit
- bne loop
-
- /* The DPLL has to be on before we take the DDR out of self refresh */
- bic r4, r4, #0x40 @ now clear self refresh bit.
- str r4, [r2] @ write to SDRC_POWER
- ldr r4, A_SDRC0 @ make a clock happen
- ldr r4, [r4] @ read A_SDRC0
- nop @ start auto refresh only after clk ok
- movs r0, r0 @ see if DDR or SDR
- strne r0, [r1] @ rewrite DLLA to force DLL reload
- addne r1, r1, #0x8 @ move to DLLB
- strne r0, [r1] @ rewrite DLLB to force DLL reload
-
- mov r5, #0x1000
-loop2:
- subs r5, r5, #0x1
- bne loop2
- /* resume*/
- ldmfd sp!, {r0 - r12, pc} @ restore regs and return
-
-A_SDRC0:
- .word A_SDRC0_V
-
-ENTRY(omap24xx_cpu_suspend_sz)
- .word . - omap24xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 9e3dbb743e5c..9c9f56ca9142 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -12,7 +12,6 @@
* Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com>
*/
-#include "omap24xx.h"
#include "omap34xx.h"
#include "omap44xx.h"
#include "ti81xx.h"
@@ -62,9 +61,6 @@ static inline int soc_is_omap(void)
/*
* Macros to group OMAP into cpu classes.
* These can be used in most places.
- * soc_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
- * soc_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
- * soc_is_omap243x(): True for OMAP2430
* soc_is_omap343x(): True for OMAP3430
* soc_is_omap443x(): True for OMAP4430
* soc_is_omap446x(): True for OMAP4460
@@ -137,7 +133,6 @@ static inline int is_dra ##subclass ##_ ##package (void) \
return (is_dra ##subclass () && GET_DRA_PACKAGE == id) ? 1 : 0; \
}
-IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
IS_AM_CLASS(35xx, 0x35)
@@ -148,8 +143,6 @@ IS_AM_CLASS(43xx, 0x43)
IS_TI_CLASS(81xx, 0x81)
IS_DRA_CLASS(7xx, 0x7)
-IS_OMAP_SUBCLASS(242x, 0x242)
-IS_OMAP_SUBCLASS(243x, 0x243)
IS_OMAP_SUBCLASS(343x, 0x343)
IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
@@ -186,21 +179,6 @@ IS_DRA_SUBCLASS(72x, 0x72)
#define soc_is_dra74x() 0
#define soc_is_dra72x() 0
-#if defined(CONFIG_ARCH_OMAP2)
-# define soc_is_omap24xx() is_omap24xx()
-#else
-# define soc_is_omap24xx() 0
-#endif
-#if defined(CONFIG_SOC_OMAP2420)
-# define soc_is_omap242x() is_omap242x()
-#else
-# define soc_is_omap242x() 0
-#endif
-#if defined(CONFIG_SOC_OMAP2430)
-# define soc_is_omap243x() is_omap243x()
-#else
-# define soc_is_omap243x() 0
-#endif
#if defined(CONFIG_ARCH_OMAP3)
# define soc_is_omap34xx() is_omap34xx()
# define soc_is_omap343x() is_omap343x()
@@ -212,10 +190,6 @@ IS_DRA_SUBCLASS(72x, 0x72)
/*
* Macros to detect individual cpu types.
* These are only rarely needed.
- * soc_is_omap2420(): True for OMAP2420
- * soc_is_omap2422(): True for OMAP2422
- * soc_is_omap2423(): True for OMAP2423
- * soc_is_omap2430(): True for OMAP2430
* soc_is_omap3430(): True for OMAP3430
*/
#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
@@ -226,16 +200,8 @@ static inline int is_omap ##type (void) \
return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
}
-IS_OMAP_TYPE(2420, 0x2420)
-IS_OMAP_TYPE(2422, 0x2422)
-IS_OMAP_TYPE(2423, 0x2423)
-IS_OMAP_TYPE(2430, 0x2430)
IS_OMAP_TYPE(3430, 0x3430)
-#define soc_is_omap2420() 0
-#define soc_is_omap2422() 0
-#define soc_is_omap2423() 0
-#define soc_is_omap2430() 0
#define soc_is_omap3430() 0
#define soc_is_omap3630() 0
#define soc_is_omap5430() 0
@@ -252,17 +218,6 @@ IS_OMAP_TYPE(3430, 0x3430)
#define cpu_class_is_omap1() 0
#define cpu_class_is_omap2() 1
-#if defined(CONFIG_ARCH_OMAP2)
-# undef soc_is_omap2420
-# undef soc_is_omap2422
-# undef soc_is_omap2423
-# undef soc_is_omap2430
-# define soc_is_omap2420() is_omap2420()
-# define soc_is_omap2422() is_omap2422()
-# define soc_is_omap2423() is_omap2423()
-# define soc_is_omap2430() is_omap2430()
-#endif
-
#if defined(CONFIG_ARCH_OMAP3)
# undef soc_is_omap3430
# undef soc_is_ti81xx
@@ -326,13 +281,6 @@ IS_OMAP_TYPE(3430, 0x3430)
#endif
/* Various silicon revisions for omap2 */
-#define OMAP242X_CLASS 0x24200024
-#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
-#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
-
-#define OMAP243X_CLASS 0x24300024
-#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
-
#define OMAP343X_CLASS 0x34300034
#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
@@ -400,7 +348,6 @@ IS_OMAP_TYPE(3430, 0x3430)
#define DRA722_REV_ES2_0 (DRA7XX_CLASS | (0x22 << 16) | (0x20 << 8))
#define DRA722_REV_ES2_1 (DRA7XX_CLASS | (0x22 << 16) | (0x21 << 8))
-void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);
void omap4xxx_check_revision(void);
void omap5xxx_check_revision(void);
@@ -484,12 +431,6 @@ level(__##fn);
#define omap_late_initcall_sync(fn) omap_initcall(late_initcall_sync, fn)
/* Legacy defines, these can be removed when users are removed */
-#define cpu_is_omap2420() soc_is_omap2420()
-#define cpu_is_omap2422() soc_is_omap2422()
-#define cpu_is_omap242x() soc_is_omap242x()
-#define cpu_is_omap2430() soc_is_omap2430()
-#define cpu_is_omap243x() soc_is_omap243x()
-#define cpu_is_omap24xx() soc_is_omap24xx()
#define cpu_is_omap3430() soc_is_omap3430()
#define cpu_is_omap343x() soc_is_omap343x()
#define cpu_is_omap34xx() soc_is_omap34xx()
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 898b011ae8d9..8f980849f201 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -28,15 +28,10 @@
#include "sdrc.h"
#include "sram.h"
-#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
#define SRAM_BOOTLOADER_SZ 0x00
-#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
-#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
-#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
-
#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
@@ -120,18 +115,11 @@ static int is_sram_locked(void)
{
if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
/* RAMFW: R/W access to all initiators for all qualifier sets */
- if (cpu_is_omap242x()) {
- writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
- writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
- writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
- }
- if (cpu_is_omap34xx()) {
- writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
- writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
- writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
- writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
- writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
- }
+ writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
+ writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
+ writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
+ writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
+ writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
return 0;
} else
return 1; /* assume locked with no PPA or security driver */
@@ -147,30 +135,17 @@ static void __init omap_detect_sram(void)
{
omap_sram_skip = SRAM_BOOTLOADER_SZ;
if (is_sram_locked()) {
- if (cpu_is_omap34xx()) {
- omap_sram_start = OMAP3_SRAM_PUB_PA;
- if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
- (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
- omap_sram_size = 0x7000; /* 28K */
- omap_sram_skip += SZ_16K;
- } else {
- omap_sram_size = 0x8000; /* 32K */
- }
+ omap_sram_start = OMAP3_SRAM_PUB_PA;
+ if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
+ (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
+ omap_sram_size = 0x7000; /* 28K */
+ omap_sram_skip += SZ_16K;
} else {
- omap_sram_start = OMAP2_SRAM_PUB_PA;
- omap_sram_size = 0x800; /* 2K */
+ omap_sram_size = 0x8000; /* 32K */
}
} else {
- if (cpu_is_omap34xx()) {
- omap_sram_start = OMAP3_SRAM_PA;
- omap_sram_size = 0x10000; /* 64K */
- } else {
- omap_sram_start = OMAP2_SRAM_PA;
- if (cpu_is_omap242x())
- omap_sram_size = 0xa0000; /* 640K */
- else if (cpu_is_omap243x())
- omap_sram_size = 0x10000; /* 64K */
- }
+ omap_sram_start = OMAP3_SRAM_PA;
+ omap_sram_size = 0x10000; /* 64K */
}
}
@@ -181,24 +156,20 @@ static void __init omap2_map_sram(void)
{
unsigned long base;
int pages;
- int cached = 1;
-
- if (cpu_is_omap34xx()) {
- /*
- * SRAM must be marked as non-cached on OMAP3 since the
- * CORE DPLL M2 divider change code (in SRAM) runs with the
- * SDRAM controller disabled, and if it is marked cached,
- * the ARM may attempt to write cache lines back to SDRAM
- * which will cause the system to hang.
- */
- cached = 0;
- }
if (omap_sram_size == 0)
return;
omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
- omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, cached);
+ /*
+ * SRAM must be marked as non-cached on OMAP3 since the
+ * CORE DPLL M2 divider change code (in SRAM) runs with the
+ * SDRAM controller disabled, and if it is marked cached,
+ * the ARM may attempt to write cache lines back to SDRAM
+ * which will cause the system to hang.
+ */
+
+ omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, 0);
if (!omap_sram_base) {
pr_err("SRAM: Could not map\n");
return;
@@ -219,78 +190,6 @@ static void __init omap2_map_sram(void)
set_memory_rox(base, pages);
}
-static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock);
-
-void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock)
-{
- BUG_ON(!_omap2_sram_ddr_init);
- _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
- base_cs, force_unlock);
-}
-
-static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
- u32 mem_type);
-
-void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
-{
- BUG_ON(!_omap2_sram_reprogram_sdrc);
- _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
-}
-
-static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-
-u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
-{
- BUG_ON(!_omap2_set_prcm);
- return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
-}
-
-#ifdef CONFIG_SOC_OMAP2420
-static int __init omap242x_sram_init(void)
-{
- _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
- omap242x_sram_ddr_init_sz);
-
- _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
- omap242x_sram_reprogram_sdrc_sz);
-
- _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
- omap242x_sram_set_prcm_sz);
-
- return 0;
-}
-#else
-static inline int omap242x_sram_init(void)
-{
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-static int __init omap243x_sram_init(void)
-{
- _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
- omap243x_sram_ddr_init_sz);
-
- _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
- omap243x_sram_reprogram_sdrc_sz);
-
- _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
- omap243x_sram_set_prcm_sz);
-
- return 0;
-}
-#else
-static inline int omap243x_sram_init(void)
-{
- return 0;
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-
void omap3_sram_restore_context(void)
{
omap_sram_reset();
@@ -303,24 +202,12 @@ static inline int omap34xx_sram_init(void)
omap3_sram_restore_context();
return 0;
}
-#else
-static inline int omap34xx_sram_init(void)
-{
- return 0;
-}
-#endif /* CONFIG_ARCH_OMAP3 */
int __init omap_sram_init(void)
{
omap_detect_sram();
omap2_map_sram();
-
- if (cpu_is_omap242x())
- omap242x_sram_init();
- else if (cpu_is_omap2430())
- omap243x_sram_init();
- else if (cpu_is_omap34xx())
- omap34xx_sram_init();
+ omap34xx_sram_init();
return 0;
}
diff --git a/arch/arm/mach-omap2/sram.h b/arch/arm/mach-omap2/sram.h
index 030cabc39821..2db2c4598cdb 100644
--- a/arch/arm/mach-omap2/sram.h
+++ b/arch/arm/mach-omap2/sram.h
@@ -5,43 +5,12 @@
#ifndef __ASSEMBLY__
-extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock);
-extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
- u32 mem_type);
-extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-
extern void omap3_sram_restore_context(void);
extern int __init omap_sram_init(void);
extern void *omap_sram_push(void *funcp, unsigned long size);
-extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock);
-extern unsigned long omap242x_sram_ddr_init_sz;
-
-extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
- int bypass);
-extern unsigned long omap242x_sram_set_prcm_sz;
-
-extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
- u32 mem_type);
-extern unsigned long omap242x_sram_reprogram_sdrc_sz;
-
-
-extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock);
-extern unsigned long omap243x_sram_ddr_init_sz;
-
-extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
- int bypass);
-extern unsigned long omap243x_sram_set_prcm_sz;
-
-extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
- u32 mem_type);
-extern unsigned long omap243x_sram_reprogram_sdrc_sz;
-
#ifdef CONFIG_PM
extern void omap_push_sram_idle(void);
#else
@@ -54,5 +23,4 @@ static inline void omap_push_sram_idle(void) {}
* OMAP2+: define the SRAM PA addresses.
* Used by the SRAM management code and the idle sleep code.
*/
-#define OMAP2_SRAM_PA 0x40200000
#define OMAP3_SRAM_PA 0x40200000
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
deleted file mode 100644
index 92ef21ac2ac1..000000000000
--- a/arch/arm/mach-omap2/sram242x.S
+++ /dev/null
@@ -1,317 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * linux/arch/arm/mach-omap2/sram242x.S
- *
- * Omap2 specific functions that need to be run in internal SRAM
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * Richard Woodruff notes that any changes to this code must be carefully
- * audited and tested to ensure that they don't cause a TLB miss while
- * the SDRAM is inaccessible. Such a situation will crash the system
- * since it will cause the ARM MMU to attempt to walk the page tables.
- * These crashes may be intermittent.
- */
-#include <linux/linkage.h>
-
-#include <asm/assembler.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "prm2xxx.h"
-#include "cm2xxx.h"
-#include "sdrc.h"
-
- .text
-
- .align 3
-ENTRY(omap242x_sram_ddr_init)
- stmfd sp!, {r0 - r12, lr} @ save registers on stack
-
- mov r12, r2 @ capture CS1 vs CS0
- mov r8, r3 @ capture force parameter
-
- /* frequency shift down */
- ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
- mov r3, #0x1 @ value for 1x operation
- str r3, [r2] @ go to L1-freq operation
-
- /* voltage shift down */
- mov r9, #0x1 @ set up for L1 voltage call
- bl voltage_shift @ go drop voltage
-
- /* dll lock mode */
- ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
- ldr r10, [r11] @ get current val
- cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
- addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
- mvn r9, #0x4 @ mask to get clear bit2
- and r10, r10, r9 @ clear bit2 for lock mode.
- orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
- orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
- str r10, [r11] @ commit to DLLA_CTRL
- bl i_dll_wait @ wait for dll to lock
-
- /* get dll value */
- add r11, r11, #0x4 @ get addr of status reg
- ldr r10, [r11] @ get locked value
-
- /* voltage shift up */
- mov r9, #0x0 @ shift back to L0-voltage
- bl voltage_shift @ go raise voltage
-
- /* frequency shift up */
- mov r3, #0x2 @ value for 2x operation
- str r3, [r2] @ go to L0-freq operation
-
- /* reset entry mode for dllctrl */
- sub r11, r11, #0x4 @ move from status to ctrl
- cmp r12, #0x1 @ normalize if cs1 based
- subeq r11, r11, #0x8 @ possibly back to DLLA
- cmp r8, #0x1 @ if forced unlock exit
- orreq r1, r1, #0x4 @ make sure exit with unlocked value
- str r1, [r11] @ restore DLLA_CTRL high value
- add r11, r11, #0x8 @ move to DLLB_CTRL addr
- str r1, [r11] @ set value DLLB_CTRL
- bl i_dll_wait @ wait for possible lock
-
- /* set up for return, DDR should be good */
- str r10, [r0] @ write dll_status and return counter
- ldmfd sp!, {r0 - r12, pc} @ restore regs and return
-
- /* ensure the DLL has relocked */
-i_dll_wait:
- mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
-i_dll_delay:
- subs r4, r4, #0x1
- bne i_dll_delay
- ret lr
-
- /*
- * shift up or down voltage, use R9 as input to tell level.
- * wait for it to finish, use 32k sync counter, 1tick=31uS.
- */
-voltage_shift:
- ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl.
- ldr r5, [r4] @ get value.
- ldr r6, prcm_mask_val @ get value of mask
- and r5, r5, r6 @ apply mask to clear bits
- orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
- str r5, [r4] @ set up for change.
- mov r3, #0x4000 @ get val for force
- orr r5, r5, r3 @ build value for force
- str r5, [r4] @ Force transition to L1
-
- ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter
- ldr r5, [r3] @ get value
- add r5, r5, #0x3 @ give it at most 93uS
-volt_delay:
- ldr r7, [r3] @ get timer value
- cmp r5, r7 @ time up?
- bhi volt_delay @ not yet->branch
- ret lr @ back to caller.
-
-omap242x_sdi_cm_clksel2_pll:
- .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-omap242x_sdi_sdrc_dlla_ctrl:
- .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-omap242x_sdi_prcm_voltctrl:
- .word OMAP2420_PRCM_VOLTCTRL
-prcm_mask_val:
- .word 0xFFFF3FFC
-omap242x_sdi_timer_32ksynct_cr:
- .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
-ENTRY(omap242x_sram_ddr_init_sz)
- .word . - omap242x_sram_ddr_init
-
-/*
- * Reprograms memory timings.
- * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
- * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
- */
- .align 3
-ENTRY(omap242x_sram_reprogram_sdrc)
- stmfd sp!, {r0 - r10, lr} @ save registers on stack
- mov r3, #0x0 @ clear for mrc call
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
- nop
- nop
- ldr r6, omap242x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
- ldr r5, [r6] @ get value
- mov r5, r5, lsr #8 @ isolate rfr field and drop burst
-
- cmp r0, #0x1 @ going to half speed?
- movne r9, #0x0 @ if up set flag up for pre up, hi volt
-
- blne voltage_shift_c @ adjust voltage
-
- cmp r0, #0x1 @ going to half speed (post branch link)
- moveq r5, r5, lsr #1 @ divide by 2 if to half
- movne r5, r5, lsl #1 @ mult by 2 if to full
- mov r5, r5, lsl #8 @ put rfr field back into place
- add r5, r5, #0x1 @ turn on burst of 1
- ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
- ldr r3, [r4] @ get curr value
- orr r3, r3, #0x3
- bic r3, r3, #0x3 @ clear lower bits
- orr r3, r3, r0 @ new state value
- str r3, [r4] @ set new state (pll/x, x=1 or 2)
- nop
- nop
-
- moveq r9, #0x1 @ if speed down, post down, drop volt
- bleq voltage_shift_c
-
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier
- str r5, [r6] @ set new RFR_1 value
- add r6, r6, #0x30 @ get RFR_2 addr
- str r5, [r6] @ set RFR_2
- nop
- cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
- bne freq_out @ leave if SDR, no DLL function
-
- /* With DDR, we need to take care of the DLL for the frequency change */
- ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
- str r1, [r2] @ write out new SDRC_DLLA_CTRL
- add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
- str r1, [r2] @ commit to SDRC_DLLB_CTRL
- mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
-dll_wait:
- subs r1, r1, #0x1
- bne dll_wait
-freq_out:
- ldmfd sp!, {r0 - r10, pc} @ restore regs and return
-
- /*
- * shift up or down voltage, use R9 as input to tell level.
- * wait for it to finish, use 32k sync counter, 1tick=31uS.
- */
-voltage_shift_c:
- ldr r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
- ldr r8, [r10] @ get value
- ldr r7, ddr_prcm_mask_val @ get value of mask
- and r8, r8, r7 @ apply mask to clear bits
- orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
- str r8, [r10] @ set up for change.
- mov r7, #0x4000 @ get val for force
- orr r8, r8, r7 @ build value for force
- str r8, [r10] @ Force transition to L1
-
- ldr r10, omap242x_srs_timer_32ksynct @ get addr of counter
- ldr r8, [r10] @ get value
- add r8, r8, #0x2 @ give it at most 62uS (min 31+)
-volt_delay_c:
- ldr r7, [r10] @ get timer value
- cmp r8, r7 @ time up?
- bhi volt_delay_c @ not yet->branch
- ret lr @ back to caller
-
-omap242x_srs_cm_clksel2_pll:
- .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-omap242x_srs_sdrc_dlla_ctrl:
- .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-omap242x_srs_sdrc_rfr_ctrl:
- .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap242x_srs_prcm_voltctrl:
- .word OMAP2420_PRCM_VOLTCTRL
-ddr_prcm_mask_val:
- .word 0xFFFF3FFC
-omap242x_srs_timer_32ksynct:
- .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
-
-ENTRY(omap242x_sram_reprogram_sdrc_sz)
- .word . - omap242x_sram_reprogram_sdrc
-
-/*
- * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
- */
- .align 3
-ENTRY(omap242x_sram_set_prcm)
- stmfd sp!, {r0-r12, lr} @ regs to stack
- adr r4, pbegin @ addr of preload start
- adr r8, pend @ addr of preload end
- mcrr p15, 1, r8, r4, c12 @ preload into icache
-pbegin:
- /* move into fast relock bypass */
- ldr r8, omap242x_ssp_pll_ctl @ get addr
- ldr r5, [r8] @ get val
- mvn r6, #0x3 @ clear mask
- and r5, r5, r6 @ clear field
- orr r7, r5, #0x2 @ fast relock val
- str r7, [r8] @ go to fast relock
- ldr r4, omap242x_ssp_pll_stat @ addr of stat
-block:
- /* wait for bypass */
- ldr r8, [r4] @ stat value
- and r8, r8, #0x3 @ mask for stat
- cmp r8, #0x1 @ there yet
- bne block @ loop if not
-
- /* set new dpll dividers _after_ in bypass */
- ldr r4, omap242x_ssp_pll_div @ get addr
- str r0, [r4] @ set dpll ctrl val
-
- ldr r4, omap242x_ssp_set_config @ get addr
- mov r8, #1 @ valid cfg msk
- str r8, [r4] @ make dividers take
-
- mov r4, #100 @ dead spin a bit
-wait_a_bit:
- subs r4, r4, #1 @ dec loop
- bne wait_a_bit @ delay done?
-
- /* check if staying in bypass */
- cmp r2, #0x1 @ stay in bypass?
- beq pend @ jump over dpll relock
-
- /* relock DPLL with new vals */
- ldr r5, omap242x_ssp_pll_stat @ get addr
- ldr r4, omap242x_ssp_pll_ctl @ get addr
- orr r8, r7, #0x3 @ val for lock dpll
- str r8, [r4] @ set val
- mov r0, #1000 @ dead spin a bit
-wait_more:
- subs r0, r0, #1 @ dec loop
- bne wait_more @ delay done?
-wait_lock:
- ldr r8, [r5] @ get lock val
- and r8, r8, #3 @ isolate field
- cmp r8, #2 @ locked?
- bne wait_lock @ wait if not
-pend:
- /* update memory timings & briefly lock dll */
- ldr r4, omap242x_ssp_sdrc_rfr @ get addr
- str r1, [r4] @ update refresh timing
- ldr r11, omap242x_ssp_dlla_ctrl @ get addr of DLLA ctrl
- ldr r10, [r11] @ get current val
- mvn r9, #0x4 @ mask to get clear bit2
- and r10, r10, r9 @ clear bit2 for lock mode
- orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
- str r10, [r11] @ commit to DLLA_CTRL
- add r11, r11, #0x8 @ move to dllb
- str r10, [r11] @ hit DLLB also
-
- mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
-wait_dll_lock:
- subs r4, r4, #0x1
- bne wait_dll_lock
- nop
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
-
-omap242x_ssp_set_config:
- .word OMAP2420_PRCM_CLKCFG_CTRL
-omap242x_ssp_pll_ctl:
- .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
-omap242x_ssp_pll_stat:
- .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
-omap242x_ssp_pll_div:
- .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
-omap242x_ssp_sdrc_rfr:
- .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap242x_ssp_dlla_ctrl:
- .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-
-ENTRY(omap242x_sram_set_prcm_sz)
- .word . - omap242x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
deleted file mode 100644
index faf03b7f08f5..000000000000
--- a/arch/arm/mach-omap2/sram243x.S
+++ /dev/null
@@ -1,317 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * linux/arch/arm/mach-omap2/sram243x.S
- *
- * Omap2 specific functions that need to be run in internal SRAM
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * Richard Woodruff notes that any changes to this code must be carefully
- * audited and tested to ensure that they don't cause a TLB miss while
- * the SDRAM is inaccessible. Such a situation will crash the system
- * since it will cause the ARM MMU to attempt to walk the page tables.
- * These crashes may be intermittent.
- */
-#include <linux/linkage.h>
-
-#include <asm/assembler.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "prm2xxx.h"
-#include "cm2xxx.h"
-#include "sdrc.h"
-
- .text
-
- .align 3
-ENTRY(omap243x_sram_ddr_init)
- stmfd sp!, {r0 - r12, lr} @ save registers on stack
-
- mov r12, r2 @ capture CS1 vs CS0
- mov r8, r3 @ capture force parameter
-
- /* frequency shift down */
- ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
- mov r3, #0x1 @ value for 1x operation
- str r3, [r2] @ go to L1-freq operation
-
- /* voltage shift down */
- mov r9, #0x1 @ set up for L1 voltage call
- bl voltage_shift @ go drop voltage
-
- /* dll lock mode */
- ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
- ldr r10, [r11] @ get current val
- cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
- addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
- mvn r9, #0x4 @ mask to get clear bit2
- and r10, r10, r9 @ clear bit2 for lock mode.
- orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
- orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
- str r10, [r11] @ commit to DLLA_CTRL
- bl i_dll_wait @ wait for dll to lock
-
- /* get dll value */
- add r11, r11, #0x4 @ get addr of status reg
- ldr r10, [r11] @ get locked value
-
- /* voltage shift up */
- mov r9, #0x0 @ shift back to L0-voltage
- bl voltage_shift @ go raise voltage
-
- /* frequency shift up */
- mov r3, #0x2 @ value for 2x operation
- str r3, [r2] @ go to L0-freq operation
-
- /* reset entry mode for dllctrl */
- sub r11, r11, #0x4 @ move from status to ctrl
- cmp r12, #0x1 @ normalize if cs1 based
- subeq r11, r11, #0x8 @ possibly back to DLLA
- cmp r8, #0x1 @ if forced unlock exit
- orreq r1, r1, #0x4 @ make sure exit with unlocked value
- str r1, [r11] @ restore DLLA_CTRL high value
- add r11, r11, #0x8 @ move to DLLB_CTRL addr
- str r1, [r11] @ set value DLLB_CTRL
- bl i_dll_wait @ wait for possible lock
-
- /* set up for return, DDR should be good */
- str r10, [r0] @ write dll_status and return counter
- ldmfd sp!, {r0 - r12, pc} @ restore regs and return
-
- /* ensure the DLL has relocked */
-i_dll_wait:
- mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
-i_dll_delay:
- subs r4, r4, #0x1
- bne i_dll_delay
- ret lr
-
- /*
- * shift up or down voltage, use R9 as input to tell level.
- * wait for it to finish, use 32k sync counter, 1tick=31uS.
- */
-voltage_shift:
- ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
- ldr r5, [r4] @ get value.
- ldr r6, prcm_mask_val @ get value of mask
- and r5, r5, r6 @ apply mask to clear bits
- orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
- str r5, [r4] @ set up for change.
- mov r3, #0x4000 @ get val for force
- orr r5, r5, r3 @ build value for force
- str r5, [r4] @ Force transition to L1
-
- ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter
- ldr r5, [r3] @ get value
- add r5, r5, #0x3 @ give it at most 93uS
-volt_delay:
- ldr r7, [r3] @ get timer value
- cmp r5, r7 @ time up?
- bhi volt_delay @ not yet->branch
- ret lr @ back to caller.
-
-omap243x_sdi_cm_clksel2_pll:
- .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-omap243x_sdi_sdrc_dlla_ctrl:
- .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-omap243x_sdi_prcm_voltctrl:
- .word OMAP2430_PRCM_VOLTCTRL
-prcm_mask_val:
- .word 0xFFFF3FFC
-omap243x_sdi_timer_32ksynct_cr:
- .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
-ENTRY(omap243x_sram_ddr_init_sz)
- .word . - omap243x_sram_ddr_init
-
-/*
- * Reprograms memory timings.
- * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
- * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
- */
- .align 3
-ENTRY(omap243x_sram_reprogram_sdrc)
- stmfd sp!, {r0 - r10, lr} @ save registers on stack
- mov r3, #0x0 @ clear for mrc call
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
- nop
- nop
- ldr r6, omap243x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
- ldr r5, [r6] @ get value
- mov r5, r5, lsr #8 @ isolate rfr field and drop burst
-
- cmp r0, #0x1 @ going to half speed?
- movne r9, #0x0 @ if up set flag up for pre up, hi volt
-
- blne voltage_shift_c @ adjust voltage
-
- cmp r0, #0x1 @ going to half speed (post branch link)
- moveq r5, r5, lsr #1 @ divide by 2 if to half
- movne r5, r5, lsl #1 @ mult by 2 if to full
- mov r5, r5, lsl #8 @ put rfr field back into place
- add r5, r5, #0x1 @ turn on burst of 1
- ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
- ldr r3, [r4] @ get curr value
- orr r3, r3, #0x3
- bic r3, r3, #0x3 @ clear lower bits
- orr r3, r3, r0 @ new state value
- str r3, [r4] @ set new state (pll/x, x=1 or 2)
- nop
- nop
-
- moveq r9, #0x1 @ if speed down, post down, drop volt
- bleq voltage_shift_c
-
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier
- str r5, [r6] @ set new RFR_1 value
- add r6, r6, #0x30 @ get RFR_2 addr
- str r5, [r6] @ set RFR_2
- nop
- cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
- bne freq_out @ leave if SDR, no DLL function
-
- /* With DDR, we need to take care of the DLL for the frequency change */
- ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
- str r1, [r2] @ write out new SDRC_DLLA_CTRL
- add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
- str r1, [r2] @ commit to SDRC_DLLB_CTRL
- mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
-dll_wait:
- subs r1, r1, #0x1
- bne dll_wait
-freq_out:
- ldmfd sp!, {r0 - r10, pc} @ restore regs and return
-
- /*
- * shift up or down voltage, use R9 as input to tell level.
- * wait for it to finish, use 32k sync counter, 1tick=31uS.
- */
-voltage_shift_c:
- ldr r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
- ldr r8, [r10] @ get value
- ldr r7, ddr_prcm_mask_val @ get value of mask
- and r8, r8, r7 @ apply mask to clear bits
- orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
- str r8, [r10] @ set up for change.
- mov r7, #0x4000 @ get val for force
- orr r8, r8, r7 @ build value for force
- str r8, [r10] @ Force transition to L1
-
- ldr r10, omap243x_srs_timer_32ksynct @ get addr of counter
- ldr r8, [r10] @ get value
- add r8, r8, #0x2 @ give it at most 62uS (min 31+)
-volt_delay_c:
- ldr r7, [r10] @ get timer value
- cmp r8, r7 @ time up?
- bhi volt_delay_c @ not yet->branch
- ret lr @ back to caller
-
-omap243x_srs_cm_clksel2_pll:
- .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-omap243x_srs_sdrc_dlla_ctrl:
- .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-omap243x_srs_sdrc_rfr_ctrl:
- .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap243x_srs_prcm_voltctrl:
- .word OMAP2430_PRCM_VOLTCTRL
-ddr_prcm_mask_val:
- .word 0xFFFF3FFC
-omap243x_srs_timer_32ksynct:
- .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
-
-ENTRY(omap243x_sram_reprogram_sdrc_sz)
- .word . - omap243x_sram_reprogram_sdrc
-
-/*
- * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
- */
- .align 3
-ENTRY(omap243x_sram_set_prcm)
- stmfd sp!, {r0-r12, lr} @ regs to stack
- adr r4, pbegin @ addr of preload start
- adr r8, pend @ addr of preload end
- mcrr p15, 1, r8, r4, c12 @ preload into icache
-pbegin:
- /* move into fast relock bypass */
- ldr r8, omap243x_ssp_pll_ctl @ get addr
- ldr r5, [r8] @ get val
- mvn r6, #0x3 @ clear mask
- and r5, r5, r6 @ clear field
- orr r7, r5, #0x2 @ fast relock val
- str r7, [r8] @ go to fast relock
- ldr r4, omap243x_ssp_pll_stat @ addr of stat
-block:
- /* wait for bypass */
- ldr r8, [r4] @ stat value
- and r8, r8, #0x3 @ mask for stat
- cmp r8, #0x1 @ there yet
- bne block @ loop if not
-
- /* set new dpll dividers _after_ in bypass */
- ldr r4, omap243x_ssp_pll_div @ get addr
- str r0, [r4] @ set dpll ctrl val
-
- ldr r4, omap243x_ssp_set_config @ get addr
- mov r8, #1 @ valid cfg msk
- str r8, [r4] @ make dividers take
-
- mov r4, #100 @ dead spin a bit
-wait_a_bit:
- subs r4, r4, #1 @ dec loop
- bne wait_a_bit @ delay done?
-
- /* check if staying in bypass */
- cmp r2, #0x1 @ stay in bypass?
- beq pend @ jump over dpll relock
-
- /* relock DPLL with new vals */
- ldr r5, omap243x_ssp_pll_stat @ get addr
- ldr r4, omap243x_ssp_pll_ctl @ get addr
- orr r8, r7, #0x3 @ val for lock dpll
- str r8, [r4] @ set val
- mov r0, #1000 @ dead spin a bit
-wait_more:
- subs r0, r0, #1 @ dec loop
- bne wait_more @ delay done?
-wait_lock:
- ldr r8, [r5] @ get lock val
- and r8, r8, #3 @ isolate field
- cmp r8, #2 @ locked?
- bne wait_lock @ wait if not
-pend:
- /* update memory timings & briefly lock dll */
- ldr r4, omap243x_ssp_sdrc_rfr @ get addr
- str r1, [r4] @ update refresh timing
- ldr r11, omap243x_ssp_dlla_ctrl @ get addr of DLLA ctrl
- ldr r10, [r11] @ get current val
- mvn r9, #0x4 @ mask to get clear bit2
- and r10, r10, r9 @ clear bit2 for lock mode
- orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
- str r10, [r11] @ commit to DLLA_CTRL
- add r11, r11, #0x8 @ move to dllb
- str r10, [r11] @ hit DLLB also
-
- mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
-wait_dll_lock:
- subs r4, r4, #0x1
- bne wait_dll_lock
- nop
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
-
-omap243x_ssp_set_config:
- .word OMAP2430_PRCM_CLKCFG_CTRL
-omap243x_ssp_pll_ctl:
- .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
-omap243x_ssp_pll_stat:
- .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
-omap243x_ssp_pll_div:
- .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
-omap243x_ssp_sdrc_rfr:
- .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap243x_ssp_dlla_ctrl:
- .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-
-ENTRY(omap243x_sram_set_prcm_sz)
- .word . - omap243x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
deleted file mode 100644
index b46c254c2bc4..000000000000
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap2/usb-tusb6010.c
- *
- * Copyright (C) 2006 Nokia Corporation
- */
-
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/export.h>
-#include <linux/platform_data/usb-omap.h>
-
-#include <linux/usb/musb.h>
-
-#include "usb-tusb6010.h"
-#include "gpmc.h"
-
-static u8 async_cs, sync_cs;
-static unsigned refclk_psec;
-
-static struct gpmc_settings tusb_async = {
- .wait_on_read = true,
- .wait_on_write = true,
- .device_width = GPMC_DEVWIDTH_16BIT,
- .mux_add_data = GPMC_MUX_AD,
-};
-
-static struct gpmc_settings tusb_sync = {
- .burst_read = true,
- .burst_write = true,
- .sync_read = true,
- .sync_write = true,
- .wait_on_read = true,
- .wait_on_write = true,
- .burst_len = GPMC_BURST_16,
- .device_width = GPMC_DEVWIDTH_16BIT,
- .mux_add_data = GPMC_MUX_AD,
-};
-
-/* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
-
-static int tusb_set_async_mode(unsigned sysclk_ps)
-{
- struct gpmc_device_timings dev_t;
- struct gpmc_timings t;
- unsigned t_acsnh_advnh = sysclk_ps + 3000;
-
- memset(&dev_t, 0, sizeof(dev_t));
-
- dev_t.t_ceasu = 8 * 1000;
- dev_t.t_avdasu = t_acsnh_advnh - 7000;
- dev_t.t_ce_avd = 1000;
- dev_t.t_avdp_r = t_acsnh_advnh;
- dev_t.t_oeasu = t_acsnh_advnh + 1000;
- dev_t.t_oe = 300;
- dev_t.t_cez_r = 7000;
- dev_t.t_cez_w = dev_t.t_cez_r;
- dev_t.t_avdp_w = t_acsnh_advnh;
- dev_t.t_weasu = t_acsnh_advnh + 1000;
- dev_t.t_wpl = 300;
- dev_t.cyc_aavdh_we = 1;
-
- gpmc_calc_timings(&t, &tusb_async, &dev_t);
-
- return gpmc_cs_set_timings(async_cs, &t, &tusb_async);
-}
-
-static int tusb_set_sync_mode(unsigned sysclk_ps)
-{
- struct gpmc_device_timings dev_t;
- struct gpmc_timings t;
- unsigned t_scsnh_advnh = sysclk_ps + 3000;
-
- memset(&dev_t, 0, sizeof(dev_t));
-
- dev_t.clk = 11100;
- dev_t.t_bacc = 1000;
- dev_t.t_ces = 1000;
- dev_t.t_ceasu = 8 * 1000;
- dev_t.t_avdasu = t_scsnh_advnh - 7000;
- dev_t.t_ce_avd = 1000;
- dev_t.t_avdp_r = t_scsnh_advnh;
- dev_t.cyc_aavdh_oe = 3;
- dev_t.cyc_oe = 5;
- dev_t.t_ce_rdyz = 7000;
- dev_t.t_avdp_w = t_scsnh_advnh;
- dev_t.cyc_aavdh_we = 3;
- dev_t.cyc_wpl = 6;
-
- gpmc_calc_timings(&t, &tusb_sync, &dev_t);
-
- return gpmc_cs_set_timings(sync_cs, &t, &tusb_sync);
-}
-
-/* tusb driver calls this when it changes the chip's clocking */
-static int tusb6010_platform_retime(unsigned is_refclk)
-{
- static const char error[] =
- KERN_ERR "tusb6010 %s retime error %d\n";
-
- unsigned sysclk_ps;
- int status;
-
- if (!refclk_psec)
- return -ENODEV;
-
- sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60;
-
- status = tusb_set_async_mode(sysclk_ps);
- if (status < 0) {
- printk(error, "async", status);
- goto done;
- }
- status = tusb_set_sync_mode(sysclk_ps);
- if (status < 0)
- printk(error, "sync", status);
-done:
- return status;
-}
-
-static struct resource tusb_resources[] = {
- /* Order is significant! The start/end fields
- * are updated during setup..
- */
- { /* Asynchronous access */
- .flags = IORESOURCE_MEM,
- },
- { /* Synchronous access */
- .flags = IORESOURCE_MEM,
- },
-};
-
-static u64 tusb_dmamask = ~(u32)0;
-
-static struct platform_device tusb_device = {
- .name = "musb-tusb",
- .id = -1,
- .dev = {
- .dma_mask = &tusb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(tusb_resources),
- .resource = tusb_resources,
-};
-
-
-/* this may be called only from board-*.c setup code */
-int __init tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
- unsigned int ps_refclk, unsigned int waitpin,
- unsigned int async, unsigned int sync,
- unsigned int dmachan)
-{
- int status;
- static char error[] __initdata =
- KERN_ERR "tusb6010 init error %d, %d\n";
-
- /* ASYNC region, primarily for PIO */
- status = gpmc_cs_request(async, SZ_16M, (unsigned long *)
- &tusb_resources[0].start);
- if (status < 0) {
- printk(error, 1, status);
- return status;
- }
- tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
- tusb_async.wait_pin = waitpin;
- async_cs = async;
-
- status = gpmc_cs_program_settings(async_cs, &tusb_async);
- if (status < 0)
- return status;
-
- /* SYNC region, primarily for DMA */
- status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
- &tusb_resources[1].start);
- if (status < 0) {
- printk(error, 2, status);
- return status;
- }
- tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
- tusb_sync.wait_pin = waitpin;
- sync_cs = sync;
-
- status = gpmc_cs_program_settings(sync_cs, &tusb_sync);
- if (status < 0)
- return status;
-
- /* set up memory timings ... can speed them up later */
- if (!ps_refclk) {
- printk(error, 4, status);
- return -ENODEV;
- }
- refclk_psec = ps_refclk;
- status = tusb6010_platform_retime(1);
- if (status < 0) {
- printk(error, 5, status);
- return status;
- }
-
- /* finish device setup ... */
- if (!data) {
- printk(error, 6, status);
- return -ENODEV;
- }
- tusb_device.dev.platform_data = data;
-
- /* so far so good ... register the device */
- status = platform_device_register(&tusb_device);
- if (status < 0) {
- printk(error, 7, status);
- return status;
- }
- return 0;
-}
diff --git a/arch/arm/mach-omap2/usb-tusb6010.h b/arch/arm/mach-omap2/usb-tusb6010.h
deleted file mode 100644
index d210ff6238c2..000000000000
--- a/arch/arm/mach-omap2/usb-tusb6010.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef __USB_TUSB6010_H
-#define __USB_TUSB6010_H
-
-extern int __init tusb6010_setup_interface(
- struct musb_hdrc_platform_data *data,
- unsigned int ps_refclk, unsigned int waitpin,
- unsigned int async_cs, unsigned int sync_cs,
- unsigned int dmachan);
-
-#endif /* __USB_TUSB6010_H */
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index e610f63a020d..cbac3f151900 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -156,7 +156,6 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
struct omap_voltdm_pmic *pmic);
int omap_voltage_late_init(void);
-extern void omap2xxx_voltagedomains_init(void);
extern void omap3xxx_voltagedomains_init(void);
extern void omap44xx_voltagedomains_init(void);
extern void omap54xx_voltagedomains_init(void);
diff --git a/arch/arm/mach-omap2/voltagedomains2xxx_data.c b/arch/arm/mach-omap2/voltagedomains2xxx_data.c
deleted file mode 100644
index 9bc116fe3ba9..000000000000
--- a/arch/arm/mach-omap2/voltagedomains2xxx_data.c
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP3 voltage domain data
- *
- * Copyright (C) 2011 Texas Instruments, Inc.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include "voltage.h"
-
-static struct voltagedomain omap2_voltdm_core = {
- .name = "core",
-};
-
-static struct voltagedomain omap2_voltdm_wkup = {
- .name = "wakeup",
-};
-
-static struct voltagedomain *voltagedomains_omap2[] __initdata = {
- &omap2_voltdm_core,
- &omap2_voltdm_wkup,
- NULL,
-};
-
-void __init omap2xxx_voltagedomains_init(void)
-{
- voltdm_init(voltagedomains_omap2);
-}
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 0189dfdcbbe1..a383ff8f446c 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -337,7 +337,7 @@ config CRYPTO_DEV_OMAP_SHAM
config CRYPTO_DEV_OMAP_AES
tristate "Support for OMAP AES hw engine"
- depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP2PLUS
+ depends on ARCH_OMAP3 || ARCH_OMAP2PLUS
select CRYPTO_AES
select CRYPTO_SKCIPHER
select CRYPTO_ENGINE
diff --git a/drivers/media/platform/ti/omap/Kconfig b/drivers/media/platform/ti/omap/Kconfig
index a9dbe1097775..c41812b324ad 100644
--- a/drivers/media/platform/ti/omap/Kconfig
+++ b/drivers/media/platform/ti/omap/Kconfig
@@ -9,9 +9,9 @@ config VIDEO_OMAP2_VOUT
depends on V4L_PLATFORM_DRIVERS
depends on MMU
depends on FB_OMAP2 || (COMPILE_TEST && FB_OMAP2=n)
- depends on ARCH_OMAP2 || ARCH_OMAP3 || COMPILE_TEST
+ depends on ARCH_OMAP3 || COMPILE_TEST
depends on VIDEO_DEV
select VIDEOBUF2_DMA_CONTIG
- select OMAP2_VRFB if ARCH_OMAP2 || ARCH_OMAP3
+ select OMAP2_VRFB if ARCH_OMAP3
help
V4L2 Display driver support for OMAP2/3 based boards.
diff --git a/drivers/mtd/nand/onenand/Kconfig b/drivers/mtd/nand/onenand/Kconfig
index 7d57836bf32f..8a362fd5bfc4 100644
--- a/drivers/mtd/nand/onenand/Kconfig
+++ b/drivers/mtd/nand/onenand/Kconfig
@@ -23,8 +23,8 @@ config MTD_ONENAND_GENERIC
Support for OneNAND flash via platform device driver.
config MTD_ONENAND_OMAP2
- tristate "OneNAND on OMAP2/OMAP3 support"
- depends on ARCH_OMAP2 || ARCH_OMAP3 || (COMPILE_TEST && ARM)
+ tristate "OneNAND on OMAP3 support"
+ depends on ARCH_OMAP3 || (COMPILE_TEST && ARM)
depends on OF
depends on OMAP_GPMC
help
diff --git a/drivers/video/fbdev/omap2/omapfb/Kconfig b/drivers/video/fbdev/omap2/omapfb/Kconfig
index 2d20e79adefc..d8227f4326bd 100644
--- a/drivers/video/fbdev/omap2/omapfb/Kconfig
+++ b/drivers/video/fbdev/omap2/omapfb/Kconfig
@@ -8,7 +8,7 @@ menuconfig FB_OMAP2
depends on DRM_OMAP = n
depends on GPIOLIB
select FB_OMAP2_DSS
- select OMAP2_VRFB if ARCH_OMAP2 || ARCH_OMAP3
+ select OMAP2_VRFB if ARCH_OMAP3
select FB_IOMEM_HELPERS
help
Frame buffer driver for OMAP2+ based boards.
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 54a3fa370004..ca151152da19 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -265,12 +265,6 @@ int omap2_clk_disable_autoidle_all(void);
int omap2_clk_enable_autoidle_all(void);
int omap2_clk_allow_idle(struct clk *clk);
int omap2_clk_deny_idle(struct clk *clk);
-unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
- unsigned long parent_rate);
-int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
- unsigned long parent_rate);
-void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
-void omap2xxx_clkt_vps_init(void);
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
void ti_dt_clk_init_retry_clks(void);
@@ -322,8 +316,6 @@ void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
int omap3_core_dpll_save_context(struct clk_hw *hw);
void omap3_core_dpll_restore_context(struct clk_hw *hw);
-extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
-
#ifdef CONFIG_ATAGS
int omap3430_clk_legacy_init(void);
int omap3430es1_clk_legacy_init(void);
--
2.53.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 07/14] ARM: imx: remove i.MX31 SoC support
2026-09-14 14:08 [PATCH v2 00/14] ARM: deprecated platform removal Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 06/14] ARM: omap2: remove omap24xx support Arnd Bergmann
@ 2026-09-14 14:08 ` Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 09/14] ARM: imx: remove nommu support Arnd Bergmann
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Arnd Bergmann @ 2026-09-14 14:08 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
imx, devicetree, Frank Li, Daniel Baluta, Vladimir Zapolskiy
From: Arnd Bergmann <arnd@arndb.de>
The Freescale i.MX31 was an early SoC based on the ARM1136r0 CPU core. It
was used in the Bug Labs modular computer but ultimately much less
popular than most other i.MX SoCs.
As the ARM1136r0 support is causing a lot of extra maintenance effort
to keep alive and there are no known users, remove i.MX31 in order to
allow removing support for that CPU core altogether.
The related i.MX35 is based on a slightly newer ARM1136r1 CPU core that
does not have this problem, so there is no reason to remove that.
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: imx@lists.linux.dev
Cc: devicetree@vger.kernel.org
Acked-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Daniel Baluta <daniel.baluta@nxp.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
I have follow-up patches to remove the i.MX31 specific clk
and hwrng drivers as well as the orphaned wm8350 driver.
---
arch/arm/Kconfig.debug | 9 -
arch/arm/boot/dts/nxp/imx/Makefile | 3 -
arch/arm/boot/dts/nxp/imx/imx31-bug.dts | 22 --
arch/arm/boot/dts/nxp/imx/imx31-lite.dts | 178 -----------
arch/arm/boot/dts/nxp/imx/imx31.dtsi | 371 -----------------------
arch/arm/configs/imx_v6_v7_defconfig | 1 -
arch/arm/include/debug/imx-uart.h | 10 -
arch/arm/mach-imx/Kconfig | 11 -
arch/arm/mach-imx/Makefile | 1 -
arch/arm/mach-imx/common.h | 2 -
arch/arm/mach-imx/cpu-imx31.c | 72 -----
arch/arm/mach-imx/mach-imx31.c | 18 --
arch/arm/mach-imx/mm-imx3.c | 44 ---
13 files changed, 742 deletions(-)
delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31-bug.dts
delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31-lite.dts
delete mode 100644 arch/arm/boot/dts/nxp/imx/imx31.dtsi
delete mode 100644 arch/arm/mach-imx/cpu-imx31.c
delete mode 100644 arch/arm/mach-imx/mach-imx31.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 237a2ea717ed..729f5184fba5 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -424,13 +424,6 @@ choice
Say Y here if you want kernel low-level debugging support
on i.MX28.
- config DEBUG_IMX31_UART
- bool "i.MX31 Debug UART"
- depends on SOC_IMX31
- help
- Say Y here if you want kernel low-level debugging support
- on i.MX31.
-
config DEBUG_IMX35_UART
bool "i.MX35 Debug UART"
depends on SOC_IMX35
@@ -1411,7 +1404,6 @@ config DEBUG_IMX_UART_PORT
depends on DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
DEBUG_IMX27_UART || \
- DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX50_UART || \
DEBUG_IMX51_UART || \
@@ -1468,7 +1460,6 @@ config DEBUG_LL_INCLUDE
default "debug/imx.S" if DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
DEBUG_IMX27_UART || \
- DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX50_UART || \
DEBUG_IMX51_UART || \
diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
index 1a2539fa19b4..e0747cb6e772 100644
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -16,9 +16,6 @@ dtb-$(CONFIG_SOC_IMX27) += \
imx27-pdk.dtb \
imx27-phytec-phycore-rdk.dtb \
imx27-phytec-phycard-s-rdk.dtb
-dtb-$(CONFIG_SOC_IMX31) += \
- imx31-bug.dtb \
- imx31-lite.dtb
dtb-$(CONFIG_SOC_IMX35) += \
imx35-eukrea-mbimxsd35-baseboard.dtb \
imx35-pdk.dtb
diff --git a/arch/arm/boot/dts/nxp/imx/imx31-bug.dts b/arch/arm/boot/dts/nxp/imx/imx31-bug.dts
deleted file mode 100644
index d87eee3f9b3c..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imx31-bug.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
- */
-
-/dts-v1/;
-#include "imx31.dtsi"
-
-/ {
- model = "Buglabs i.MX31 Bug 1.x";
- compatible = "buglabs,imx31-bug", "fsl,imx31";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x8000000>; /* 128M */
- };
-};
-
-&uart5 {
- uart-has-rtscts;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/nxp/imx/imx31-lite.dts b/arch/arm/boot/dts/nxp/imx/imx31-lite.dts
deleted file mode 100644
index 630f8fa69ba8..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imx31-lite.dts
+++ /dev/null
@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
-
-/dts-v1/;
-
-#include "imx31.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "LogicPD i.MX31 Lite";
- compatible = "logicpd,imx31-lite", "fsl,imx31";
-
- chosen {
- stdout-path = &uart1;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x8000000>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led0 {
- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
- };
-
- led1 {
- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&ata {
- status = "okay";
-};
-
-&nfc {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- nand-on-flash-bbt;
- status = "okay";
-};
-
-&sdhci1 {
- bus-width = <4>;
- cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
- wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&spi2 {
- status = "okay";
-
- pmic@0 {
- compatible = "fsl,mc13783";
- reg = <0>;
- spi-cs-high;
- spi-max-frequency = <1000000>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
-
- fsl,mc13xxx-uses-adc;
- fsl,mc13xxx-uses-rtc;
-
- regulators {
- sw1a { /* QVCC */
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- sw1b { /* QVCC */
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- sw2b { /* NVCC10 */
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- violo { /* NVCC1 and NVCC7 */
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- viohi { /* VIOHI */
- regulator-min-microvolt = <2775000>;
- regulator-max-microvolt = <2775000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vaudio { /* VAUDIO */
- regulator-min-microvolt = <2775000>;
- regulator-max-microvolt = <2775000>;
- };
-
- vcam { /* NVCC4 */
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */
- regulator-min-microvolt = <2775000>;
- regulator-max-microvolt = <2775000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vmmc2 { /* NVCC3 */
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-&uart1 {
- uart-has-rtscts;
- status = "okay";
-};
-
-/* Routed to the extension board */
-&uart2 {
- uart-has-rtscts;
- status = "okay";
-};
-
-/* Routed to the extension board */
-&uart3 {
- uart-has-rtscts;
- status = "okay";
-};
-
-&weim {
- status = "okay";
-
- flash@0,0 {
- compatible = "cfi-flash";
- reg = <0 0x0 0x200000>;
- bank-width = <2>;
- linux,mtd-name = "physmap-flash.0";
- fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>;
- };
-
- ethernet@4,0 {
- compatible = "smsc,lan9117", "smsc,lan9115";
- reg = <4 0x0 0x100>;
- interrupt-parent = <&gpio1>;
- interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
- phy-mode = "mii";
- reg-io-width = <2>;
- smsc,irq-push-pull;
- fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>;
- };
-};
diff --git a/arch/arm/boot/dts/nxp/imx/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi
deleted file mode 100644
index c58f855ea851..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imx31.dtsi
+++ /dev/null
@@ -1,371 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
-// Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- /*
- * The decompressor and also some bootloaders rely on a
- * pre-existing /chosen node to be available to insert the
- * command line and merge other ATAGS info.
- */
- chosen {};
-
- aliases {
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- serial4 = &uart5;
- spi0 = &spi1;
- spi1 = &spi2;
- spi2 = &spi3;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,arm1136jf-s";
- device_type = "cpu";
- reg = <0>;
- };
- };
-
- avic: interrupt-controller@68000000 {
- compatible = "fsl,imx31-avic", "fsl,avic";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x68000000 0x100000>;
- };
-
- soc: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&avic>;
- ranges;
-
- iram: sram@1fffc000 {
- compatible = "mmio-sram";
- reg = <0x1fffc000 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1fffc000 0x4000>;
- };
-
- aips1: bus@43f00000 { /* AIPS1 */
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x43f00000 0x100000>;
- ranges;
-
- i2c1: i2c@43f80000 {
- compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
- reg = <0x43f80000 0x4000>;
- interrupts = <10>;
- clocks = <&clks 33>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@43f84000 {
- compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
- reg = <0x43f84000 0x4000>;
- interrupts = <3>;
- clocks = <&clks 35>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ata: ata@43f8c000 {
- compatible = "fsl,imx31-pata", "fsl,imx27-pata";
- reg = <0x43f8c000 0x4000>;
- interrupts = <15>;
- clocks = <&clks 26>;
- status = "disabled";
- };
-
- uart1: serial@43f90000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x43f90000 0x4000>;
- interrupts = <45>;
- clocks = <&clks 10>, <&clks 30>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- uart2: serial@43f94000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x43f94000 0x4000>;
- interrupts = <32>;
- clocks = <&clks 10>, <&clks 31>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- i2c2: i2c@43f98000 {
- compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
- reg = <0x43f98000 0x4000>;
- interrupts = <4>;
- clocks = <&clks 34>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@43fa4000 {
- compatible = "fsl,imx31-cspi";
- reg = <0x43fa4000 0x4000>;
- interrupts = <14>;
- clocks = <&clks 10>, <&clks 53>;
- clock-names = "ipg", "per";
- dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
- dma-names = "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- kpp: kpp@43fa8000 {
- compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
- reg = <0x43fa8000 0x4000>;
- interrupts = <24>;
- clocks = <&clks 46>;
- status = "disabled";
- };
-
- uart4: serial@43fb0000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x43fb0000 0x4000>;
- clocks = <&clks 10>, <&clks 49>;
- clock-names = "ipg", "per";
- interrupts = <46>;
- status = "disabled";
- };
-
- uart5: serial@43fb4000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x43fb4000 0x4000>;
- interrupts = <47>;
- clocks = <&clks 10>, <&clks 50>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
- };
-
- spba-bus@50000000 {
- compatible = "fsl,spba-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x50000000 0x100000>;
- ranges;
-
- sdhci1: mmc@50004000 {
- compatible = "fsl,imx31-mmc";
- reg = <0x50004000 0x4000>;
- interrupts = <9>;
- clocks = <&clks 10>, <&clks 20>;
- clock-names = "ipg", "per";
- dmas = <&sdma 20 3 0>;
- dma-names = "rx-tx";
- status = "disabled";
- };
-
- sdhci2: mmc@50008000 {
- compatible = "fsl,imx31-mmc";
- reg = <0x50008000 0x4000>;
- interrupts = <8>;
- clocks = <&clks 10>, <&clks 21>;
- clock-names = "ipg", "per";
- dmas = <&sdma 21 3 0>;
- dma-names = "rx-tx";
- status = "disabled";
- };
-
- uart3: serial@5000c000 {
- compatible = "fsl,imx31-uart", "fsl,imx21-uart";
- reg = <0x5000c000 0x4000>;
- interrupts = <18>;
- clocks = <&clks 10>, <&clks 48>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- spi2: spi@50010000 {
- compatible = "fsl,imx31-cspi";
- reg = <0x50010000 0x4000>;
- interrupts = <13>;
- clocks = <&clks 10>, <&clks 54>;
- clock-names = "ipg", "per";
- dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
- dma-names = "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- iim: efuse@5001c000 {
- compatible = "fsl,imx31-iim";
- reg = <0x5001c000 0x1000>;
- interrupts = <19>;
- clocks = <&clks 25>;
- };
- };
-
- bus@53f00000 { /* AIPS2 */
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x53f00000 0x100000>;
- ranges;
-
- clks: ccm@53f80000 {
- compatible = "fsl,imx31-ccm";
- reg = <0x53f80000 0x4000>;
- interrupts = <31>, <53>;
- #clock-cells = <1>;
- };
-
- spi3: spi@53f84000 {
- compatible = "fsl,imx31-cspi";
- reg = <0x53f84000 0x4000>;
- interrupts = <17>;
- clocks = <&clks 10>, <&clks 28>;
- clock-names = "ipg", "per";
- dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
- dma-names = "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gpt: timer@53f90000 {
- compatible = "fsl,imx31-gpt";
- reg = <0x53f90000 0x4000>;
- interrupts = <29>;
- clocks = <&clks 10>, <&clks 22>;
- clock-names = "ipg", "per";
- };
-
- gpio3: gpio@53fa4000 {
- compatible = "fsl,imx31-gpio";
- reg = <0x53fa4000 0x4000>;
- interrupts = <56>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- rng@53fb0000 {
- compatible = "fsl,imx31-rnga";
- reg = <0x53fb0000 0x4000>;
- interrupts = <22>;
- clocks = <&clks 29>;
- };
-
- gpio1: gpio@53fcc000 {
- compatible = "fsl,imx31-gpio";
- reg = <0x53fcc000 0x4000>;
- interrupts = <52>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@53fd0000 {
- compatible = "fsl,imx31-gpio";
- reg = <0x53fd0000 0x4000>;
- interrupts = <51>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sdma: dma-controller@53fd4000 {
- compatible = "fsl,imx31-sdma";
- reg = <0x53fd4000 0x4000>;
- interrupts = <34>;
- clocks = <&clks 10>, <&clks 27>;
- clock-names = "ipg", "ahb";
- #dma-cells = <3>;
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
- };
-
- rtc: rtc@53fd8000 {
- compatible = "fsl,imx31-rtc", "fsl,imx21-rtc";
- reg = <0x53fd8000 0x4000>;
- interrupts = <25>;
- clocks = <&clks 2>, <&clks 40>;
- clock-names = "ref", "ipg";
- };
-
- wdog: watchdog@53fdc000 {
- compatible = "fsl,imx31-wdt", "fsl,imx21-wdt";
- reg = <0x53fdc000 0x4000>;
- clocks = <&clks 41>;
- interrupts = <55>;
- };
-
- pwm: pwm@53fe0000 {
- compatible = "fsl,imx31-pwm", "fsl,imx27-pwm";
- reg = <0x53fe0000 0x4000>;
- interrupts = <26>;
- clocks = <&clks 10>, <&clks 42>;
- clock-names = "ipg", "per";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- emi-bus@b8000000 { /* External Memory Interface */
- compatible = "simple-bus";
- reg = <0xb8000000 0x5000>;
- ranges;
- #address-cells = <1>;
- #size-cells = <1>;
-
- nfc: nand-controller@b8000000 {
- compatible = "fsl,imx31-nand", "fsl,imx27-nand";
- reg = <0xb8000000 0x1000>;
- interrupts = <33>;
- clocks = <&clks 9>;
- dmas = <&sdma 30 17 0>;
- dma-names = "rx-tx";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- };
-
- weim: memory-controller@b8002000 {
- compatible = "fsl,imx31-weim", "fsl,imx27-weim";
- reg = <0xb8002000 0x1000>;
- clocks = <&clks 56>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0xa0000000 0x08000000
- 1 0 0xa8000000 0x08000000
- 2 0 0xb0000000 0x02000000
- 3 0 0xb2000000 0x02000000
- 4 0 0xb4000000 0x02000000
- 5 0 0xb6000000 0x02000000>;
- status = "disabled";
- };
- };
- };
-};
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index ed588add8d31..6ac42c06c1e9 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -15,7 +15,6 @@ CONFIG_PERF_EVENTS=y
CONFIG_KEXEC=y
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_MXC=y
-CONFIG_SOC_IMX31=y
CONFIG_SOC_IMX35=y
CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX51=y
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 3edbb3c5b42b..df038a0852f9 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -26,14 +26,6 @@
#define IMX27_UART_BASE_ADDR(n) IMX27_UART##n##_BASE_ADDR
#define IMX27_UART_BASE(n) IMX27_UART_BASE_ADDR(n)
-#define IMX31_UART1_BASE_ADDR 0x43f90000
-#define IMX31_UART2_BASE_ADDR 0x43f94000
-#define IMX31_UART3_BASE_ADDR 0x5000c000
-#define IMX31_UART4_BASE_ADDR 0x43fb0000
-#define IMX31_UART5_BASE_ADDR 0x43fb4000
-#define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR
-#define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n)
-
#define IMX35_UART1_BASE_ADDR 0x43f90000
#define IMX35_UART2_BASE_ADDR 0x43f94000
#define IMX35_UART3_BASE_ADDR 0x5000c000
@@ -116,8 +108,6 @@
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX25)
#elif defined(CONFIG_DEBUG_IMX27_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX27)
-#elif defined(CONFIG_DEBUG_IMX31_UART)
-#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
#elif defined(CONFIG_DEBUG_IMX35_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35)
#elif defined(CONFIG_DEBUG_IMX50_UART)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3f0521c652cb..77704c6a70ba 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -39,17 +39,6 @@ if ARCH_MULTI_V6
comment "ARM1136 platforms"
-config SOC_IMX31
- bool "i.MX31 support (DEPRECATED)"
- depends on !SMP
- select CPU_ARM1136R0
- select MXC_AVIC
- help
- This enables support for Freescale i.MX31 processor
-
- This SoC is scheduled for removal in early 2027,
- since it uses the ARM1136r0 CPU revision.
-
config SOC_IMX35
bool "i.MX35 support"
select CPU_ARM1136R1
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5c650bf40e02..fa0144f0882d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -5,7 +5,6 @@ obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o
-obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o mach-imx31.o
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o
imx5-pm-$(CONFIG_PM) += pm-imx5.o
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index d7ecaa822adb..158ea819f5be 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -15,9 +15,7 @@ struct pt_regs;
struct clk;
struct device_node;
-void mx31_map_io(void);
void mx35_map_io(void);
-void imx31_init_early(void);
void imx35_init_early(void);
void mxc_set_cpu_type(unsigned int type);
void mxc_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
deleted file mode 100644
index e81ef9e36a1f..000000000000
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * MX31 CPU type detection
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- */
-
-#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/io.h>
-
-#include "common.h"
-#include "hardware.h"
-#include "iim.h"
-
-static int mx31_cpu_rev = -1;
-
-static struct {
- u8 srev;
- const char *name;
- unsigned int rev;
-} mx31_cpu_type[] = {
- { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
- { .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 },
- { .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 },
- { .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 },
- { .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 },
-};
-
-static int mx31_read_cpu_rev(void)
-{
- void __iomem *iim_base;
- struct device_node *np;
- u32 i, srev;
- int rev = IMX_CHIP_REVISION_UNKNOWN;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
- iim_base = of_iomap(np, 0);
- of_node_put(np);
- BUG_ON(!iim_base);
-
- /* read SREV register from IIM module */
- srev = imx_readl(iim_base + MXC_IIMSREV);
- srev &= 0xff;
-
- for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
- if (srev == mx31_cpu_type[i].srev) {
- rev = mx31_cpu_type[i].rev;
- imx_print_silicon_rev(mx31_cpu_type[i].name,
- mx31_cpu_type[i].rev);
- goto out;
- }
-
- imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
-
-out:
- iounmap(iim_base);
- return rev;
-}
-
-int mx31_revision(void)
-{
- if (mx31_cpu_rev == -1)
- mx31_cpu_rev = mx31_read_cpu_rev();
-
- return mx31_cpu_rev;
-}
-EXPORT_SYMBOL(mx31_revision);
diff --git a/arch/arm/mach-imx/mach-imx31.c b/arch/arm/mach-imx/mach-imx31.c
deleted file mode 100644
index e9a1092b6093..000000000000
--- a/arch/arm/mach-imx/mach-imx31.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix
- */
-
-#include <asm/mach/arch.h>
-#include "common.h"
-
-static const char * const imx31_dt_board_compat[] __initconst = {
- "fsl,imx31",
- NULL
-};
-
-DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .dt_compat = imx31_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 9b0b014d7fe2..42e73518004a 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -69,49 +69,6 @@ static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}
-#ifdef CONFIG_SOC_IMX31
-static struct map_desc mx31_io_desc[] __initdata = {
- imx_map_entry(MX31, X_MEMC, MT_DEVICE),
- imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
- imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
- imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
- imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx31_map_io(void)
-{
- iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
-}
-
-static void imx31_idle(void)
-{
- int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
- reg &= ~MXC_CCM_CCMR_LPM_MASK;
- imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
-
- imx3_idle();
-}
-
-void __init imx31_init_early(void)
-{
- struct device_node *np;
-
- mxc_set_cpu_type(MXC_CPU_MX31);
- arch_ioremap_caller = imx3_ioremap_caller;
- arm_pm_idle = imx31_idle;
- np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
- mx3_ccm_base = of_iomap(np, 0);
- of_node_put(np);
- BUG_ON(!mx3_ccm_base);
-}
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
static struct map_desc mx35_io_desc[] __initdata = {
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
@@ -147,4 +104,3 @@ void __init imx35_init_early(void)
of_node_put(np);
BUG_ON(!mx3_ccm_base);
}
-#endif /* ifdef CONFIG_SOC_IMX35 */
--
2.53.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 09/14] ARM: imx: remove nommu support
2026-09-14 14:08 [PATCH v2 00/14] ARM: deprecated platform removal Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 06/14] ARM: omap2: remove omap24xx support Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 07/14] ARM: imx: remove i.MX31 SoC support Arnd Bergmann
@ 2026-09-14 14:08 ` Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 10/14] ARM: lpc18xx: remove entire platform Arnd Bergmann
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Arnd Bergmann @ 2026-09-14 14:08 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Stefan Agner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, imx, Frank Li, Giulio Benetti
From: Arnd Bergmann <arnd@arndb.de>
The i.MX platform has grown support for three separate product
lines using Cortex-M based microcontrollers over the years:
- i.MX RT1050, a high-end microcontroller
- Vybrid vf610 suppors running Linux on either the Cortex-A5
CPU or the Cortex-M4 MCU
- i.MX7D similarly can run Linux on the Cortex-A7 or the
Cortex-M4
There are no known upstream users of any of those three, so
drop support and simplify the platform to assume that an MMU
is present.
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: imx@lists.linux.dev
Acked-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
I have follow-up patches to remove the imxrt specific pinctrl
and clk drivers.
---
arch/arm/boot/dts/nxp/imx/Makefile | 2 -
arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 -----------
arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 -----------------
arch/arm/boot/dts/nxp/vf/Makefile | 2 -
arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -
arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 -
arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -
arch/arm/configs/imxrt_defconfig | 35 -
arch/arm/configs/vf610m4_defconfig | 39 -
arch/arm/mach-imx/Kconfig | 27 +-
arch/arm/mach-imx/Makefile | 3 -
arch/arm/mach-imx/mach-imx7d-cm4.c | 18 -
arch/arm/mach-imx/mach-imxrt.c | 19 -
arch/arm/mach-imx/mach-vf610.c | 1 -
16 files changed, 6 insertions(+), 3136 deletions(-)
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h
delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
delete mode 100644 arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
delete mode 100644 arch/arm/configs/imxrt_defconfig
delete mode 100644 arch/arm/configs/vf610m4_defconfig
delete mode 100644 arch/arm/mach-imx/mach-imx7d-cm4.c
delete mode 100644 arch/arm/mach-imx/mach-imxrt.c
diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
index e0747cb6e772..288d16d9315d 100644
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -452,5 +452,3 @@ dtb-$(CONFIG_SOC_IMX7D) += \
dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-com.dtb \
imx7ulp-evk.dtb
-dtb-$(CONFIG_SOC_IMXRT) += \
- imxrt1050-evk.dtb
diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts b/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts
deleted file mode 100644
index 6a9c10decf52..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-/dts-v1/;
-#include "imxrt1050.dtsi"
-#include "imxrt1050-pinfunc.h"
-
-/ {
- model = "NXP IMXRT1050-evk board";
- compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
-
- chosen {
- stdout-path = &lpuart1;
- };
-
- aliases {
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- gpio4 = &gpio5;
- mmc0 = &usdhc1;
- serial0 = &lpuart1;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x2000000>;
- };
-};
-
-&lpuart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart1>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl_lpuart1: lpuart1grp {
- fsl,pins = <
- MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
- MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
- >;
- };
-
- pinctrl_usdhc0: usdhc0grp {
- fsl,pins = <
- MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
- MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
- MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
- >;
- };
-};
-
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc0>;
- pinctrl-1 = <&pinctrl_usdhc0>;
- pinctrl-2 = <&pinctrl_usdhc0>;
- pinctrl-3 = <&pinctrl_usdhc0>;
- cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h
deleted file mode 100644
index 22c14a3262ad..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h
+++ /dev/null
@@ -1,993 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
-#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
-
-#define IMX_PAD_SION 0x40000000
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-
-#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4
-#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3
-#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4
-
-#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4
-
-#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2
-
-#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0
-
-#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi b/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
deleted file mode 100644
index b0bad0d1ba36..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
+++ /dev/null
@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#include "../../armv7-m.dtsi"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/imxrt1050-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- osc: osc {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
-
- osc3M: osc3M {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <3000000>;
- };
- };
-
- soc {
- lpuart1: serial@40184000 {
- compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x40184000 0x4000>;
- interrupts = <20>;
- clocks = <&clks IMXRT1050_CLK_LPUART1>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- iomuxc: pinctrl@401f8000 {
- compatible = "fsl,imxrt1050-iomuxc";
- reg = <0x401f8000 0x4000>;
- fsl,mux_mask = <0x7>;
- };
-
- anatop: anatop@400d8000 {
- compatible = "fsl,imxrt-anatop";
- reg = <0x400d8000 0x4000>;
- };
-
- clks: clock-controller@400fc000 {
- compatible = "fsl,imxrt1050-ccm";
- reg = <0x400fc000 0x4000>;
- interrupts = <95>, <96>;
- clocks = <&osc>;
- clock-names = "osc";
- #clock-cells = <1>;
- assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
- <&clks IMXRT1050_CLK_PLL1_BYPASS>,
- <&clks IMXRT1050_CLK_PLL2_BYPASS>,
- <&clks IMXRT1050_CLK_PLL3_BYPASS>,
- <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
- <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
- assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
- <&clks IMXRT1050_CLK_PLL1_ARM>,
- <&clks IMXRT1050_CLK_PLL2_SYS>,
- <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
- <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
- <&clks IMXRT1050_CLK_PLL2_SYS>;
- };
-
- edma1: dma-controller@400e8000 {
- #dma-cells = <2>;
- compatible = "fsl,imx7ulp-edma";
- reg = <0x400e8000 0x4000>,
- <0x400ec000 0x4000>;
- dma-channels = <32>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
- <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
- clock-names = "dma", "dmamux0";
- clocks = <&clks IMXRT1050_CLK_DMA>,
- <&clks IMXRT1050_CLK_DMA_MUX>;
- };
-
- usdhc1: mmc@402c0000 {
- compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
- reg = <0x402c0000 0x4000>;
- interrupts = <110>;
- clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
- <&clks IMXRT1050_CLK_AHB_PODF>,
- <&clks IMXRT1050_CLK_USDHC1>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- fsl,wp-controller;
- no-1-8-v;
- max-frequency = <200000000>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- status = "disabled";
- };
-
- gpio1: gpio@401b8000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401b8000 0x4000>;
- interrupts = <80>, <81>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@401bc000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401bc000 0x4000>;
- interrupts = <82>, <83>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@401c0000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401c0000 0x4000>;
- interrupts = <84>, <85>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@401c4000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401c4000 0x4000>;
- interrupts = <86>, <87>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio5: gpio@400c0000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x400c0000 0x4000>;
- interrupts = <88>, <89>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpt: timer@401ec000 {
- compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
- reg = <0x401ec000 0x4000>;
- interrupts = <100>;
- clocks = <&osc3M>;
- clock-names = "per";
- };
- };
-};
diff --git a/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h
deleted file mode 100644
index 3b9fff2f08e1..000000000000
--- a/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h
+++ /dev/null
@@ -1,1561 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2021
- * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H
-#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H
-
-#define IMX_PAD_SION 0x40000000
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-
-#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
-#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
-#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
-#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0
-#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0
-#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x004 0x044 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x008 0x048 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x008 0x048 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0
-#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x00C 0x04C 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x00C 0x04C 0x094 0x1 0x0
-#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0
-#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x00C 0x04C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0
-#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x010 0x050 0x0A0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0
-#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0
-#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x010 0x050 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x014 0x054 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0
-#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0
-#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1
-#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0
-#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0
-
-#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0
-#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1
-#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x018 0x058 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x018 0x058 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x018 0x058 0x0 0x6 0x0
-#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x018 0x058 0x0 0x7 0x0
-#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x018 0x058 0x0 0x8 0x0
-#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x018 0x058 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x01C 0x05C 0x08C 0x0 0x0
-#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x01C 0x05C 0x0CC 0x2 0x0
-#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x01C 0x05C 0x0AC 0x3 0x1
-#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x01C 0x05C 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x01C 0x05C 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x01C 0x05C 0x080 0x6 0x1
-#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x01C 0x05C 0x0 0x7 0x0
-#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x01C 0x05C 0x0 0x8 0x0
-#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x01C 0x05C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x020 0x060 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x020 0x060 0x0A8 0x0 0x1
-#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x020 0x060 0x0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x020 0x060 0x0D4 0x2 0x0
-#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x020 0x060 0x0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x020 0x060 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x020 0x060 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x020 0x060 0x088 0x6 0x1
-#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x020 0x060 0x0 0x7 0x0
-#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x020 0x060 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x024 0x064 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x024 0x064 0x0A4 0x0 0x1
-#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x024 0x064 0x080 0x1 0x2
-#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x024 0x064 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x024 0x064 0x0B4 0x3 0x1
-#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x024 0x064 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x024 0x064 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x024 0x064 0x084 0x6 0x1
-#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x024 0x064 0x0 0x7 0x0
-
-#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x028 0x068 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x028 0x068 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x028 0x068 0x0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x028 0x068 0x090 0x2 0x1
-#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x028 0x068 0x0B8 0x3 0x0
-#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x028 0x068 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x028 0x068 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x028 0x068 0x0 0x6 0x0
-#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x028 0x068 0x0DC 0x7 0x1
-#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x028 0x068 0x0B0 0x8 0x2
-
-#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x02C 0x06C 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x02C 0x06C 0x0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x02C 0x06C 0x08C 0x2 0x1
-#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x02C 0x06C 0x0BC 0x3 0x0
-#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x02C 0x06C 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x02C 0x06C 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x02C 0x06C 0x0 0x6 0x0
-#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x02C 0x06C 0x0 0x7 0x0
-#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x02C 0x06C 0x0AC 0x8 0x2
-#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x02C 0x06C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x030 0x070 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x030 0x070 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x030 0x070 0x0 0x1 0x0
-#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x030 0x070 0x0C0 0x3 0x0
-#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x030 0x070 0x0 0x4 0x0
-#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x030 0x070 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x030 0x070 0x0 0x6 0x0
-#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x030 0x070 0x0D8 0x7 0x1
-#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x030 0x070 0x098 0x8 0x1
-
-#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x034 0x074 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x034 0x074 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x034 0x074 0x0B8 0x1 0x1
-#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x034 0x074 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x034 0x074 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x034 0x074 0x0D0 0x7 0x1
-#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x034 0x074 0x094 0x8 0x1
-
-#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x038 0x078 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x038 0x078 0x0BC 0x1 0x1
-#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x038 0x078 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x038 0x078 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x038 0x078 0x0CC 0x7 0x1
-#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x038 0x078 0x0A0 0x8 0x1
-#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x038 0x078 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x03C 0x07C 0x0 0xA 0x0
-#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x03C 0x07C 0x0 0x0 0x0
-#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x03C 0x07C 0x0C0 0x1 0x1
-#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x03C 0x07C 0x0 0x2 0x0
-#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x03C 0x07C 0x0 0x5 0x0
-#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x03C 0x07C 0x0D4 0x7 0x1
-#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x03C 0x07C 0x09C 0x8 0x1
-
-#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000 0x40C94040 0x0 0x5 0x0
-#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000 0x40C94040 0x0C4 0x7 0x1
-
-#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004 0x40C94044 0x0 0x0 0x0
-#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004 0x40C94044 0x0 0x5 0x0
-
-#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008 0x40C94048 0x0 0x0 0x0
-#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008 0x40C94048 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400C 0x40C9404C 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400C 0x40C9404C 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010 0x40C94050 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010 0x40C94050 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014 0x40C94054 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014 0x40C94054 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018 0x40C94058 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018 0x40C94058 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401C 0x40C9405C 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401C 0x40C9405C 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020 0x40C94060 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020 0x40C94060 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024 0x40C94064 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024 0x40C94064 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028 0x40C94068 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028 0x40C94068 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402C 0x40C9406C 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402C 0x40C9406C 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030 0x40C94070 0x0 0x0 0x0
-#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030 0x40C94070 0x0 0x5 0x0
-
-#define IOMUXC_TEST_MODE_DIG 0x0 0x40C94034 0x0 0x0 0x0
-
-#define IOMUXC_POR_B_DIG 0x0 0x40C94038 0x0 0x0 0x0
-
-#define IOMUXC_ONOFF_DIG 0x0 0x40C9403C 0x0 0x0 0x0
-
-#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 0x014 0x258 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 0x014 0x258 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x014 0x258 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x014 0x258 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01 0x014 0x258 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 0x018 0x25C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x018 0x25C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x018 0x25C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02 0x018 0x25C 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 0x018 0x25C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 0x01C 0x260 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x01C 0x260 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x01C 0x260 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03 0x01C 0x260 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 0x01C 0x260 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 0x020 0x264 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 0x020 0x264 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x020 0x264 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x020 0x264 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04 0x020 0x264 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 0x024 0x268 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x024 0x268 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x024 0x268 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05 0x024 0x268 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 0x024 0x268 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 0x028 0x26C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x028 0x26C 0x518 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x028 0x26C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06 0x028 0x26C 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 0x028 0x26C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 0x02C 0x270 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 0x02C 0x270 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x02C 0x270 0x524 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x02C 0x270 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07 0x02C 0x270 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 0x030 0x274 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x030 0x274 0x51C 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x030 0x274 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08 0x030 0x274 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 0x030 0x274 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 0x034 0x278 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x034 0x278 0x528 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x034 0x278 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x034 0x278 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09 0x034 0x278 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 0x034 0x278 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 0x038 0x27C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x038 0x27C 0x520 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x038 0x27C 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x038 0x27C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10 0x038 0x27C 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 0x038 0x27C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 0x03C 0x280 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 0x03C 0x280 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x03C 0x280 0x52C 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 0x03C 0x280 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x03C 0x280 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11 0x03C 0x280 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 0x040 0x284 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04 0x040 0x284 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 0x040 0x284 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x040 0x284 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12 0x040 0x284 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 0x040 0x284 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 0x044 0x288 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05 0x044 0x288 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 0x044 0x288 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x044 0x288 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13 0x044 0x288 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 0x044 0x288 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 0x048 0x28C 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 0x048 0x28C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06 0x048 0x28C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_14_GPT5_CLK 0x048 0x28C 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x048 0x28C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14 0x048 0x28C 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 0x04C 0x290 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07 0x04C 0x290 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x04C 0x290 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15 0x04C 0x290 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 0x04C 0x290 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 0x050 0x294 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08 0x050 0x294 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x050 0x294 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16 0x050 0x294 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 0x050 0x294 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 0x054 0x298 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 0x054 0x298 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x054 0x298 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0 0x054 0x298 0x63C 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x054 0x298 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17 0x054 0x298 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 0x058 0x29C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x058 0x29C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0 0x058 0x29C 0x648 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x058 0x29C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18 0x058 0x29C 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 0x058 0x29C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 0x05C 0x2A0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x05C 0x2A0 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0 0x05C 0x2A0 0x654 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x05C 0x2A0 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19 0x05C 0x2A0 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 0x05C 0x2A0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 0x060 0x2A4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x060 0x2A4 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0 0x060 0x2A4 0x660 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x060 0x2A4 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20 0x060 0x2A4 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 0x060 0x2A4 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 0x064 0x2A8 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 0x064 0x2A8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x064 0x2A8 0x53C 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x064 0x2A8 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21 0x064 0x2A8 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 0x068 0x2AC 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 0x068 0x2AC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x068 0x2AC 0x54C 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x068 0x2AC 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22 0x068 0x2AC 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 0x06C 0x2B0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x06C 0x2B0 0x500 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x06C 0x2B0 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23 0x06C 0x2B0 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 0x06C 0x2B0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 0x070 0x2B4 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_24_SEMC_CAS 0x070 0x2B4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x070 0x2B4 0x50C 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x070 0x2B4 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24 0x070 0x2B4 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 0x074 0x2B8 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_25_SEMC_RAS 0x074 0x2B8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x074 0x2B8 0x504 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x074 0x2B8 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25 0x074 0x2B8 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_26_SEMC_CLK 0x078 0x2BC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x078 0x2BC 0x510 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x078 0x2BC 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26 0x078 0x2BC 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 0x078 0x2BC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 0x07C 0x2C0 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_27_SEMC_CKE 0x07C 0x2C0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x07C 0x2C0 0x508 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x07C 0x2C0 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27 0x07C 0x2C0 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 0x080 0x2C4 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_28_SEMC_WE 0x080 0x2C4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x080 0x2C4 0x514 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x080 0x2C4 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28 0x080 0x2C4 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 0x084 0x2C8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x084 0x2C8 0x530 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x084 0x2C8 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29 0x084 0x2C8 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 0x084 0x2C8 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 0x088 0x2CC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x088 0x2CC 0x540 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x088 0x2CC 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30 0x088 0x2CC 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 0x088 0x2CC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 0x08C 0x2D0 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 0x08C 0x2D0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x08C 0x2D0 0x534 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x08C 0x2D0 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31 0x08C 0x2D0 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 0x090 0x2D4 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 0x090 0x2D4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x090 0x2D4 0x544 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x090 0x2D4 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 0x094 0x2D8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x094 0x2D8 0x538 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x094 0x2D8 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 0x094 0x2D8 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 0x098 0x2DC 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 0x098 0x2DC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x098 0x2DC 0x548 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x098 0x2DC 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 0x09C 0x2E0 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 0x09C 0x2E0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09 0x09C 0x2E0 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x09C 0x2E0 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 0x0A0 0x2E4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10 0x0A0 0x2E4 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x0A0 0x2E4 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 0x0A0 0x2E4 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 0x0A4 0x2E8 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 0x0A4 0x2E8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11 0x0A4 0x2E8 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x0A4 0x2E8 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 0x0A8 0x2EC 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 0x0A8 0x2EC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x0A8 0x2EC 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1 0x0A8 0x2EC 0x640 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x0A8 0x2EC 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_EMC_B1_39_SEMC_DQS 0x0AC 0x2F0 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x0AC 0x2F0 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1 0x0AC 0x2F0 0x64C 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x0AC 0x2F0 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 0x0AC 0x2F0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_40_SEMC_RDY 0x0B0 0x2F4 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12 0x0B0 0x2F4 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT 0x0B0 0x2F4 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD 0x0B0 0x2F4 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x0B0 0x2F4 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC 0x0B0 0x2F4 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 0x0B0 0x2F4 0x0 0x9 0x0
-#define IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 0x0B0 0x2F4 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 0x0B4 0x2F8 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 0x0B4 0x2F8 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13 0x0B4 0x2F8 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B1_41_MQS_LEFT 0x0B4 0x2F8 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD 0x0B4 0x2F8 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x0B4 0x2F8 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x0B4 0x2F8 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO 0x0B4 0x2F8 0x4C8 0x7 0x0
-#define IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 0x0B4 0x2F8 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 0x0B8 0x2FC 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x0B8 0x2FC 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1 0x0B8 0x2FC 0x658 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B 0x0B8 0x2FC 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x0B8 0x2FC 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x0B8 0x2FC 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20 0x0B8 0x2FC 0x6D8 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x0B8 0x2FC 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK 0x0B8 0x2FC 0x5D0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL 0x0B8 0x2FC 0x5B4 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 0x0B8 0x2FC 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x0B8 0x2FC 0x530 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 0x0BC 0x300 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B 0x0BC 0x300 0x6D0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1 0x0BC 0x300 0x664 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B 0x0BC 0x300 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x0BC 0x300 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x0BC 0x300 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21 0x0BC 0x300 0x6DC 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x0BC 0x300 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 0x0BC 0x300 0x5CC 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA 0x0BC 0x300 0x5B8 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 0x0BC 0x300 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x0BC 0x300 0x540 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 0x0C0 0x304 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_02_USDHC2_WP 0x0C0 0x304 0x6D4 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x0C0 0x304 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x0C0 0x304 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x0C0 0x304 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22 0x0C0 0x304 0x6E0 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x0C0 0x304 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT 0x0C0 0x304 0x5D8 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 0x0C0 0x304 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x0C0 0x304 0x534 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 0x0C4 0x308 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT 0x0C4 0x308 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x0C4 0x308 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x0C4 0x308 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x0C4 0x308 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23 0x0C4 0x308 0x6E4 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x0C4 0x308 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN 0x0C4 0x308 0x5D4 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 0x0C4 0x308 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x0C4 0x308 0x544 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 0x0C8 0x30C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B 0x0C8 0x30C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK 0x0C8 0x30C 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x0C8 0x30C 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x0C8 0x30C 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x0C8 0x30C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24 0x0C8 0x30C 0x6E8 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x0C8 0x30C 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK 0x0C8 0x30C 0x600 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 0x0C8 0x30C 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x0C8 0x30C 0x538 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 0x0CC 0x310 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_05_GPT3_CLK 0x0CC 0x310 0x598 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x0CC 0x310 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x0CC 0x310 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x0CC 0x310 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x0CC 0x310 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25 0x0CC 0x310 0x6EC 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x0CC 0x310 0x4CC 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 0x0CC 0x310 0x5F0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x0CC 0x310 0x0 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 0x0CC 0x310 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x0CC 0x310 0x548 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 0x0D0 0x314 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x0D0 0x314 0x590 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 0x0D0 0x314 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x0D0 0x314 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x0D0 0x314 0x53C 0xB 0x1
-#define IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x0D0 0x314 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x0D0 0x314 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x0D0 0x314 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26 0x0D0 0x314 0x6F0 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x0D0 0x314 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT 0x0D0 0x314 0x608 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x0D0 0x314 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 0x0D4 0x318 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x0D4 0x318 0x594 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA 0x0D4 0x318 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x0D4 0x318 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x0D4 0x318 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x0D4 0x318 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27 0x0D4 0x318 0x6F4 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x0D4 0x318 0x4DC 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN 0x0D4 0x318 0x604 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x0D4 0x318 0x0 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 0x0D4 0x318 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x0D4 0x318 0x54C 0xB 0x1
-
-#define IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 0x0D8 0x31C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 0x0D8 0x31C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA 0x0D8 0x31C 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x0D8 0x31C 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x0D8 0x31C 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x0D8 0x31C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28 0x0D8 0x31C 0x6F8 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x0D8 0x31C 0x4D8 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 0x0D8 0x31C 0x5F4 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x0D8 0x31C 0x0 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 0x0D8 0x31C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 0x0DC 0x320 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 0x0DC 0x320 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 0x0DC 0x320 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x0DC 0x320 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x0DC 0x320 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x0DC 0x320 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x0DC 0x320 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29 0x0DC 0x320 0x6FC 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS 0x0DC 0x320 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 0x0DC 0x320 0x5F8 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0 0x0DC 0x320 0x63C 0x9 0x1
-
-#define IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 0x0E0 0x324 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 0x0E0 0x324 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 0x0E0 0x324 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x0E0 0x324 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x0E0 0x324 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x0E0 0x324 0x58C 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x0E0 0x324 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30 0x0E0 0x324 0x700 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL 0x0E0 0x324 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 0x0E0 0x324 0x5FC 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1 0x0E0 0x324 0x640 0x9 0x1
-
-#define IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 0x0E4 0x328 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_11_SPDIF_IN 0x0E4 0x328 0x6B4 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x0E4 0x328 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x0E4 0x328 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x0E4 0x328 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x0E4 0x328 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31 0x0E4 0x328 0x704 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO 0x0E4 0x328 0x69C 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2 0x0E4 0x328 0x644 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 0x0E4 0x328 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 0x0E8 0x32C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT 0x0E8 0x32C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x0E8 0x32C 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x0E8 0x32C 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x0E8 0x32C 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x0E8 0x32C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32 0x0E8 0x32C 0x708 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK 0x0E8 0x32C 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3 0x0E8 0x32C 0x0 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 0x0E8 0x32C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 0x0EC 0x330 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 0x0EC 0x330 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x0EC 0x330 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA 0x0EC 0x330 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x0EC 0x330 0x57C 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x0EC 0x330 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33 0x0EC 0x330 0x70C 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST 0x0EC 0x330 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0 0x0EC 0x330 0x648 0x9 0x1
-
-#define IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 0x0F0 0x334 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x0F0 0x334 0x4E8 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA 0x0F0 0x334 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x0F0 0x334 0x580 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x0F0 0x334 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34 0x0F0 0x334 0x710 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x0F0 0x334 0x0 0x7 0x0
-#define IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x0F0 0x334 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1 0x0F0 0x334 0x64C 0x9 0x1
-#define IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 0x0F0 0x334 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 0x0F4 0x338 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x0F4 0x338 0x4D0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x0F4 0x338 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x0F4 0x338 0x584 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x0F4 0x338 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35 0x0F4 0x338 0x714 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD 0x0F4 0x338 0x6A0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2 0x0F4 0x338 0x650 0x9 0x0
-#define IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 0x0F4 0x338 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 0x0F8 0x33C 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 0x0F8 0x33C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14 0x0F8 0x33C 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x0F8 0x33C 0x4D4 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x0F8 0x33C 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x0F8 0x33C 0x588 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x0F8 0x33C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x0F8 0x33C 0x6A4 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3 0x0F8 0x33C 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 0x0FC 0x340 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15 0x0FC 0x340 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x0FC 0x340 0x4E0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK 0x0FC 0x340 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x0FC 0x340 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x0FC 0x340 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY 0x0FC 0x340 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0 0x0FC 0x340 0x654 0x9 0x1
-#define IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 0x0FC 0x340 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 0x100 0x344 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16 0x100 0x344 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x100 0x344 0x4E4 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B 0x100 0x344 0x0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x100 0x344 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x100 0x344 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x100 0x344 0x550 0x6 0x0
-#define IOMUXC_GPIO_EMC_B2_18_WDOG1_B 0x100 0x344 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1 0x100 0x344 0x658 0x9 0x1
-#define IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 0x100 0x344 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 0x104 0x348 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x104 0x348 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x104 0x348 0x0 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x104 0x348 0x0 0x2 0x0
-#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x104 0x348 0x4C4 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x104 0x348 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x104 0x348 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x104 0x348 0x0 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2 0x104 0x348 0x65C 0x9 0x0
-
-#define IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 0x108 0x34C 0x0 0xA 0x0
-#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x108 0x34C 0x0 0x0 0x0
-#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x108 0x34C 0x4AC 0x1 0x0
-#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x108 0x34C 0x4C8 0x2 0x1
-#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x108 0x34C 0x4A0 0x3 0x0
-#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x108 0x34C 0x0 0x4 0x0
-#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x108 0x34C 0x0 0x5 0x0
-#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x108 0x34C 0x4EC 0x8 0x0
-#define IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3 0x108 0x34C 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_00_GPIO8_IO31 0x10C 0x350 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_00_EMVSIM1_IO 0x10C 0x350 0x69C 0x0 0x1
-#define IOMUXC_GPIO_AD_00_FLEXCAN2_TX 0x10C 0x350 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x10C 0x350 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 0x10C 0x350 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A 0x10C 0x350 0x500 0x4 0x1
-#define IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 0x10C 0x350 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_00_LPUART7_TXD 0x10C 0x350 0x630 0x6 0x0
-#define IOMUXC_GPIO_AD_00_FLEXIO2_D00 0x10C 0x350 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x10C 0x350 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_01_GPIO9_IO00 0x110 0x354 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_01_EMVSIM1_CLK 0x110 0x354 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_01_FLEXCAN2_RX 0x110 0x354 0x49C 0x1 0x0
-#define IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x110 0x354 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 0x110 0x354 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B 0x110 0x354 0x50C 0x4 0x1
-#define IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 0x110 0x354 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_01_LPUART7_RXD 0x110 0x354 0x62C 0x6 0x0
-#define IOMUXC_GPIO_AD_01_FLEXIO2_D01 0x110 0x354 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x110 0x354 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_02_GPIO9_IO01 0x114 0x358 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_02_EMVSIM1_RST 0x114 0x358 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_02_LPUART7_CTS_B 0x114 0x358 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x114 0x358 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_02_GPT2_COMPARE1 0x114 0x358 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A 0x114 0x358 0x504 0x4 0x1
-#define IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 0x114 0x358 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_02_LPUART8_TXD 0x114 0x358 0x638 0x6 0x0
-#define IOMUXC_GPIO_AD_02_FLEXIO2_D02 0x114 0x358 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x114 0x358 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_03_GPIO9_IO02 0x118 0x35C 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_03_EMVSIM1_SVEN 0x118 0x35C 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_03_LPUART7_RTS_B 0x118 0x35C 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x118 0x35C 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_03_GPT2_COMPARE2 0x118 0x35C 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B 0x118 0x35C 0x510 0x4 0x1
-#define IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 0x118 0x35C 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_03_LPUART8_RXD 0x118 0x35C 0x634 0x6 0x0
-#define IOMUXC_GPIO_AD_03_FLEXIO2_D03 0x118 0x35C 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x118 0x35C 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_04_EMVSIM1_PD 0x11C 0x360 0x6A0 0x0 0x1
-#define IOMUXC_GPIO_AD_04_LPUART8_CTS_B 0x11C 0x360 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x11C 0x360 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_04_GPT2_COMPARE3 0x11C 0x360 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x11C 0x360 0x508 0x4 0x1
-#define IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 0x11C 0x360 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_04_WDOG1_B 0x11C 0x360 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_04_FLEXIO2_D04 0x11C 0x360 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_04_TMR4_TIMER0 0x11C 0x360 0x660 0x9 0x1
-#define IOMUXC_GPIO_AD_04_GPIO9_IO03 0x11C 0x360 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x120 0x364 0x6A4 0x0 0x1
-#define IOMUXC_GPIO_AD_05_LPUART8_RTS_B 0x120 0x364 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x120 0x364 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_05_GPT2_CLK 0x120 0x364 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B 0x120 0x364 0x514 0x4 0x1
-#define IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 0x120 0x364 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_05_WDOG2_B 0x120 0x364 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_05_FLEXIO2_D05 0x120 0x364 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_05_TMR4_TIMER1 0x120 0x364 0x664 0x9 0x1
-#define IOMUXC_GPIO_AD_05_GPIO9_IO04 0x120 0x364 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_06_USB_OTG2_OC 0x124 0x368 0x6B8 0x0 0x0
-#define IOMUXC_GPIO_AD_06_FLEXCAN1_TX 0x124 0x368 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_06_EMVSIM2_IO 0x124 0x368 0x6A8 0x2 0x0
-#define IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 0x124 0x368 0x590 0x3 0x1
-#define IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x124 0x368 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 0x124 0x368 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN 0x124 0x368 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_06_FLEXIO2_D06 0x124 0x368 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_06_TMR4_TIMER2 0x124 0x368 0x668 0x9 0x0
-#define IOMUXC_GPIO_AD_06_GPIO9_IO05 0x124 0x368 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X 0x124 0x368 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_07_USB_OTG2_PWR 0x128 0x36C 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_07_FLEXCAN1_RX 0x128 0x36C 0x498 0x1 0x0
-#define IOMUXC_GPIO_AD_07_EMVSIM2_CLK 0x128 0x36C 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 0x128 0x36C 0x594 0x3 0x1
-#define IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x128 0x36C 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 0x128 0x36C 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x128 0x36C 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_07_FLEXIO2_D07 0x128 0x36C 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_07_TMR4_TIMER3 0x128 0x36C 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_07_GPIO9_IO06 0x128 0x36C 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X 0x128 0x36C 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID 0x12C 0x370 0x6C4 0x0 0x0
-#define IOMUXC_GPIO_AD_08_LPI2C1_SCL 0x12C 0x370 0x5AC 0x1 0x0
-#define IOMUXC_GPIO_AD_08_EMVSIM2_RST 0x12C 0x370 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_08_GPT3_COMPARE1 0x12C 0x370 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x12C 0x370 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 0x12C 0x370 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN 0x12C 0x370 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_08_FLEXIO2_D08 0x12C 0x370 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_08_GPIO9_IO07 0x12C 0x370 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X 0x12C 0x370 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0x130 0x374 0x6C0 0x0 0x0
-#define IOMUXC_GPIO_AD_09_LPI2C1_SDA 0x130 0x374 0x5B0 0x1 0x0
-#define IOMUXC_GPIO_AD_09_EMVSIM2_SVEN 0x130 0x374 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_09_GPT3_COMPARE2 0x130 0x374 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x130 0x374 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 0x130 0x374 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x130 0x374 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_09_FLEXIO2_D09 0x130 0x374 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_09_GPIO9_IO08 0x130 0x374 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x130 0x374 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_10_USB_OTG1_PWR 0x134 0x378 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_10_LPI2C1_SCLS 0x134 0x378 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_10_EMVSIM2_PD 0x134 0x378 0x6AC 0x2 0x0
-#define IOMUXC_GPIO_AD_10_GPT3_COMPARE3 0x134 0x378 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x134 0x378 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 0x134 0x378 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN 0x134 0x378 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_10_FLEXIO2_D10 0x134 0x378 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_10_GPIO9_IO09 0x134 0x378 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X 0x134 0x378 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_11_USB_OTG1_OC 0x138 0x37C 0x6BC 0x0 0x0
-#define IOMUXC_GPIO_AD_11_LPI2C1_SDAS 0x138 0x37C 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x138 0x37C 0x6B0 0x2 0x0
-#define IOMUXC_GPIO_AD_11_GPT3_CLK 0x138 0x37C 0x598 0x3 0x1
-#define IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x138 0x37C 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 0x138 0x37C 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x138 0x37C 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_11_FLEXIO2_D11 0x138 0x37C 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_11_GPIO9_IO10 0x138 0x37C 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X 0x138 0x37C 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_12_SPDIF_LOCK 0x13C 0x380 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_12_LPI2C1_HREQ 0x13C 0x380 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 0x13C 0x380 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 0x13C 0x380 0x570 0x3 0x0
-#define IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x13C 0x380 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 0x13C 0x380 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_12_ENET_TX_DATA03 0x13C 0x380 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_12_FLEXIO2_D12 0x13C 0x380 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_12_EWM_OUT_B 0x13C 0x380 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_12_GPIO9_IO11 0x13C 0x380 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X 0x13C 0x380 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_13_SPDIF_SR_CLK 0x140 0x384 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_13_PIT1_TRIGGER0 0x140 0x384 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 0x140 0x384 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 0x140 0x384 0x56C 0x3 0x0
-#define IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x140 0x384 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 0x140 0x384 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_13_ENET_TX_DATA02 0x140 0x384 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_13_FLEXIO2_D13 0x140 0x384 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_13_REF_CLK_32K 0x140 0x384 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_13_GPIO9_IO12 0x140 0x384 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X 0x140 0x384 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK 0x144 0x388 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x144 0x388 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_14_GPT1_COMPARE1 0x144 0x388 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 0x144 0x388 0x568 0x3 0x0
-#define IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x144 0x388 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 0x144 0x388 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_14_ENET_RX_CLK 0x144 0x388 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_14_FLEXIO2_D14 0x144 0x388 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x144 0x388 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_14_GPIO9_IO13 0x144 0x388 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X 0x144 0x388 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_15_GPIO9_IO14 0x148 0x38C 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X 0x148 0x38C 0x0 0xB 0x0
-#define IOMUXC_GPIO_AD_15_SPDIF_IN 0x148 0x38C 0x6B4 0x0 0x1
-#define IOMUXC_GPIO_AD_15_LPUART10_TXD 0x148 0x38C 0x628 0x1 0x0
-#define IOMUXC_GPIO_AD_15_GPT1_COMPARE2 0x148 0x38C 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 0x148 0x38C 0x564 0x3 0x0
-#define IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x148 0x38C 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 0x148 0x38C 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_15_ENET_TX_ER 0x148 0x38C 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_15_FLEXIO2_D15 0x148 0x38C 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_AD_16_SPDIF_OUT 0x14C 0x390 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_16_LPUART10_RXD 0x14C 0x390 0x624 0x1 0x0
-#define IOMUXC_GPIO_AD_16_GPT1_COMPARE3 0x14C 0x390 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK 0x14C 0x390 0x578 0x3 0x0
-#define IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x14C 0x390 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 0x14C 0x390 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_16_ENET_RX_DATA03 0x14C 0x390 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_16_FLEXIO2_D16 0x14C 0x390 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_16_ENET_1G_MDC 0x14C 0x390 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_16_GPIO9_IO15 0x14C 0x390 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X 0x14C 0x390 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_17_SAI1_MCLK 0x150 0x394 0x66C 0x0 0x0
-#define IOMUXC_GPIO_AD_17_ACMP1_OUT 0x150 0x394 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_17_GPT1_CLK 0x150 0x394 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS 0x150 0x394 0x550 0x3 0x1
-#define IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x150 0x394 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 0x150 0x394 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_17_ENET_RX_DATA02 0x150 0x394 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_17_FLEXIO2_D17 0x150 0x394 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_17_ENET_1G_MDIO 0x150 0x394 0x4C8 0x9 0x2
-#define IOMUXC_GPIO_AD_17_GPIO9_IO16 0x150 0x394 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X 0x150 0x394 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_18_GPIO9_IO17 0x154 0x398 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X 0x154 0x398 0x0 0xB 0x0
-#define IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 0x154 0x398 0x678 0x0 0x0
-#define IOMUXC_GPIO_AD_18_ACMP2_OUT 0x154 0x398 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_18_LPSPI1_PCS1 0x154 0x398 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x154 0x398 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x154 0x398 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 0x154 0x398 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_18_ENET_CRS 0x154 0x398 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_18_FLEXIO2_D18 0x154 0x398 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_18_LPI2C2_SCL 0x154 0x398 0x5B4 0x9 0x1
-
-#define IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 0x158 0x39C 0x670 0x0 0x0
-#define IOMUXC_GPIO_AD_19_ACMP3_OUT 0x158 0x39C 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_19_LPSPI1_PCS2 0x158 0x39C 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK 0x158 0x39C 0x574 0x3 0x0
-#define IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x158 0x39C 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 0x158 0x39C 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_19_ENET_COL 0x158 0x39C 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_19_FLEXIO2_D19 0x158 0x39C 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_19_LPI2C2_SDA 0x158 0x39C 0x5B8 0x9 0x1
-#define IOMUXC_GPIO_AD_19_GPIO9_IO18 0x158 0x39C 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X 0x158 0x39C 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 0x15C 0x3A0 0x674 0x0 0x0
-#define IOMUXC_GPIO_AD_20_ACMP4_OUT 0x15C 0x3A0 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_20_LPSPI1_PCS3 0x15C 0x3A0 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 0x15C 0x3A0 0x554 0x3 0x0
-#define IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x15C 0x3A0 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 0x15C 0x3A0 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_20_KPP_ROW07 0x15C 0x3A0 0x5A8 0x6 0x0
-#define IOMUXC_GPIO_AD_20_FLEXIO2_D20 0x15C 0x3A0 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x15C 0x3A0 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_20_GPIO9_IO19 0x15C 0x3A0 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X 0x15C 0x3A0 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 0x160 0x3A4 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_21_LPSPI2_PCS1 0x160 0x3A4 0x5E0 0x2 0x0
-#define IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 0x160 0x3A4 0x558 0x3 0x0
-#define IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x160 0x3A4 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 0x160 0x3A4 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_21_KPP_COL07 0x160 0x3A4 0x5A0 0x6 0x0
-#define IOMUXC_GPIO_AD_21_FLEXIO2_D21 0x160 0x3A4 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x160 0x3A4 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_21_GPIO9_IO20 0x160 0x3A4 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X 0x160 0x3A4 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_22_GPIO9_IO21 0x164 0x3A8 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 0x164 0x3A8 0x67C 0x0 0x0
-#define IOMUXC_GPIO_AD_22_LPSPI2_PCS2 0x164 0x3A8 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 0x164 0x3A8 0x55C 0x3 0x0
-#define IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x164 0x3A8 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 0x164 0x3A8 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_22_KPP_ROW06 0x164 0x3A8 0x5A4 0x6 0x0
-#define IOMUXC_GPIO_AD_22_FLEXIO2_D22 0x164 0x3A8 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x164 0x3A8 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 0x168 0x3AC 0x680 0x0 0x0
-#define IOMUXC_GPIO_AD_23_LPSPI2_PCS3 0x168 0x3AC 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 0x168 0x3AC 0x560 0x3 0x0
-#define IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x168 0x3AC 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 0x168 0x3AC 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_23_KPP_COL06 0x168 0x3AC 0x59C 0x6 0x0
-#define IOMUXC_GPIO_AD_23_FLEXIO2_D23 0x168 0x3AC 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x168 0x3AC 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_23_GPIO9_IO22 0x168 0x3AC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_24_LPUART1_TXD 0x16C 0x3B0 0x620 0x0 0x0
-#define IOMUXC_GPIO_AD_24_LPSPI2_SCK 0x16C 0x3B0 0x5E4 0x1 0x0
-#define IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x16C 0x3B0 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_24_ENET_RX_EN 0x16C 0x3B0 0x4B8 0x3 0x0
-#define IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A 0x16C 0x3B0 0x518 0x4 0x1
-#define IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 0x16C 0x3B0 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_24_KPP_ROW05 0x16C 0x3B0 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_24_FLEXIO2_D24 0x16C 0x3B0 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_24_LPI2C4_SCL 0x16C 0x3B0 0x5C4 0x9 0x0
-#define IOMUXC_GPIO_AD_24_GPIO9_IO23 0x16C 0x3B0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_25_GPIO9_IO24 0x170 0x3B4 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_25_LPUART1_RXD 0x170 0x3B4 0x61C 0x0 0x0
-#define IOMUXC_GPIO_AD_25_LPSPI2_PCS0 0x170 0x3B4 0x5DC 0x1 0x0
-#define IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x170 0x3B4 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_25_ENET_RX_ER 0x170 0x3B4 0x4BC 0x3 0x0
-#define IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B 0x170 0x3B4 0x524 0x4 0x1
-#define IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 0x170 0x3B4 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_25_KPP_COL05 0x170 0x3B4 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_25_FLEXIO2_D25 0x170 0x3B4 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_25_LPI2C4_SDA 0x170 0x3B4 0x5C8 0x9 0x0
-
-#define IOMUXC_GPIO_AD_26_LPUART1_CTS_B 0x174 0x3B8 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_26_LPSPI2_SOUT 0x174 0x3B8 0x5EC 0x1 0x0
-#define IOMUXC_GPIO_AD_26_SEMC_CSX01 0x174 0x3B8 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_26_ENET_RX_DATA00 0x174 0x3B8 0x4B0 0x3 0x0
-#define IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A 0x174 0x3B8 0x51C 0x4 0x1
-#define IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 0x174 0x3B8 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_26_KPP_ROW04 0x174 0x3B8 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_26_FLEXIO2_D26 0x174 0x3B8 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_26_ENET_QOS_MDC 0x174 0x3B8 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_26_GPIO9_IO25 0x174 0x3B8 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_26_USDHC2_CD_B 0x174 0x3B8 0x6D0 0xB 0x1
-
-#define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0x0
-#define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0x0
-#define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 0x1
-#define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 0x1
-#define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_27_USDHC2_WP 0x178 0x3BC 0x6D4 0xB 0x1
-
-#define IOMUXC_GPIO_AD_28_GPIO9_IO27 0x17C 0x3C0 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_28_USDHC2_VSELECT 0x17C 0x3C0 0x0 0xB 0x0
-#define IOMUXC_GPIO_AD_28_LPSPI1_SCK 0x17C 0x3C0 0x5D0 0x0 0x1
-#define IOMUXC_GPIO_AD_28_LPUART5_TXD 0x17C 0x3C0 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_28_SEMC_CSX03 0x17C 0x3C0 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_28_ENET_TX_EN 0x17C 0x3C0 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A 0x17C 0x3C0 0x520 0x4 0x1
-#define IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 0x17C 0x3C0 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_28_KPP_ROW03 0x17C 0x3C0 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_28_FLEXIO2_D28 0x17C 0x3C0 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x17C 0x3C0 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x180 0x3C4 0x5CC 0x0 0x1
-#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x180 0x3C4 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x180 0x3C4 0x4A8 0x2 0x0
-#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x180 0x3C4 0x4C0 0x3 0x0
-#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x180 0x3C4 0x52C 0x4 0x1
-#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x180 0x3C4 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_29_KPP_COL03 0x180 0x3C4 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_29_FLEXIO2_D29 0x180 0x3C4 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x180 0x3C4 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_29_GPIO9_IO28 0x180 0x3C4 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_29_USDHC2_RESET_B 0x180 0x3C4 0x0 0xB 0x0
-
-#define IOMUXC_GPIO_AD_30_LPSPI1_SOUT 0x184 0x3C8 0x5D8 0x0 0x1
-#define IOMUXC_GPIO_AD_30_USB_OTG2_OC 0x184 0x3C8 0x6B8 0x1 0x1
-#define IOMUXC_GPIO_AD_30_FLEXCAN2_TX 0x184 0x3C8 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_30_ENET_TX_DATA00 0x184 0x3C8 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_30_LPUART3_TXD 0x184 0x3C8 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x184 0x3C8 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x184 0x3C8 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x184 0x3C8 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x184 0x3C8 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x184 0x3C8 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x188 0x3CC 0x5D4 0x0 0x1
-#define IOMUXC_GPIO_AD_31_USB_OTG2_PWR 0x188 0x3CC 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_31_FLEXCAN2_RX 0x188 0x3CC 0x49C 0x2 0x1
-#define IOMUXC_GPIO_AD_31_ENET_TX_DATA01 0x188 0x3CC 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_31_LPUART3_RXD 0x188 0x3CC 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x188 0x3CC 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_31_KPP_COL02 0x188 0x3CC 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x188 0x3CC 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x188 0x3CC 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x188 0x3CC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x18C 0x3D0 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_32_LPI2C1_SCL 0x18C 0x3D0 0x5AC 0x0 0x1
-#define IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID 0x18C 0x3D0 0x6C4 0x1 0x1
-#define IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY 0x18C 0x3D0 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_32_ENET_MDC 0x18C 0x3D0 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x18C 0x3D0 0x6C8 0x4 0x0
-#define IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 0x18C 0x3D0 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_32_KPP_ROW01 0x18C 0x3D0 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_32_LPUART10_TXD 0x18C 0x3D0 0x628 0x8 0x1
-#define IOMUXC_GPIO_AD_32_ENET_1G_MDC 0x18C 0x3D0 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_AD_33_LPI2C1_SDA 0x190 0x3D4 0x5B0 0x0 0x1
-#define IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID 0x190 0x3D4 0x6C0 0x1 0x1
-#define IOMUXC_GPIO_AD_33_XBAR1_INOUT17 0x190 0x3D4 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_33_ENET_MDIO 0x190 0x3D4 0x4AC 0x3 0x1
-#define IOMUXC_GPIO_AD_33_USDHC1_WP 0x190 0x3D4 0x6CC 0x4 0x0
-#define IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 0x190 0x3D4 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_33_KPP_COL01 0x190 0x3D4 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_33_LPUART10_RXD 0x190 0x3D4 0x624 0x8 0x1
-#define IOMUXC_GPIO_AD_33_ENET_1G_MDIO 0x190 0x3D4 0x4C8 0x9 0x3
-#define IOMUXC_GPIO_AD_33_GPIO10_IO00 0x190 0x3D4 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x194 0x3D8 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_34_USB_OTG1_PWR 0x194 0x3D8 0x0 0x1 0x0
-#define IOMUXC_GPIO_AD_34_XBAR1_INOUT18 0x194 0x3D8 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN 0x194 0x3D8 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0x194 0x3D8 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 0x194 0x3D8 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_34_KPP_ROW00 0x194 0x3D8 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_34_LPUART10_CTS_B 0x194 0x3D8 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_34_WDOG1_ANY 0x194 0x3D8 0x0 0x9 0x0
-#define IOMUXC_GPIO_AD_34_GPIO10_IO01 0x194 0x3D8 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_AD_35_GPIO10_IO02 0x198 0x3DC 0x0 0xA 0x0
-#define IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x0 0x0
-#define IOMUXC_GPIO_AD_35_USB_OTG1_OC 0x198 0x3DC 0x6BC 0x1 0x1
-#define IOMUXC_GPIO_AD_35_XBAR1_INOUT19 0x198 0x3DC 0x0 0x2 0x0
-#define IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x3 0x0
-#define IOMUXC_GPIO_AD_35_USDHC1_RESET_B 0x198 0x3DC 0x0 0x4 0x0
-#define IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 0x198 0x3DC 0x0 0x5 0x0
-#define IOMUXC_GPIO_AD_35_KPP_COL00 0x198 0x3DC 0x0 0x6 0x0
-#define IOMUXC_GPIO_AD_35_LPUART10_RTS_B 0x198 0x3DC 0x0 0x8 0x0
-#define IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x198 0x3DC 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x19C 0x3E0 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x19C 0x3E0 0x6D8 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x19C 0x3E0 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x19C 0x3E0 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x19C 0x3E0 0x0 0x6 0x0
-#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x19C 0x3E0 0x5A8 0x8 0x1
-#define IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 0x19C 0x3E0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x1A0 0x3E4 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x1A0 0x3E4 0x6DC 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x1A0 0x3E4 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x1A0 0x3E4 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x1A0 0x3E4 0x58C 0x6 0x1
-#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x1A0 0x3E4 0x5A0 0x8 0x1
-#define IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 0x1A0 0x3E4 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 0x1A4 0x3E8 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x1A4 0x3E8 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x1A4 0x3E8 0x6E0 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x1A4 0x3E8 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x1A4 0x3E8 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x1A4 0x3E8 0x57C 0x6 0x1
-#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x1A4 0x3E8 0x5A4 0x8 0x1
-#define IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x1A4 0x3E8 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x1A8 0x3EC 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x1A8 0x3EC 0x6E4 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x1A8 0x3EC 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x1A8 0x3EC 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x1A8 0x3EC 0x580 0x6 0x1
-#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x1A8 0x3EC 0x59C 0x8 0x1
-#define IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x1A8 0x3EC 0x0 0x9 0x0
-#define IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 0x1A8 0x3EC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x1AC 0x3F0 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x1AC 0x3F0 0x6E8 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x1AC 0x3F0 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x1AC 0x3F0 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x1AC 0x3F0 0x584 0x6 0x1
-#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x1AC 0x3F0 0x0 0x8 0x0
-#define IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x1AC 0x3F0 0x0 0x9 0x0
-#define IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 0x1AC 0x3F0 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 0x1B0 0x3F4 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x1B0 0x3F4 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x1B0 0x3F4 0x6EC 0x2 0x1
-#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x1B0 0x3F4 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x1B0 0x3F4 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x1B0 0x3F4 0x588 0x6 0x1
-#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x1B0 0x3F4 0x0 0x8 0x0
-#define IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x1B0 0x3F4 0x0 0x9 0x0
-
-#define IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 0x1B4 0x3F8 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 0x1B4 0x3F8 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x1B4 0x3F8 0x570 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN 0x1B4 0x3F8 0x4E0 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_00_LPUART9_TXD 0x1B4 0x3F8 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK 0x1B4 0x3F8 0x610 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x1B4 0x3F8 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 0x1B8 0x3FC 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x1B8 0x3FC 0x56C 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x1B8 0x3FC 0x4CC 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_01_LPUART9_RXD 0x1B8 0x3FC 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 0x1B8 0x3FC 0x60C 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x1B8 0x3FC 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 0x1B8 0x3FC 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 0x1BC 0x400 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 0x1BC 0x400 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x1BC 0x400 0x568 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x1BC 0x400 0x4D0 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B 0x1BC 0x400 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT 0x1BC 0x400 0x618 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x1BC 0x400 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 0x1C0 0x404 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 0x1C0 0x404 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x1C0 0x404 0x564 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x1C0 0x404 0x4D4 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B 0x1C0 0x404 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN 0x1C0 0x404 0x614 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x1C0 0x404 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SD_B2_04_USDHC2_CLK 0x1C4 0x408 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x1C4 0x408 0x578 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x1C4 0x408 0x4D8 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x1C4 0x408 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 0x1C4 0x408 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x1C4 0x408 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 0x1C4 0x408 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 0x1C8 0x40C 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_05_USDHC2_CMD 0x1C8 0x40C 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x1C8 0x40C 0x550 0x1 0x2
-#define IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x1C8 0x40C 0x4DC 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x1C8 0x40C 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 0x1C8 0x40C 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x1C8 0x40C 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 0x1CC 0x410 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B 0x1CC 0x410 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x1CC 0x410 0x0 0x1 0x0
-#define IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x1CC 0x410 0x0 0x2 0x0
-#define IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 0x1CC 0x410 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 0x1CC 0x410 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x1CC 0x410 0x0 0x5 0x0
-
-#define IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE 0x1D0 0x414 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x1D0 0x414 0x574 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x1D0 0x414 0x0 0x2 0x0
-#define IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B 0x1D0 0x414 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 0x1D0 0x414 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x1D0 0x414 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x1D0 0x414 0x5E4 0x6 0x1
-#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x1D0 0x414 0x0 0x8 0x0
-#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x1D0 0x414 0x4A0 0x9 0x1
-#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x1D0 0x414 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x1D4 0x418 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 0x1D4 0x418 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x1D4 0x418 0x554 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x1D4 0x418 0x0 0x2 0x0
-#define IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B 0x1D4 0x418 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 0x1D4 0x418 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x1D4 0x418 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 0x1D4 0x418 0x5DC 0x6 0x1
-
-#define IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 0x1D8 0x41C 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 0x1D8 0x41C 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x1D8 0x41C 0x558 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x1D8 0x41C 0x0 0x2 0x0
-#define IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B 0x1D8 0x41C 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 0x1D8 0x41C 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x1D8 0x41C 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT 0x1D8 0x41C 0x5EC 0x6 0x1
-
-#define IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 0x1DC 0x420 0x0 0xA 0x0
-#define IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 0x1DC 0x420 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x1DC 0x420 0x55C 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN 0x1DC 0x420 0x0 0x2 0x0
-#define IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B 0x1DC 0x420 0x0 0x3 0x0
-#define IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 0x1DC 0x420 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x1DC 0x420 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN 0x1DC 0x420 0x5E8 0x6 0x1
-
-#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x1E0 0x424 0x0 0x0 0x0
-#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x1E0 0x424 0x560 0x1 0x1
-#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x1E0 0x424 0x4E8 0x2 0x1
-#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x1E0 0x424 0x4C4 0x3 0x1
-#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x1E0 0x424 0x0 0x4 0x0
-#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x1E0 0x424 0x0 0x5 0x0
-#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x1E0 0x424 0x5E0 0x6 0x1
-#define IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 0x1E0 0x424 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x1E4 0x428 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x1E4 0x428 0x4E0 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x1E4 0x428 0x63C 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x1E4 0x428 0x6F0 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x1E4 0x428 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x1E4 0x428 0x4F8 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x1E4 0x428 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x1E8 0x42C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x1E8 0x42C 0x4CC 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x1E8 0x42C 0x4E4 0x2 0x1
-#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x1E8 0x42C 0x640 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x1E8 0x42C 0x6F4 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x1E8 0x42C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x1E8 0x42C 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x1E8 0x42C 0x4FC 0x9 0x0
-#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x1E8 0x42C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 0x1EC 0x430 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x1EC 0x430 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x1EC 0x430 0x4D0 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL 0x1EC 0x430 0x5BC 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x1EC 0x430 0x644 0x3 0x1
-#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x1EC 0x430 0x6F8 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x1EC 0x430 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x1EC 0x430 0x4F0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x1EC 0x430 0x620 0x9 0x1
-
-#define IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x1F0 0x434 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x1F0 0x434 0x4D4 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA 0x1F0 0x434 0x5C0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x1F0 0x434 0x648 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x1F0 0x434 0x6FC 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x1F0 0x434 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x1F0 0x434 0x4F4 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x1F0 0x434 0x61C 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x1F0 0x434 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x1F4 0x438 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x1F4 0x438 0x4D8 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD 0x1F4 0x438 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x1F4 0x438 0x64C 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x1F4 0x438 0x700 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x1F4 0x438 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x1F4 0x438 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x1F4 0x438 0x600 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x1F4 0x438 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 0x1F8 0x43C 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x1F8 0x43C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x1F8 0x43C 0x4DC 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B 0x1F8 0x43C 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x1F8 0x43C 0x650 0x3 0x1
-#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x1F8 0x43C 0x704 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x1F8 0x43C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x1F8 0x43C 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x1F8 0x43C 0x604 0x9 0x1
-
-#define IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x1FC 0x440 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x1FC 0x440 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD 0x1FC 0x440 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0 0x1FC 0x440 0x654 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32 0x1FC 0x440 0x708 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x1FC 0x440 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 0x1FC 0x440 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x1FC 0x440 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT 0x1FC 0x440 0x608 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 0x1FC 0x440 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x200 0x444 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x200 0x444 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B 0x200 0x444 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1 0x200 0x444 0x658 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33 0x200 0x444 0x70C 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x200 0x444 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 0x200 0x444 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x200 0x444 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 0x200 0x444 0x5F0 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 0x200 0x444 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 0x204 0x448 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x204 0x448 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x204 0x448 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B 0x204 0x448 0x6C8 0x2 0x1
-#define IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2 0x204 0x448 0x65C 0x3 0x1
-#define IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34 0x204 0x448 0x710 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x204 0x448 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 0x204 0x448 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x204 0x448 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 0x204 0x448 0x5F4 0x9 0x1
-
-#define IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x208 0x44C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x208 0x44C 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B1_09_USDHC1_WP 0x208 0x44C 0x6CC 0x2 0x1
-#define IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0 0x208 0x44C 0x660 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35 0x208 0x44C 0x714 0x4 0x1
-#define IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x208 0x44C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 0x208 0x44C 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x208 0x44C 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 0x208 0x44C 0x5F8 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 0x208 0x44C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x20C 0x450 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x20C 0x450 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B 0x20C 0x450 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1 0x20C 0x450 0x664 0x3 0x2
-#define IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36 0x20C 0x450 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x20C 0x450 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 0x20C 0x450 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x20C 0x450 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 0x20C 0x450 0x5FC 0x9 0x1
-#define IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 0x20C 0x450 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x210 0x454 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x210 0x454 0x4E8 0x1 0x2
-#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x210 0x454 0x4C4 0x2 0x2
-#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x210 0x454 0x668 0x3 0x1
-#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x210 0x454 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x210 0x454 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x210 0x454 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x210 0x454 0x4A4 0x8 0x0
-#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x210 0x454 0x4A0 0x9 0x2
-#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x210 0x454 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x214 0x458 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x214 0x458 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_00_WDOG1_B 0x214 0x458 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT 0x214 0x458 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x214 0x458 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x214 0x458 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x214 0x458 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 0x214 0x458 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x214 0x458 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x218 0x45C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT 0x218 0x45C 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_01_MQS_LEFT 0x218 0x45C 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_01_WDOG2_B 0x218 0x45C 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x218 0x45C 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x218 0x45C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 0x218 0x45C 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B 0x218 0x45C 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x218 0x45C 0x0 0x9 0x0
-#define IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 0x218 0x45C 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 0x21C 0x460 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x21C 0x460 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x21C 0x460 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x21C 0x460 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x21C 0x460 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x21C 0x460 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x21C 0x460 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x21C 0x460 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x21C 0x460 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 0x220 0x464 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x220 0x464 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x220 0x464 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x220 0x464 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x220 0x464 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x220 0x464 0x66C 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x220 0x464 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x220 0x464 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x220 0x464 0x0 0x8 0x0
-
-#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x224 0x468 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x224 0x468 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x224 0x468 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x224 0x468 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x224 0x468 0x678 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x224 0x468 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x224 0x468 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x224 0x468 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 0x224 0x468 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x228 0x46C 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x228 0x46C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x228 0x46C 0x4C0 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x228 0x46C 0x4A8 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x228 0x46C 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x228 0x46C 0x670 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x228 0x46C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x228 0x46C 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x228 0x46C 0x4A4 0x8 0x1
-
-#define IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 0x22C 0x470 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x22C 0x470 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x22C 0x470 0x4B0 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x22C 0x470 0x630 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x22C 0x470 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x22C 0x470 0x674 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x22C 0x470 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x22C 0x470 0x4F0 0x8 0x1
-
-#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x230 0x474 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x230 0x474 0x4B4 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x230 0x474 0x62C 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x230 0x474 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x230 0x474 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x230 0x474 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x230 0x474 0x4F4 0x8 0x1
-#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x230 0x474 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x234 0x478 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x234 0x478 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x234 0x478 0x4B8 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x234 0x478 0x638 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x234 0x478 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x234 0x478 0x67C 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x234 0x478 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x234 0x478 0x4F8 0x8 0x1
-#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x234 0x478 0x620 0x9 0x2
-
-#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 0x1
-#define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 0x1
-#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 0x2
-
-#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x23C 0x480 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x23C 0x480 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x23C 0x480 0x6A8 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x23C 0x480 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x23C 0x480 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x23C 0x480 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x23C 0x480 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x23C 0x480 0x5BC 0x6 0x1
-#define IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x23C 0x480 0x4FC 0x8 0x2
-#define IOMUXC_GPIO_DISP_B2_10_SPDIF_IN 0x23C 0x480 0x6B4 0x9 0x2
-
-#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x240 0x484 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x240 0x484 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x240 0x484 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x240 0x484 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x240 0x484 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x240 0x484 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x240 0x484 0x5C0 0x6 0x1
-#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x240 0x484 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x240 0x484 0x0 0x9 0x0
-#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x240 0x484 0x0 0xA 0x0
-
-#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x244 0x488 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x244 0x488 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x244 0x488 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x244 0x488 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B 0x244 0x488 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40 0x244 0x488 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x244 0x488 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL 0x244 0x488 0x5C4 0x6 0x1
-#define IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL 0x244 0x488 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x244 0x488 0x610 0x9 0x1
-
-#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x248 0x48C 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x248 0x48C 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x248 0x48C 0x0 0x1 0x0
-#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x248 0x48C 0x498 0x2 0x1
-#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x248 0x48C 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x248 0x48C 0x4A8 0x4 0x2
-#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x248 0x48C 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x248 0x48C 0x5C8 0x6 0x1
-#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x248 0x48C 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN 0x248 0x48C 0x614 0x9 0x1
-
-#define IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x24C 0x490 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX 0x24C 0x490 0x0 0x6 0x0
-#define IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x24C 0x490 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT 0x24C 0x490 0x618 0x9 0x1
-#define IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 0x24C 0x490 0x0 0xA 0x0
-#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x24C 0x490 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x24C 0x490 0x6AC 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x24C 0x490 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x24C 0x490 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x24C 0x490 0x4C4 0x4 0x3
-
-#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x250 0x494 0x0 0x0 0x0
-#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x250 0x494 0x6B0 0x1 0x1
-#define IOMUXC_GPIO_DISP_B2_15_WDOG1_B 0x250 0x494 0x0 0x2 0x0
-#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x250 0x494 0x0 0x3 0x0
-#define IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x250 0x494 0x0 0x4 0x0
-#define IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x250 0x494 0x0 0x5 0x0
-#define IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX 0x250 0x494 0x498 0x6 0x2
-#define IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x250 0x494 0x0 0x8 0x0
-#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x250 0x494 0x60C 0x9 0x1
-#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x250 0x494 0x0 0xA 0x0
-
-#endif /* _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H */
diff --git a/arch/arm/boot/dts/nxp/vf/Makefile b/arch/arm/boot/dts/nxp/vf/Makefile
index 0a4a7f9dd43e..1733506c0c72 100644
--- a/arch/arm/boot/dts/nxp/vf/Makefile
+++ b/arch/arm/boot/dts/nxp/vf/Makefile
@@ -3,9 +3,7 @@ dtb-$(CONFIG_SOC_VF610) += \
vf500-colibri-eval-v3.dtb \
vf610-bk4.dtb \
vf610-colibri-eval-v3.dtb \
- vf610m4-colibri.dtb \
vf610-cosmic.dtb \
- vf610m4-cosmic.dtb \
vf610-twr.dtb \
vf610-zii-cfu1.dtb \
vf610-zii-dev-rev-b.dtb \
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
deleted file mode 100644
index 86d32f54c250..000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Device tree for Colibri VF61 Cortex-M4 support
- *
- * Copyright (C) 2015 Stefan Agner
- */
-
-/dts-v1/;
-#include "vf610m4.dtsi"
-
-/ {
- model = "VF610 Cortex-M4";
- compatible = "fsl,vf610m4";
-
- chosen {
- bootargs = "clk_ignore_unused init=/linuxrc rw";
- stdout-path = "serial2:115200";
- };
-
- memory@8c000000 {
- device_type = "memory";
- reg = <0x8c000000 0x3000000>;
- };
-};
-
-&gpio0 {
- status = "disabled";
-};
-
-&gpio1 {
- status = "disabled";
-};
-
-&gpio2 {
- status = "disabled";
-};
-
-&gpio3 {
- status = "disabled";
-};
-
-&gpio4 {
- status = "disabled";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- VF610_PAD_PTD0__UART2_TX 0x21a2
- VF610_PAD_PTD1__UART2_RX 0x21a1
- VF610_PAD_PTD2__UART2_RTS 0x21a2
- VF610_PAD_PTD3__UART2_CTS 0x21a1
- >;
- };
-};
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
deleted file mode 100644
index 454b484368cb..000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Device tree for Cosmic+ VF6xx Cortex-M4 support
- *
- * Copyright (C) 2015
- *
- * Based on vf610m4 Colibri
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "vf610m4.dtsi"
-
-/ {
- model = "VF610 Cortex-M4";
- compatible = "fsl,vf610m4";
-};
-
-&gpio0 {
- status = "disabled";
-};
-
-&gpio1 {
- status = "disabled";
-};
-
-&gpio2 {
- status = "disabled";
-};
-
-&gpio3 {
- status = "disabled";
-};
-
-&gpio4 {
- status = "disabled";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- VF610_PAD_PTA20__UART3_TX 0x21a2
- VF610_PAD_PTA21__UART3_RX 0x21a1
- >;
- };
-};
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
deleted file mode 100644
index 648d219e1d0e..000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Device tree for VF6xx Cortex-M4 support
- *
- * Copyright (C) 2015 Stefan Agner
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../../armv7-m.dtsi"
-#include "vfxxx.dtsi"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
- aliases { };
-};
-
-&mscm_ir {
- interrupt-parent = <&nvic>;
-};
-
-&nvic {
- arm,num-irq-priority-bits = <4>;
-};
diff --git a/arch/arm/configs/imxrt_defconfig b/arch/arm/configs/imxrt_defconfig
deleted file mode 100644
index 52dba3762996..000000000000
--- a/arch/arm/configs/imxrt_defconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_BPF_SYSCALL=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_MMU is not set
-CONFIG_ARCH_MXC=y
-CONFIG_SOC_IMXRT=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x80000000
-CONFIG_DRAM_SIZE=0x02000000
-CONFIG_BINFMT_FLAT=y
-CONFIG_UEVENT_HELPER=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_IMX_WEIM=y
-CONFIG_LEGACY_PTY_COUNT=2
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_GPIO_MXC=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_DMADEVICES=y
-CONFIG_FSL_EDMA=y
-CONFIG_CLK_IMXRT1050=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_UTF8=y
-CONFIG_EXFAT_FS=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_UTF8=y
diff --git a/arch/arm/configs/vf610m4_defconfig b/arch/arm/configs/vf610m4_defconfig
deleted file mode 100644
index a5609cbfdfb3..000000000000
--- a/arch/arm/configs/vf610m4_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_NAMESPACES=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZ4 is not set
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_MMU is not set
-CONFIG_ARCH_MXC=y
-CONFIG_SOC_VF610=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x8c000000
-CONFIG_FLASH_MEM_BASE=0x8f000000
-CONFIG_FLASH_SIZE=0x01000000
-CONFIG_CMDLINE="console=/dev/ttyLP2"
-CONFIG_XIP_KERNEL=y
-CONFIG_XIP_PHYS_ADDR=0x0f000080
-# CONFIG_SUSPEND is not set
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-# CONFIG_UEVENT_HELPER is not set
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_ALLOW_DEV_COREDUMP is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=4
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_MFD_SYSCON=y
-# CONFIG_HID is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT4_FS=y
-# CONFIG_MISC_FILESYSTEMS is not set
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 77704c6a70ba..cdc1b31fe573 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -2,7 +2,7 @@
menuconfig ARCH_MXC
bool "Freescale i.MX family"
depends on ((ARCH_MULTI_V4T || ARCH_MULTI_V5) && CPU_LITTLE_ENDIAN) || \
- ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
+ ARCH_MULTI_V6_V7
select CLKSRC_IMX_GPT
select GENERIC_IRQ_CHIP
select GPIOLIB
@@ -174,7 +174,7 @@ config SOC_LS1021A
endif
-if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+if ARCH_MULTI_V7
comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
@@ -187,38 +187,23 @@ config SOC_IMX7D_CA7
select HAVE_IMX_SRC
select IMX_GPCV2
-config SOC_IMX7D_CM4
- bool
- select ARMV7M_SYSTICK
-
config SOC_IMX7D
bool "i.MX7 Dual support"
- select SOC_IMX7D_CA7 if ARCH_MULTI_V7
- select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
- select ARM_ERRATA_814220 if ARCH_MULTI_V7
+ select SOC_IMX7D_CA7
+ select ARM_ERRATA_814220
help
This enables support for Freescale i.MX7 Dual processor.
config SOC_IMX7ULP
bool "i.MX7ULP support"
select CLKSRC_IMX_TPM
- select SOC_IMX7D_CA7 if ARCH_MULTI_V7
- select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
+ select SOC_IMX7D_CA7
help
This enables support for Freescale i.MX7 Ultra Low Power processor.
-config SOC_IMXRT
- bool "i.MXRT support (DEPRECATED)"
- depends on ARM_SINGLE_ARMV7M
- select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
- help
- This enables support for Freescale i.MXRT Crossover processor.
-
- This platform is scheduled for removal in early 2027
-
config SOC_VF610
bool "Vybrid Family VF610 support"
- select ARM_GIC if ARCH_MULTI_V7
+ select ARM_GIC
help
This enables support for Freescale Vybrid VF610 processor.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index fa0144f0882d..135079340428 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o
-obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
ifeq ($(CONFIG_SUSPEND),y)
@@ -59,8 +58,6 @@ obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
-obj-$(CONFIG_SOC_IMXRT) += mach-imxrt.o
-
obj-$(CONFIG_SOC_VF610) += mach-vf610.o
obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
diff --git a/arch/arm/mach-imx/mach-imx7d-cm4.c b/arch/arm/mach-imx/mach-imx7d-cm4.c
deleted file mode 100644
index 0800b5891d2a..000000000000
--- a/arch/arm/mach-imx/mach-imx7d-cm4.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
- */
-
-#include <linux/kernel.h>
-#include <asm/v7m.h>
-#include <asm/mach/arch.h>
-
-static const char * const imx7d_cm4_dt_compat[] __initconst = {
- "fsl,imx7d-cm4",
- NULL,
-};
-
-DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
- .dt_compat = imx7d_cm4_dt_compat,
- .restart = armv7m_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imxrt.c b/arch/arm/mach-imx/mach-imxrt.c
deleted file mode 100644
index 2063a3059c84..000000000000
--- a/arch/arm/mach-imx/mach-imxrt.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#include <linux/kernel.h>
-#include <asm/mach/arch.h>
-#include <asm/v7m.h>
-
-static const char *const imxrt_compat[] __initconst = {
- "fsl,imxrt1050",
- NULL
-};
-
-DT_MACHINE_START(IMXRTDT, "IMXRT (Device Tree Support)")
- .dt_compat = imxrt_compat,
- .restart = armv7m_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index 208ff640698d..f77565381097 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -59,7 +59,6 @@ static const char * const vf610_dt_compat[] __initconst = {
"fsl,vf510",
"fsl,vf600",
"fsl,vf610",
- "fsl,vf610m4",
NULL,
};
--
2.53.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 10/14] ARM: lpc18xx: remove entire platform
2026-09-14 14:08 [PATCH v2 00/14] ARM: deprecated platform removal Arnd Bergmann
` (2 preceding siblings ...)
2026-09-14 14:08 ` [PATCH v2 09/14] ARM: imx: remove nommu support Arnd Bergmann
@ 2026-09-14 14:08 ` Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 11/14] ARM: stm32: remove stm32f4/f7/h7 MCU support Arnd Bergmann
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Arnd Bergmann @ 2026-09-14 14:08 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
imx, devicetree, Vladimir Zapolskiy, Linus Walleij
From: Arnd Bergmann <arnd@arndb.de>
The NXP LPC18xx and LPC43xx microcontrollers are the more modern
version of the classic LPC32xx line, but they lack memory management
units.
These microcontrollers all remain in production as of 2026, but
there are no known users running Linux on them.
The platform was marked deprecated in the 7.3-LTS release, which
will remain supported for a few more years.
Remove support for both LPC18xx and LPC43xx.
Cc: Frank Li <Frank.Li@nxp.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: imx@lists.linux.dev
Cc: devicetree@vger.kernel.org
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
I have follow-up patches to remove all the lpc18xx specific
drivers and dt bindings (iio, mtd, phy, watchdog, pwm,
nvmem, reset, rtc, pinctrl, gpio, clk, dma, i2c, uart),
but will post those separately.
---
MAINTAINERS | 12 -
arch/arm/Kconfig | 14 -
arch/arm/Kconfig.debug | 9 -
arch/arm/Makefile | 1 -
arch/arm/boot/dts/nxp/lpc/Makefile | 5 -
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 543 ---------------
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts | 221 -------
.../boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 485 --------------
arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi | 48 --
.../dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 624 ------------------
.../boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 621 -----------------
arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi | 52 --
arch/arm/configs/lpc18xx_defconfig | 158 -----
arch/arm/mach-lpc18xx/Makefile | 2 -
arch/arm/mach-lpc18xx/board-dt.c | 19 -
15 files changed, 2814 deletions(-)
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
delete mode 100644 arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
delete mode 100644 arch/arm/configs/lpc18xx_defconfig
delete mode 100644 arch/arm/mach-lpc18xx/Makefile
delete mode 100644 arch/arm/mach-lpc18xx/board-dt.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 4522bde3f92e..96aba2553cbc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3038,18 +3038,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/dts/lg/
-ARM/LPC18XX ARCHITECTURE
-M: Vladimir Zapolskiy <vz@mleia.com>
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
-F: Documentation/devicetree/bindings/i2c/nxp,lpc1788-i2c.yaml
-F: arch/arm/boot/dts/nxp/lpc/lpc43*
-F: drivers/i2c/busses/i2c-lpc2k.c
-F: drivers/memory/pl172.c
-F: drivers/mtd/spi-nor/controllers/nxp-spifi.c
-F: drivers/rtc/rtc-lpc24xx.c
-N: lpc18xx
-
ARM/LPC32XX SOC SUPPORT
M: Vladimir Zapolskiy <vz@mleia.com>
M: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index de3d9bae33fa..b569052bfba1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -457,20 +457,6 @@ source "arch/arm/mach-zte/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
-# ARMv7-M architecture
-config ARCH_LPC18XX
- bool "NXP LPC18xx/LPC43xx (DEPRECATED)"
- depends on ARM_SINGLE_ARMV7M
- select ARCH_HAS_RESET_CONTROLLER
- select ARM_AMBA
- select CLKSRC_LPC32XX
- select PINCTRL
- help
- Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
- high performance microcontrollers.
-
- This platform is scheduled for removal in early 2027
-
config ARCH_MPS2
bool "ARM MPS2 platform (DEPRECATED)"
depends on ARM_SINGLE_ARMV7M
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 729f5184fba5..4e34ff43ef75 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -511,14 +511,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to UART1 serial port on KEYSTONE2 devices.
- config DEBUG_LPC18XX_UART0
- bool "Kernel low-level debugging via LPC18xx/43xx UART0"
- depends on ARCH_LPC18XX
- select DEBUG_UART_8250
- help
- Say Y here if you want kernel low-level debugging support
- on NXP LPC18xx/43xx UART0.
-
config DEBUG_LPC32XX
bool "Kernel low-level debugging messages via NXP LPC32xx UART"
depends on ARCH_LPC32XX
@@ -1552,7 +1544,6 @@ config DEBUG_UART_PHYS
default 0x40011000 if STM32F4_DEBUG_UART || STM32F7_DEBUG_UART || \
STM32H7_DEBUG_UART
default 0x40028000 if DEBUG_AT91_SAMV7_USART1
- default 0x40081000 if DEBUG_LPC18XX_UART0
default 0x40090000 if DEBUG_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
default 0x42000000 if DEBUG_GEMINI
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f882e8a35167..81dad2a602d9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -185,7 +185,6 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISI) += hisi
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
-machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
diff --git a/arch/arm/boot/dts/nxp/lpc/Makefile b/arch/arm/boot/dts/nxp/lpc/Makefile
index 56b9a0ebb917..3f82628f3ff9 100644
--- a/arch/arm/boot/dts/nxp/lpc/Makefile
+++ b/arch/arm/boot/dts/nxp/lpc/Makefile
@@ -1,9 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_LPC18XX) += \
- lpc4337-ciaa.dtb \
- lpc4350-hitex-eval.dtb \
- lpc4357-ea4357-devkit.dtb \
- lpc4357-myd-lpc4357.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += \
lpc3250-ea3250.dtb \
lpc3250-phy3250.dtb
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
deleted file mode 100644
index 152e98cf0c4e..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * Common base for NXP LPC18xx and LPC43xx devices.
- *
- * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-
-#include "../../armv7-m.dtsi"
-
-#include "dt-bindings/clock/lpc18xx-cgu.h"
-#include "dt-bindings/clock/lpc18xx-ccu.h"
-
-#define LPC_PIN(port, pin) (0x##port * 32 + pin)
-#define LPC_GPIO(port, pin) (port * 32 + pin)
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,cortex-m3";
- device_type = "cpu";
- reg = <0x0>;
- clocks = <&ccu1 CLK_CPU_CORE>;
- };
- };
-
- clocks {
- xtal: xtal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- xtal32: xtal32 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
-
- enet_rx_clk: enet_rx_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "enet_rx_clk";
- };
-
- enet_tx_clk: enet_tx_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "enet_tx_clk";
- };
-
- gp_clkin: gp_clkin {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "gp_clkin";
- };
- };
-
- soc {
- sct_pwm: pwm@40000000 {
- compatible = "nxp,lpc1850-sct-pwm";
- reg = <0x40000000 0x1000>;
- clocks = <&ccu1 CLK_CPU_SCT>;
- clock-names = "pwm";
- resets = <&rgu 37>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- dmac: dma-controller@40002000 {
- compatible = "arm,pl080", "arm,primecell";
- arm,primecell-periphid = <0x00041080>;
- reg = <0x40002000 0x1000>;
- interrupts = <2>;
- clocks = <&ccu1 CLK_CPU_DMA>;
- clock-names = "apb_pclk";
- resets = <&rgu 19>;
- #dma-cells = <2>;
- dma-channels = <8>;
- dma-requests = <16>;
- lli-bus-interface-ahb1;
- lli-bus-interface-ahb2;
- mem-bus-interface-ahb1;
- mem-bus-interface-ahb2;
- memcpy-burst-size = <256>;
- memcpy-bus-width = <32>;
- };
-
- spifi: spi@40003000 {
- compatible = "nxp,lpc1773-spifi";
- reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
- reg-names = "spifi", "flash";
- interrupts = <30>;
- clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
- clock-names = "spifi", "reg";
- #address-cells = <1>;
- #size-cells = <0>;
- resets = <&rgu 53>;
- status = "disabled";
- };
-
- mmcsd: mmc@40004000 {
- compatible = "snps,dw-mshc";
- reg = <0x40004000 0x1000>;
- interrupts = <6>;
- clocks = <&ccu1 CLK_CPU_SDIO>, <&ccu2 CLK_SDIO>;
- clock-names = "biu", "ciu";
- resets = <&rgu 20>;
- status = "disabled";
- };
-
- usb0: usb@40006100 {
- compatible = "nxp,lpc1850-ehci", "generic-ehci";
- reg = <0x40006100 0x100>;
- interrupts = <8>;
- clocks = <&ccu1 CLK_CPU_USB0>;
- resets = <&rgu 17>;
- phys = <&usb0_otg_phy>;
- phy-names = "usb";
- has-transaction-translator;
- status = "disabled";
- };
-
- usb1: usb@40007100 {
- compatible = "nxp,lpc1850-ehci", "generic-ehci";
- reg = <0x40007100 0x100>;
- interrupts = <9>;
- clocks = <&ccu1 CLK_CPU_USB1>;
- resets = <&rgu 18>;
- status = "disabled";
- };
-
- emc: memory-controller@40005000 {
- compatible = "arm,pl172", "arm,primecell";
- reg = <0x40005000 0x1000>;
- clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
- clock-names = "mpmcclk", "apb_pclk";
- resets = <&rgu 21>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0x1c000000 0x1000000
- 1 0 0x1d000000 0x1000000
- 2 0 0x1e000000 0x1000000
- 3 0 0x1f000000 0x1000000>;
- status = "disabled";
- };
-
- lcdc: lcd-controller@40008000 {
- compatible = "arm,pl111", "arm,primecell";
- reg = <0x40008000 0x1000>;
- interrupts = <7>;
- interrupt-names = "combined";
- clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
- clock-names = "clcdclk", "apb_pclk";
- resets = <&rgu 16>;
- status = "disabled";
- };
-
- eeprom: eeprom@4000e000 {
- compatible = "nxp,lpc1857-eeprom";
- reg = <0x4000e000 0x1000>, <0x20040000 0x4000>;
- reg-names = "reg", "mem";
- clocks = <&ccu1 CLK_CPU_EEPROM>;
- clock-names = "eeprom";
- resets = <&rgu 27>;
- interrupts = <4>;
- status = "disabled";
- };
-
- mac: ethernet@40010000 {
- compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
- reg = <0x40010000 0x2000>;
- interrupts = <5>;
- interrupt-names = "macirq";
- clocks = <&ccu1 CLK_CPU_ETHERNET>;
- clock-names = "stmmaceth";
- resets = <&rgu 22>;
- reset-names = "stmmaceth";
- rx-fifo-depth = <256>;
- tx-fifo-depth = <256>;
- snps,pbl = <4>; /* 32 (8x mode) */
- snps,force_thresh_dma_mode;
- status = "disabled";
- };
-
- creg: syscon@40043000 {
- compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
- reg = <0x40043000 0x1000>;
- clocks = <&ccu1 CLK_CPU_CREG>;
- resets = <&rgu 5>;
-
- creg_clk: clock-controller {
- compatible = "nxp,lpc1850-creg-clk";
- clocks = <&xtal32>;
- #clock-cells = <1>;
- };
-
- usb0_otg_phy: phy {
- compatible = "nxp,lpc1850-usb-otg-phy";
- clocks = <&ccu1 CLK_USB0>;
- #phy-cells = <0>;
- };
-
- dmamux: dma-mux {
- compatible = "nxp,lpc1850-dmamux";
- #dma-cells = <3>;
- dma-requests = <64>;
- dma-masters = <&dmac>;
- };
- };
-
- rtc: rtc@40046000 {
- compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
- reg = <0x40046000 0x1000>;
- interrupts = <47>;
- clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
- clock-names = "rtc", "reg";
- };
-
- cgu: clock-controller@40050000 {
- compatible = "nxp,lpc1850-cgu";
- reg = <0x40050000 0x1000>;
- #clock-cells = <1>;
- clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
- };
-
- ccu1: clock-controller@40051000 {
- compatible = "nxp,lpc1850-ccu";
- reg = <0x40051000 0x1000>;
- #clock-cells = <1>;
- clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
- <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
- <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
- <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
- clock-names = "base_apb3_clk", "base_apb1_clk",
- "base_spifi_clk", "base_cpu_clk",
- "base_periph_clk", "base_usb0_clk",
- "base_usb1_clk", "base_spi_clk";
- };
-
- ccu2: clock-controller@40052000 {
- compatible = "nxp,lpc1850-ccu";
- reg = <0x40052000 0x1000>;
- #clock-cells = <1>;
- clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
- <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
- <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
- <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
- clock-names = "base_audio_clk", "base_uart3_clk",
- "base_uart2_clk", "base_uart1_clk",
- "base_uart0_clk", "base_ssp1_clk",
- "base_ssp0_clk", "base_sdio_clk";
- };
-
- rgu: reset-controller@40053000 {
- compatible = "nxp,lpc1850-rgu";
- reg = <0x40053000 0x1000>;
- clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
- clock-names = "delay", "reg";
- #reset-cells = <1>;
- };
-
- watchdog@40080000 {
- compatible = "nxp,lpc1850-wwdt";
- reg = <0x40080000 0x24>;
- interrupts = <49>;
- clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
- clock-names = "wdtclk", "reg";
- };
-
- uart0: serial@40081000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x40081000 0x1000>;
- reg-shift = <2>;
- interrupts = <24>;
- clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 44>;
- dmas = <&dmamux 1 1 2
- &dmamux 2 1 2
- &dmamux 11 2 2
- &dmamux 12 2 2>;
- dma-names = "tx", "rx", "tx", "rx";
- status = "disabled";
- };
-
- uart1: serial@40082000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x40082000 0x1000>;
- reg-shift = <2>;
- interrupts = <25>;
- clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 45>;
- dmas = <&dmamux 3 1 2
- &dmamux 4 1 2>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- ssp0: spi@40083000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x40083000 0x1000>;
- interrupts = <22>;
- clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
- clock-names = "sspclk", "apb_pclk";
- resets = <&rgu 50>;
- dmas = <&dmamux 9 0 2
- &dmamux 10 0 2>;
- dma-names = "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- timer0: timer@40084000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x40084000 0x1000>;
- interrupts = <12>;
- clocks = <&ccu1 CLK_CPU_TIMER0>;
- clock-names = "timerclk";
- resets = <&rgu 32>;
- };
-
- timer1: timer@40085000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x40085000 0x1000>;
- interrupts = <13>;
- clocks = <&ccu1 CLK_CPU_TIMER1>;
- clock-names = "timerclk";
- resets = <&rgu 33>;
- };
-
- pinctrl: pinctrl@40086000 {
- compatible = "nxp,lpc1850-scu";
- reg = <0x40086000 0x1000>;
- clocks = <&ccu1 CLK_CPU_SCU>;
- };
-
- i2c0: i2c@400a1000 {
- compatible = "nxp,lpc1788-i2c";
- reg = <0x400a1000 0x1000>;
- interrupts = <18>;
- clocks = <&ccu1 CLK_APB1_I2C0>;
- resets = <&rgu 48>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@400a4000 {
- compatible = "bosch,c_can";
- reg = <0x400a4000 0x1000>;
- interrupts = <43>;
- clocks = <&ccu1 CLK_APB1_CAN1>;
- resets = <&rgu 54>;
- status = "disabled";
- };
-
- uart2: serial@400c1000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x400c1000 0x1000>;
- reg-shift = <2>;
- interrupts = <26>;
- clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 46>;
- dmas = <&dmamux 5 1 2
- &dmamux 6 1 2>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- uart3: serial@400c2000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x400c2000 0x1000>;
- reg-shift = <2>;
- interrupts = <27>;
- clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 47>;
- dmas = <&dmamux 7 1 2
- &dmamux 8 1 2
- &dmamux 13 3 2
- &dmamux 14 3 2>;
- dma-names = "tx", "rx", "rx", "tx";
- status = "disabled";
- };
-
- timer2: timer@400c3000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x400c3000 0x1000>;
- interrupts = <14>;
- clocks = <&ccu1 CLK_CPU_TIMER2>;
- clock-names = "timerclk";
- resets = <&rgu 34>;
- };
-
- timer3: timer@400c4000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x400c4000 0x1000>;
- interrupts = <15>;
- clocks = <&ccu1 CLK_CPU_TIMER3>;
- clock-names = "timerclk";
- resets = <&rgu 35>;
- };
-
- ssp1: spi@400c5000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x400c5000 0x1000>;
- interrupts = <23>;
- clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
- clock-names = "sspclk", "apb_pclk";
- resets = <&rgu 51>;
- dmas = <&dmamux 11 2 2
- &dmamux 12 2 2
- &dmamux 3 3 2
- &dmamux 4 3 2
- &dmamux 5 2 2
- &dmamux 6 2 2
- &dmamux 13 2 2
- &dmamux 14 2 2>;
- dma-names = "rx", "tx", "tx", "rx",
- "tx", "rx", "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@400e0000 {
- compatible = "nxp,lpc1788-i2c";
- reg = <0x400e0000 0x1000>;
- interrupts = <19>;
- clocks = <&ccu1 CLK_APB3_I2C1>;
- resets = <&rgu 49>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- dac: dac@400e1000 {
- compatible = "nxp,lpc1850-dac";
- reg = <0x400e1000 0x1000>;
- interrupts = <0>;
- clocks = <&ccu1 CLK_APB3_DAC>;
- resets = <&rgu 42>;
- status = "disabled";
- };
-
- can0: can@400e2000 {
- compatible = "bosch,c_can";
- reg = <0x400e2000 0x1000>;
- interrupts = <51>;
- clocks = <&ccu1 CLK_APB3_CAN0>;
- resets = <&rgu 55>;
- status = "disabled";
- };
-
- adc0: adc@400e3000 {
- compatible = "nxp,lpc1850-adc";
- reg = <0x400e3000 0x1000>;
- interrupts = <17>;
- clocks = <&ccu1 CLK_APB3_ADC0>;
- resets = <&rgu 40>;
- status = "disabled";
- };
-
- adc1: adc@400e4000 {
- compatible = "nxp,lpc1850-adc";
- reg = <0x400e4000 0x1000>;
- interrupts = <21>;
- clocks = <&ccu1 CLK_APB3_ADC1>;
- resets = <&rgu 41>;
- status = "disabled";
- };
-
- gpio: gpio@400f4000 {
- compatible = "nxp,lpc1850-gpio";
- reg = <0x400f4000 0x4000>;
- clocks = <&ccu1 CLK_CPU_GPIO>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
- <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>,
- <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>,
- <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>,
- <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>,
- <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>,
- <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
- <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
- <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>,
- <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>,
- <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>,
- <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>,
- <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
- <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
- <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>,
- <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>,
- <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>,
- <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>,
- <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>,
- <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>,
- <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>,
- <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>,
- <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>,
- <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>,
- <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>,
- <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>,
- <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>,
- <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>,
- <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>,
- <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>,
- <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>,
- <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>,
- <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>,
- <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>,
- <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>,
- <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>,
- <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
- <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>,
- <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>,
- <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
- };
- };
-};
-
-&nvic {
- arm,num-irq-priority-bits = <3>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
deleted file mode 100644
index 5ff43c825944..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar)
- *
- * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- */
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4357.dtsi"
-
-#include "dt-bindings/gpio/gpio.h"
-
-/ {
- model = "CIAA NXP LPC4337";
- compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350";
-
- aliases {
- serial0 = &uart2;
- serial1 = &uart3;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200 earlyprintk";
- stdout-path = &uart2;
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x0800000>; /* 8 MB */
- };
-};
-
-&pinctrl {
- enet_rmii_pins: enet-rmii-pins {
- enet_rmii_rxd_cfg {
- pins = "p1_15", "p0_0";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_txd_cfg {
- pins = "p1_18", "p1_20";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_rx_dv_cfg {
- pins = "p1_16";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_tx_en_cfg {
- pins = "p0_1";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_ref_clk_cfg {
- pins = "p1_19";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdc_cfg {
- pins = "p7_7";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- ssp_pins: ssp-pins {
- ssp1_cs_cfg {
- pins = "p6_7";
- function = "gpio";
- bias-pull-up;
- bias-disable;
- };
-
- ssp1_miso_mosi_cfg {
- pins = "p1_3", "p1_4";
- function = "ssp1";
- slew-rate = <1>;
- bias-pull-down;
- input-enable;
- input-schmitt-disable;
- };
-
- ssp1_sck_cfg {
- pins = "pf_4";
- function = "ssp1";
- slew-rate = <1>;
- bias-disable;
- };
- };
-
- uart2_pins: uart2-pins {
- uart2_rx_cfg {
- pins = "p7_2";
- function = "uart2";
- bias-disable;
- input-enable;
- };
-
- uart2_tx_cfg {
- pins = "p7_1";
- function = "uart2";
- bias-disable;
- };
- };
-
- uart3_pins: uart3-pins {
- uart3_rx_cfg {
- pins = "p2_4";
- function = "uart3";
- bias-disable;
- input-enable;
- };
-
- uart3_tx_cfg {
- pins = "p2_3";
- function = "uart3";
- bias-disable;
- };
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <50000000>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-
- eeprom@50 {
- compatible = "microchip,24c512", "atmel,24c512";
- reg = <0x50>;
- };
-
- eeprom@51 {
- compatible = "microchip,24c02", "atmel,24c02";
- reg = <0x51>;
- };
-
- eeprom@54 {
- compatible = "microchip,24c512", "atmel,24c512";
- reg = <0x54>;
- };
-};
-
-&mac {
- status = "okay";
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_rmii_pins>;
-};
-
-&sct_pwm {
- status = "okay";
-};
-
-&ssp1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ssp_pins>;
- cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>;
- num-cs = <1>;
-};
-
-&uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
deleted file mode 100644
index 18f757c56905..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
+++ /dev/null
@@ -1,485 +0,0 @@
-/*
- * Hitex LPC4350 Evaluation Board
- *
- * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4350.dtsi"
-
-#include "dt-bindings/input/input.h"
-#include "dt-bindings/gpio/gpio.h"
-
-/ {
- model = "Hitex LPC4350 Evaluation Board";
- compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- };
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x800000>; /* 8 MB */
- };
-
- pca_buttons {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
- autorepeat;
-
- button-0 {
- label = "joy:right";
- linux,code = <KEY_RIGHT>;
- gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>;
- };
-
- button-1 {
- label = "joy:up";
- linux,code = <KEY_UP>;
- gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>;
- };
-
-
- button-2 {
- label = "joy:enter";
- linux,code = <KEY_ENTER>;
- gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>;
- };
-
- button-3 {
- label = "joy:left";
- linux,code = <KEY_LEFT>;
- gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>;
- };
-
- button-4 {
- label = "joy:down";
- linux,code = <KEY_DOWN>;
- gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>;
- };
-
- button-5 {
- label = "user:sw3";
- linux,code = <KEY_F1>;
- gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>;
- };
-
- button-6 {
- label = "user:sw4";
- linux,code = <KEY_F2>;
- gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>;
- };
-
- button-7 {
- label = "user:sw5";
- linux,code = <KEY_F3>;
- gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>;
- };
- };
-
- pca_leds {
- compatible = "gpio-leds";
-
- led0 {
- label = "ext:led0";
- gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
-
- led1 {
- label = "ext:led1";
- gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>;
- };
-
- led2 {
- label = "ext:led2";
- gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>;
- };
-
- led3 {
- label = "ext:led3";
- gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>;
- };
- };
-
- vcc: vcc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "3v3io";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&pinctrl {
- adc1_pins: adc1-pins {
- adc1_pins_cfg {
- pins = "pf_9";
- function = "adc";
- input-disable;
- bias-disable;
- };
- };
-
- emc_pins: emc-pins {
- emc_addr0_23_cfg {
- pins = "p2_9", "p2_10", "p2_11", "p2_12",
- "p2_13", "p1_0", "p1_1", "p1_2",
- "p2_8", "p2_7", "p2_6", "p2_2",
- "p2_1", "p2_0", "p6_8", "p6_7",
- "pd_16", "pd_15", "pe_0", "pe_1",
- "pe_2", "pe_3", "pe_4", "pa_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_data0_15_cfg {
- pins = "p1_7", "p1_8", "p1_9", "p1_10",
- "p1_11", "p1_12", "p1_13", "p1_14",
- "p5_4", "p5_5", "p5_6", "p5_7",
- "p5_0", "p5_1", "p5_2", "p5_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_we_oe_cfg {
- pins = "p1_6", "p1_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_bls0_3_cfg {
- pins = "p1_4", "p6_6", "pd_13", "pd_10";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_cs0_cs2_cfg {
- pins = "p1_5", "pd_12";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dqm0_3_cfg {
- pins = "p6_12", "p6_10", "pd_0", "pe_13";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_ras_cas_cfg {
- pins = "p6_5", "p6_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dycs0_cfg {
- pins = "p6_9";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_cke_cfg {
- pins = "p6_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_clock_cfg {
- pins = "clk0", "clk1", "clk2", "clk3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- enet_mii_pins: enet-mii-pins {
- enet_mii_rxd0_3_cfg {
- pins = "p1_15", "p0_0", "p9_3", "p9_2";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mii_txd0_3_cfg {
- pins = "p1_18", "p1_20", "p9_4", "p9_5";
- function = "enet";
- bias-disable;
- };
-
- enet_mii_crs_col_cfg {
- pins = "p9_0", "p9_6";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mii_rx_clk_dv_er_cfg {
- pins = "pc_0", "p1_16", "p9_1";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mii_tx_clk_en_cfg {
- pins = "p1_19", "p0_1";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mdc_cfg {
- pins = "pc_1";
- function = "enet";
- bias-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- spifi_pins: spifi-pins {
- spifi_clk_cfg {
- pins = "p3_3";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_mosi_miso_sio2_3_cfg {
- pins = "p3_7", "p3_6", "p3_5", "p3_4";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_cs_cfg {
- pins = "p3_8";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- uart0_pins: uart0-pins {
- uart0_rx_cfg {
- pins = "pf_11";
- function = "uart0";
- input-schmitt-disable;
- bias-disable;
- input-enable;
- };
-
- uart0_tx_cfg {
- pins = "pf_10";
- function = "uart0";
- bias-pull-down;
- };
- };
-};
-
-&adc1 {
- status = "okay";
- vref-supply = <&vcc>;
- pinctrl-names = "default";
- pinctrl-0 = <&adc1_pins>;
-};
-
-&emc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&emc_pins>;
-
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <0>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <0>;
- mpmc,read-access-delay = <70>;
- mpmc,page-mode-read-delay = <70>;
-
- flash@0,0 {
- compatible = "sst,sst39vf320", "cfi-flash";
- reg = <0 0 0x400000>;
- bank-width = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootloader";
- reg = <0x000000 0x040000>; /* 256 KiB */
- };
-
- partition@1 {
- label = "kernel";
- reg = <0x040000 0x2C0000>; /* 2.75 MiB */
- };
-
- partition@2 {
- label = "rootfs";
- reg = <0x300000 0x100000>; /* 1 MiB */
- };
- };
- };
-
- cs2 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <2>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <30>;
- mpmc,read-access-delay = <90>;
- mpmc,page-mode-read-delay = <55>;
- mpmc,write-access-delay = <55>;
- mpmc,turn-round-delay = <55>;
-
- ext_sram: sram@2,0 {
- compatible = "mmio-sram";
- reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 2 0 0x80000>;
- };
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <25000000>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-
- /* NXP SE97BTP with temperature sensor + eeprom */
- sensor@18 {
- compatible = "nxp,se97", "jedec,jc-42.4-temp";
- reg = <0x18>;
- };
-
- eeprom@50 {
- compatible = "nxp,24c02", "atmel,24c02";
- reg = <0x50>;
- };
-
- pca_gpio: gpio@24 {
- compatible = "nxp,pca9673";
- reg = <0x24>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&mac {
- status = "okay";
- phy-mode = "mii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_mii_pins>;
-};
-
-&spifi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spifi_pins>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootloader";
- reg = <0x000000 0x040000>; /* 256 KiB */
- };
-
- partition@1 {
- label = "kernel";
- reg = <0x040000 0x2c0000>; /* 2.75 MiB */
- };
-
- partition@2 {
- label = "rootfs";
- reg = <0x300000 0x500000>; /* 5 MiB */
- };
- };
-};
-
-&uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
deleted file mode 100644
index 707d22a219d8..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * NXP LPC4350 and LPC4330 SoC
- *
- * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-
-/ {
- compatible = "nxp,lpc4350", "nxp,lpc4330";
-
- cpus {
- cpu@0 {
- compatible = "arm,cortex-m4";
- };
- };
-
- soc {
- sram0: sram@10000000 {
- compatible = "mmio-sram";
- reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram1: sram@10080000 {
- compatible = "mmio-sram";
- reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram2: sram@20000000 {
- compatible = "mmio-sram";
- reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
- };
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
deleted file mode 100644
index 7ccb4c2ca571..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
+++ /dev/null
@@ -1,624 +0,0 @@
-/*
- * Embedded Artist LPC4357 Developer's Kit
- *
- * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4357.dtsi"
-
-#include "dt-bindings/input/input.h"
-#include "dt-bindings/gpio/gpio.h"
-
-/ {
- model = "Embedded Artists' LPC4357 Developer's Kit";
- compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- };
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x2000000>; /* 32 MB */
- };
-
- vcc: vcc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "3v3-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- /* vmmc is controlled by sdmmc host internally */
- vmmc: vmmc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "vmmc-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- gpio_joystick {
- compatible = "gpio-keys-polled";
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_joystick_pins>;
- poll-interval = <100>;
- autorepeat;
-
- button-0 {
- label = "joy_enter";
- linux,code = <KEY_ENTER>;
- gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>;
- };
-
- button-1 {
- label = "joy_left";
- linux,code = <KEY_LEFT>;
- gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>;
- };
-
- button-2 {
- label = "joy_up";
- linux,code = <KEY_UP>;
- gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>;
- };
-
- button-3 {
- label = "joy_right";
- linux,code = <KEY_RIGHT>;
- gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>;
- };
-
- button-4 {
- label = "joy_down";
- linux,code = <KEY_DOWN>;
- gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>;
- };
- };
-
- leds_mmio {
- compatible = "gpio-leds";
-
- led1 {
- gpios = <&mmio_leds 15 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
- led2 {
- gpios = <&mmio_leds 14 GPIO_ACTIVE_HIGH>;
- };
-
- led3 {
- gpios = <&mmio_leds 13 GPIO_ACTIVE_HIGH>;
- };
-
- led4 {
- gpios = <&mmio_leds 12 GPIO_ACTIVE_HIGH>;
- };
-
- led5 {
- gpios = <&mmio_leds 11 GPIO_ACTIVE_HIGH>;
- };
-
- led6 {
- gpios = <&mmio_leds 10 GPIO_ACTIVE_HIGH>;
- };
-
- led7 {
- gpios = <&mmio_leds 9 GPIO_ACTIVE_HIGH>;
- };
-
- led8 {
- gpios = <&mmio_leds 8 GPIO_ACTIVE_HIGH>;
- };
-
- led9 {
- gpios = <&mmio_leds 7 GPIO_ACTIVE_HIGH>;
- };
-
- led10 {
- gpios = <&mmio_leds 6 GPIO_ACTIVE_HIGH>;
- };
-
- led11 {
- gpios = <&mmio_leds 5 GPIO_ACTIVE_HIGH>;
- };
-
- led12 {
- gpios = <&mmio_leds 4 GPIO_ACTIVE_HIGH>;
- };
-
- led13 {
- gpios = <&mmio_leds 3 GPIO_ACTIVE_HIGH>;
- };
-
- led14 {
- gpios = <&mmio_leds 2 GPIO_ACTIVE_HIGH>;
- };
-
- led15 {
- gpios = <&mmio_leds 1 GPIO_ACTIVE_HIGH>;
- };
-
- led16 {
- gpios = <&mmio_leds 0 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&pinctrl {
- emc_pins: emc-pins {
- emc_addr0_23_cfg {
- pins = "p2_9", "p2_10", "p2_11", "p2_12",
- "p2_13", "p1_0", "p1_1", "p1_2",
- "p2_8", "p2_7", "p2_6", "p2_2",
- "p2_1", "p2_0", "p6_8", "p6_7",
- "pd_16", "pd_15", "pe_0", "pe_1",
- "pe_2", "pe_3", "pe_4", "pa_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_data0_31_cfg {
- pins = "p1_7", "p1_8", "p1_9", "p1_10",
- "p1_11", "p1_12", "p1_13", "p1_14",
- "p5_4", "p5_5", "p5_6", "p5_7",
- "p5_0", "p5_1", "p5_2", "p5_3",
- "pd_2", "pd_3", "pd_4", "pd_5",
- "pd_6", "pd_7", "pd_8", "pd_9",
- "pe_5", "pe_6", "pe_7", "pe_8",
- "pe_9", "pe_10", "pe_11", "pe_12";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_we_oe_cfg {
- pins = "p1_6", "p1_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_bls0_3_cfg {
- pins = "p1_4", "p6_6", "pd_13", "pd_10";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_cs0_3_cfg {
- pins = "p1_5", "p6_3", "pd_12", "pd_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dqm0_3_cfg {
- pins = "p6_12", "p6_10", "pd_0", "pe_13";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_ras_cas_cfg {
- pins = "p6_5", "p6_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dycs0_cfg {
- pins = "p6_9";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_cke_cfg {
- pins = "p6_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_clock_cfg {
- pins = "clk0", "clk1", "clk2", "clk3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- enet_rmii_pins: enet-rmii-pins {
- enet_rmii_rxd_cfg {
- pins = "p1_15", "p0_0";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_txd_cfg {
- pins = "p1_18", "p1_20";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_rx_dv_cfg {
- pins = "p1_16";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_tx_en_cfg {
- pins = "p0_1";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_ref_clk_cfg {
- pins = "p1_19";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdc_cfg {
- pins = "pc_1";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- gpio_joystick_pins: gpio-joystick-pins {
- gpio_joystick_cfg {
- pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3";
- function = "gpio";
- input-enable;
- bias-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- sdmmc_pins: sdmmc-pins {
- sdmmc_clk_cfg {
- pins = "pc_0";
- function = "sdmmc";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- sdmmc_cmd_dat0_3_cfg {
- pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10";
- function = "sdmmc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- sdmmc_cd_cfg {
- pins = "pc_8";
- function = "sdmmc";
- bias-pull-down;
- input-enable;
- };
-
- sdmmc_pow_cfg {
- pins = "pc_9";
- function = "sdmmc";
- bias-pull-down;
- };
- };
-
- spifi_pins: spifi-pins {
- spifi_clk_cfg {
- pins = "p3_3";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_mosi_miso_sio2_3_cfg {
- pins = "p3_7", "p3_6", "p3_5", "p3_4";
- function = "spifi";
- slew-rate = <0>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_cs_cfg {
- pins = "p3_8";
- function = "spifi";
- bias-disable;
- };
- };
-
- ssp0_pins: ssp0-pins {
- ssp0_sck_miso_mosi_cfg {
- pins = "pf_0", "pf_2", "pf_3";
- function = "ssp0";
- slew-rate = <1>;
- bias-pull-down;
- input-enable;
- input-schmitt-disable;
- };
-
- ssp0_ssel_cfg {
- pins = "pf_1";
- function = "ssp0";
- bias-pull-up;
- };
- };
-
- uart0_pins: uart0-pins {
- uart0_rx_cfg {
- pins = "pf_11";
- function = "uart0";
- input-schmitt-disable;
- bias-disable;
- input-enable;
- };
-
- uart0_tx_cfg {
- pins = "pf_10";
- function = "uart0";
- bias-pull-down;
- };
- };
-
- uart3_pins: uart3-pins {
- uart3_rx_cfg {
- pins = "p2_4";
- function = "uart3";
- input-schmitt-disable;
- bias-disable;
- input-enable;
- };
-
- uart3_tx_cfg {
- pins = "p9_3";
- function = "uart3";
- bias-pull-down;
- };
- };
-
- usb0_pins: usb0-pins {
- usb0_pwr_enable_cfg {
- pins = "p2_3";
- function = "usb0";
- };
-
- usb0_pwr_fault_cfg {
- pins = "p8_0";
- function = "usb0";
- bias-disable;
- input-enable;
- };
- };
-};
-
-&adc0 {
- status = "okay";
- vref-supply = <&vcc>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-
- mma7455@1d {
- compatible = "fsl,mma7455";
- reg = <0x1d>;
- };
-
- temperature-sensor@48 {
- compatible = "national,lm75b";
- reg = <0x48>;
- };
-
- eeprom@57 {
- compatible = "microchip,24c64", "atmel,24c64";
- reg = <0x57>;
- };
-};
-
-&dac {
- status = "okay";
- vref-supply = <&vcc>;
-};
-
-&emc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&emc_pins>;
-
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <0>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <0>;
- mpmc,read-access-delay = <70>;
- mpmc,page-mode-read-delay = <70>;
-
- flash@0,0 {
- compatible = "sst,sst39vf320", "cfi-flash";
- reg = <0 0 0x400000>;
- bank-width = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootloader";
- reg = <0x000000 0x040000>; /* 256 KiB */
- };
-
- partition@1 {
- label = "kernel";
- reg = <0x040000 0x2c0000>; /* 2.75 MiB */
- };
-
- partition@2 {
- label = "rootfs";
- reg = <0x300000 0x100000>; /* 1 MiB */
- };
- };
- };
-
- cs2 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <2>;
- mpmc,memory-width = <16>;
-
- mmio_leds: gpio@2,0 {
- compatible = "ti,7416374";
- reg = <2 0 0x2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <50000000>;
-};
-
-&mac {
- status = "okay";
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_rmii_pins>;
-};
-
-&mmcsd {
- status = "okay";
- bus-width = <4>;
- vmmc-supply = <&vmmc>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pins>;
-};
-
-&spifi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spifi_pins>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-cpol;
- spi-cpha;
- spi-rx-bus-width = <4>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "data";
- reg = <0 0x200000>;
- };
- };
-};
-
-&ssp0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ssp0_pins>;
- num-cs = <1>;
-};
-
-&uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
-
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
-
-&usb0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
deleted file mode 100644
index d18f2b2caf68..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
+++ /dev/null
@@ -1,621 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
- *
- * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4357.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "MYIR Tech LPC4357 Development Board";
- compatible = "myir,myd-lpc4357", "nxp,lpc4357";
-
- chosen {
- stdout-path = "serial3:115200n8";
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x2000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins>;
-
- led1 {
- gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led2 {
- gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led3 {
- gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led4 {
- gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led5 {
- gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led6 {
- gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- panel: panel {
- compatible = "innolux,at070tn92";
- power-supply = <&vcc>;
-
- port {
- panel_input: endpoint {
- remote-endpoint = <&lcdc_output>;
- };
- };
- };
-
- vcc: vcc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "vcc-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vmmc: vmmc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "vmmc-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&pinctrl {
- can0_pins: can0-pins {
- can_rd_cfg {
- pins = "p3_1";
- function = "can0";
- input-enable;
- };
-
- can_td_cfg {
- pins = "p3_2";
- function = "can0";
- };
- };
-
- can1_pins: can1-pins {
- can_rd_cfg {
- pins = "pe_1";
- function = "can1";
- input-enable;
- };
-
- can_td_cfg {
- pins = "pe_0";
- function = "can1";
- };
- };
-
- emc_pins: emc-pins {
- emc_addr0_22_cfg {
- pins = "p2_9", "p2_10", "p2_11", "p2_12",
- "p2_13", "p1_0", "p1_1", "p1_2",
- "p2_8", "p2_7", "p2_6", "p2_2",
- "p2_1", "p2_0", "p6_8", "p6_7",
- "pd_16", "pd_15", "pe_0", "pe_1",
- "pe_2", "pe_3", "pe_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_data0_15_cfg {
- pins = "p1_7", "p1_8", "p1_9", "p1_10",
- "p1_11", "p1_12", "p1_13", "p1_14",
- "p5_4", "p5_5", "p5_6", "p5_7",
- "p5_0", "p5_1", "p5_2", "p5_3";
- function = "emc";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_we_oe_cfg {
- pins = "p1_6", "p1_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_cs0_cfg {
- pins = "p1_5";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_dqm0_1_cfg {
- pins = "p6_12", "p6_10";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_ras_cas_cfg {
- pins = "p6_5", "p6_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_dycs0_cfg {
- pins = "p6_9";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_cke_cfg {
- pins = "p6_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_clock_cfg {
- pins = "clk0";
- function = "emc";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
- };
-
- enet_rmii_pins: enet-rmii-pins {
- enet_rmii_rxd_cfg {
- pins = "p1_15", "p0_0";
- function = "enet";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- enet_rmii_txd_cfg {
- pins = "p1_18", "p1_20";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- };
-
- enet_rmii_rx_dv_cfg {
- pins = "p1_16";
- function = "enet";
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
-
- enet_mdc_cfg {
- pins = "pc_1";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- };
-
- enet_rmii_tx_en_cfg {
- pins = "p0_1";
- function = "enet";
- bias-disable;
- };
-
- enet_ref_clk_cfg {
- pins = "p1_19";
- function = "enet";
- slew-rate = <1>;
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- i2c1_pins: i2c1-pins {
- i2c1_pins_cfg {
- pins = "pe_15", "pe_13";
- function = "i2c1";
- input-enable;
- };
- };
-
- lcd_pins: lcd-pins {
- lcd_vd0_23_cfg {
- pins = "p4_1", "p4_4", "p4_3", "p4_2",
- "p8_7", "p8_6", "p8_5", "p8_4",
- "p7_5", "p4_8", "p4_10", "p4_9",
- "p8_3", "pb_6", "pb_5", "pb_4",
- "p7_4", "p7_3", "p7_2", "p7_1",
- "pb_3", "pb_2", "pb_1", "pb_0";
- function = "lcd";
- };
-
- lcd_vsync_en_dclk_lp_pwr_cfg {
- pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7";
- function = "lcd";
- };
- };
-
- led_pins: led-pins {
- led_1_6_cfg {
- pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0";
- function = "gpio";
- bias-pull-down;
- };
- };
-
- sdmmc_pins: sdmmc-pins {
- sdmmc_clk_cfg {
- pins = "pc_0";
- function = "sdmmc";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- sdmmc_cmd_dat0_3_cfg {
- pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10";
- function = "sdmmc";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- sdmmc_cd_cfg {
- pins = "pc_8";
- function = "sdmmc";
- input-enable;
- bias-pull-down;
- };
- };
-
- spifi_pins: spifi-pins {
- spifi_sck_cfg {
- pins = "p3_3";
- function = "spifi";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- spifi_mosi_miso_sio2_sio3_cfg {
- pins = "p3_7", "p3_6", "p3_5", "p3_4";
- function = "spifi";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- spifi_cs_cfg {
- pins = "p3_8";
- function = "spifi";
- bias-disable;
- };
- };
-
- ssp1_pins: ssp1-pins {
- ssp1_sck_cfg {
- pins = "pf_4";
- function = "ssp1";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- ssp1_miso_cfg {
- pins = "pf_6";
- function = "ssp1";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-pull-down;
- };
-
- ssp1_mosi_cfg {
- pins = "pf_7";
- function = "ssp1";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- ssp1_ssel_cfg {
- pins = "pf_5";
- function = "gpio";
- bias-disable;
- };
- };
-
- uart0_pins: uart0-pins {
- uart0_rxd_cfg {
- pins = "pf_11";
- function = "uart0";
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
-
- uart0_clk_dir_txd_cfg {
- pins = "pf_8", "pf_9", "pf_10";
- function = "uart0";
- bias-pull-down;
- };
- };
-
- uart1_pins: uart1-pins {
- uart1_rxd_cfg {
- pins = "pc_14";
- function = "uart1";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- uart1_dtr_txd_cfg {
- pins = "pc_12", "pc_13";
- function = "uart1";
- bias-pull-down;
- };
- };
-
- uart2_pins: uart2-pins {
- uart2_rxd_cfg {
- pins = "pa_2";
- function = "uart2";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- uart2_txd_cfg {
- pins = "pa_1";
- function = "uart2";
- bias-pull-down;
- };
- };
-
- uart3_pins: uart3-pins {
- uart3_rx_cfg {
- pins = "p2_4";
- function = "uart3";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- uart3_tx_cfg {
- pins = "p2_3";
- function = "uart3";
- bias-pull-down;
- };
- };
-
- usb0_pins: usb0-pins {
- usb0_pwr_enable_cfg {
- pins = "p6_3";
- function = "usb0";
- };
-
- usb0_pwr_fault_cfg {
- pins = "p8_0";
- function = "usb0";
- bias-disable;
- input-enable;
- };
- };
-};
-
-&adc1 {
- status = "okay";
- vref-supply = <&vcc>;
-};
-
-&can0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&can0_pins>;
-};
-
-/* Pin conflict with EMC, muxed by JP5 and JP6 */
-&can1 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&can1_pins>;
-};
-
-&emc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&emc_pins>;
-
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <0>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <0>;
- mpmc,read-access-delay = <70>;
- mpmc,page-mode-read-delay = <70>;
-
- /* SST/Microchip SST39VF1601 */
- flash@0,0 {
- compatible = "cfi-flash";
- reg = <0 0 0x400000>;
- bank-width = <2>;
- };
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <50000000>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clock-frequency = <400000>;
-
- sensor@49 {
- compatible = "national,lm75";
- reg = <0x49>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c512";
- reg = <0x50>;
- };
-};
-
-&lcdc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_pins>;
-
- max-memory-bandwidth = <92240000>;
-
- port {
- lcdc_output: endpoint {
- remote-endpoint = <&panel_input>;
- arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- };
- };
-};
-
-&mac {
- status = "okay";
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_rmii_pins>;
- phy-handle = <&phy1>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-};
-
-&mmcsd {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pins>;
- bus-width = <4>;
- vmmc-supply = <&vmmc>;
-};
-
-/* Pin conflict with SSP0, the latter is routed to J17 pin header */
-&spifi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spifi_pins>;
-
- /* Atmel AT25DF321A */
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <51000000>;
- spi-cpol;
- spi-cpha;
- };
-};
-
-&ssp1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ssp1_pins>;
- num-cs = <1>;
- cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>;
-};
-
-/* Routed to J17 pin header */
-&uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
-
-/* RS485 */
-&uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-/* Routed to J17 pin header */
-&uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
-
-&usb0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
deleted file mode 100644
index d138ee7869ff..000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC
- *
- * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-
-/ {
- compatible = "nxp,lpc4357";
-
- cpus {
- cpu@0 {
- compatible = "arm,cortex-m4";
- };
- };
-
- soc {
- sram0: sram@10000000 {
- compatible = "mmio-sram";
- reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram1: sram@10080000 {
- compatible = "mmio-sram";
- reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram2: sram@20000000 {
- compatible = "mmio-sram";
- reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
- };
-};
-
-&eeprom {
- status = "okay";
-};
diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig
deleted file mode 100644
index f142a6637ede..000000000000
--- a/arch/arm/configs/lpc18xx_defconfig
+++ /dev/null
@@ -1,158 +0,0 @@
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZO is not set
-# CONFIG_RD_LZ4 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_UID16 is not set
-CONFIG_BASE_SMALL=y
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_EXPERT=y
-# CONFIG_MMU is not set
-CONFIG_ARCH_LPC18XX=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x28000000
-CONFIG_DRAM_SIZE=0x02000000
-CONFIG_FLASH_MEM_BASE=0x1b000000
-CONFIG_FLASH_SIZE=0x00080000
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-# CONFIG_COREDUMP is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_SPI_NOR=y
-# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
-CONFIG_SPI_NXP_SPIFI=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SRAM=y
-CONFIG_EEPROM_AT24=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_HISILICON is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_QUALCOMM is not set
-# CONFIG_NET_VENDOR_ROCKER is not set
-# CONFIG_NET_VENDOR_SAMSUNG is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-CONFIG_STMMAC_ETH=y
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_SMSC_PHY=y
-# CONFIG_USB_NET_DRIVERS is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_LPC2K=y
-CONFIG_SPI=y
-CONFIG_SPI_PL022=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_74XX_MMIO=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_SENSORS_JC42=y
-CONFIG_SENSORS_LM75=y
-CONFIG_WATCHDOG=y
-CONFIG_LPC18XX_WATCHDOG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_DRM=y
-CONFIG_DRM_PL111=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_PCA9532=y
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_LPC24XX=y
-CONFIG_DMADEVICES=y
-CONFIG_AMBA_PL08X=y
-CONFIG_LPC18XX_DMAMUX=y
-CONFIG_MEMORY=y
-CONFIG_ARM_PL172_MPMC=y
-CONFIG_IIO=y
-CONFIG_MMA7455_I2C=y
-CONFIG_LPC18XX_ADC=y
-CONFIG_LPC18XX_DAC=y
-CONFIG_IIO_SYSFS_TRIGGER=y
-CONFIG_PWM=y
-CONFIG_PWM_LPC18XX_SCT=y
-CONFIG_PHY_LPC18XX_USB_OTG=y
-CONFIG_NVMEM_LPC18XX_EEPROM=y
-CONFIG_EXT2_FS=y
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_JFFS2_FS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PRINTK_TIME=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/mach-lpc18xx/Makefile b/arch/arm/mach-lpc18xx/Makefile
deleted file mode 100644
index c80d80c199d3..000000000000
--- a/arch/arm/mach-lpc18xx/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-y += board-dt.o
diff --git a/arch/arm/mach-lpc18xx/board-dt.c b/arch/arm/mach-lpc18xx/board-dt.c
deleted file mode 100644
index 4729eb83401a..000000000000
--- a/arch/arm/mach-lpc18xx/board-dt.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree board file for NXP LPC18xx/43xx
- *
- * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- */
-
-#include <asm/mach/arch.h>
-
-static const char *const lpc18xx_43xx_compat[] __initconst = {
- "nxp,lpc1850",
- "nxp,lpc4350",
- "nxp,lpc4370",
- NULL
-};
-
-DT_MACHINE_START(LPC18XXDT, "NXP LPC18xx/43xx (Device Tree)")
- .dt_compat = lpc18xx_43xx_compat,
-MACHINE_END
--
2.53.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 11/14] ARM: stm32: remove stm32f4/f7/h7 MCU support
2026-09-14 14:08 [PATCH v2 00/14] ARM: deprecated platform removal Arnd Bergmann
` (3 preceding siblings ...)
2026-09-14 14:08 ` [PATCH v2 10/14] ARM: lpc18xx: remove entire platform Arnd Bergmann
@ 2026-09-14 14:08 ` Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 12/14] ARM: versatile: remove mps2 support Arnd Bergmann
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Arnd Bergmann @ 2026-09-14 14:08 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christophe Parant,
Benjamin Gaignard, Dario Binacchi, devicetree, linux-stm32,
Linus Walleij
From: Arnd Bergmann <arnd@arndb.de>
The stm32 platform started out as a Cortex-M based microcontoller
platform in 2007, with a few of the older products gaining Linux kernel
support in 2016. These days, the only relevant chips for Linux are the
stm32mp1 (Cortex-A7) and stm32mp2 (Cortex-A35) product lines, with the
microcontrollers running smaller RTOSs on new products.
The microcontrollers were marked as deprecated in the linux-7.3LTS
release, which will remain supported for a few more years and
is expected to be sufficient for any of the remaining original users.
Remove the MCU support now, leaving only the stm32mp SoCs in the platform.
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Christophe Parant <c.parant@phytec.fr>
Cc: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Cc: devicetree@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
Acked-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
I have separate patches to remove the MCU support from the
shared stm32 drivers and DT bindings, as well as the MCU
specific drivers for pinctrl, clk, i2c, can, media) and will
post these separately.
---
Documentation/arch/arm/index.rst | 5 -
Documentation/arch/arm/stm32/overview.rst | 8 +-
.../arch/arm/stm32/stm32f429-overview.rst | 25 -
.../arch/arm/stm32/stm32f746-overview.rst | 32 -
.../arch/arm/stm32/stm32f769-overview.rst | 34 -
.../arch/arm/stm32/stm32h743-overview.rst | 33 -
.../arch/arm/stm32/stm32h750-overview.rst | 34 -
arch/arm/Kconfig.debug | 38 -
arch/arm/boot/dts/st/Makefile | 11 -
arch/arm/boot/dts/st/stm32429i-eval.dts | 349 --------
arch/arm/boot/dts/st/stm32746g-eval.dts | 236 ------
arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi | 482 -----------
arch/arm/boot/dts/st/stm32f429-disco.dts | 243 ------
arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi | 91 --
arch/arm/boot/dts/st/stm32f429.dtsi | 800 ------------------
arch/arm/boot/dts/st/stm32f469-disco.dts | 260 ------
arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi | 92 --
arch/arm/boot/dts/st/stm32f469.dtsi | 18 -
arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi | 436 ----------
arch/arm/boot/dts/st/stm32f746-disco.dts | 234 -----
arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi | 55 --
arch/arm/boot/dts/st/stm32f746.dtsi | 727 ----------------
.../dts/st/stm32f769-disco-mb1166-reva09.dts | 13 -
arch/arm/boot/dts/st/stm32f769-disco.dts | 243 ------
arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi | 55 --
arch/arm/boot/dts/st/stm32f769.dtsi | 37 -
arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi | 301 -------
arch/arm/boot/dts/st/stm32h743.dtsi | 738 ----------------
arch/arm/boot/dts/st/stm32h743i-disco.dts | 145 ----
arch/arm/boot/dts/st/stm32h743i-eval.dts | 185 ----
arch/arm/boot/dts/st/stm32h747i-disco.dts | 149 ----
arch/arm/boot/dts/st/stm32h750.dtsi | 6 -
arch/arm/boot/dts/st/stm32h750i-art-pi.dts | 229 -----
arch/arm/configs/stm32_defconfig | 80 --
arch/arm/mach-stm32/Kconfig | 38 +-
arch/arm/mach-stm32/board-dt.c | 7 -
36 files changed, 7 insertions(+), 6462 deletions(-)
delete mode 100644 Documentation/arch/arm/stm32/stm32f429-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32f746-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32f769-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32h743-overview.rst
delete mode 100644 Documentation/arch/arm/stm32/stm32h750-overview.rst
delete mode 100644 arch/arm/boot/dts/st/stm32429i-eval.dts
delete mode 100644 arch/arm/boot/dts/st/stm32746g-eval.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f429-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f429.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f469-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f469.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f746-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f746.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f769-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32f769.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h743.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h743i-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32h743i-eval.dts
delete mode 100644 arch/arm/boot/dts/st/stm32h747i-disco.dts
delete mode 100644 arch/arm/boot/dts/st/stm32h750.dtsi
delete mode 100644 arch/arm/boot/dts/st/stm32h750i-art-pi.dts
delete mode 100644 arch/arm/configs/stm32_defconfig
diff --git a/Documentation/arch/arm/index.rst b/Documentation/arch/arm/index.rst
index 17d6a5bbfc26..70bc418fdb38 100644
--- a/Documentation/arch/arm/index.rst
+++ b/Documentation/arch/arm/index.rst
@@ -47,12 +47,7 @@ SoC-specific documents
pxa/mfp
- stm32/stm32f746-overview
stm32/overview
- stm32/stm32h743-overview
- stm32/stm32h750-overview
- stm32/stm32f769-overview
- stm32/stm32f429-overview
stm32/stm32mp13-overview
stm32/stm32mp151-overview
stm32/stm32mp157-overview
diff --git a/Documentation/arch/arm/stm32/overview.rst b/Documentation/arch/arm/stm32/overview.rst
index 85cfc8410798..43dc7c990f71 100644
--- a/Documentation/arch/arm/stm32/overview.rst
+++ b/Documentation/arch/arm/stm32/overview.rst
@@ -5,15 +5,13 @@ STM32 ARM Linux Overview
Introduction
------------
-The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) and
-Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of
-ARM Linux.
+The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) is
+supported by the 'STM32' platform of ARM Linux, support for the Cortex-M
+based MCUs has been removed.
Configuration
-------------
-For MCUs, use the provided default configuration:
- make stm32_defconfig
For MPUs, use multi_v7 configuration:
make multi_v7_defconfig
diff --git a/Documentation/arch/arm/stm32/stm32f429-overview.rst b/Documentation/arch/arm/stm32/stm32f429-overview.rst
deleted file mode 100644
index a7ebe8ea6697..000000000000
--- a/Documentation/arch/arm/stm32/stm32f429-overview.rst
+++ /dev/null
@@ -1,25 +0,0 @@
-==================
-STM32F429 Overview
-==================
-
-Introduction
-------------
-
-The STM32F429 is a Cortex-M4 MCU aimed at various applications.
-It features:
-
-- ARM Cortex-M4 up to 180MHz with FPU
-- 2MB internal Flash Memory
-- External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
-- I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
-- LCD controller & Camera interface
-- Cryptographic processor
-
-Resources
----------
-
-Datasheet and reference manual are publicly available on ST website (STM32F429_).
-
-.. _STM32F429: http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
-
-:Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
diff --git a/Documentation/arch/arm/stm32/stm32f746-overview.rst b/Documentation/arch/arm/stm32/stm32f746-overview.rst
deleted file mode 100644
index 335f0855a858..000000000000
--- a/Documentation/arch/arm/stm32/stm32f746-overview.rst
+++ /dev/null
@@ -1,32 +0,0 @@
-==================
-STM32F746 Overview
-==================
-
-Introduction
-------------
-
-The STM32F746 is a Cortex-M7 MCU aimed at various applications.
-It features:
-
-- Cortex-M7 core running up to @216MHz
-- 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
-- FMC controller to connect SDRAM, NOR and NAND memories
-- Dual mode QSPI
-- SD/MMC/SDIO support
-- Ethernet controller
-- USB OTFG FS & HS controllers
-- I2C, SPI, CAN buses support
-- Several 16 & 32 bits general purpose timers
-- Serial Audio interface
-- LCD controller
-- HDMI-CEC
-- SPDIFRX
-
-Resources
----------
-
-Datasheet and reference manual are publicly available on ST website (STM32F746_).
-
-.. _STM32F746: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
-
-:Authors: Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arch/arm/stm32/stm32f769-overview.rst b/Documentation/arch/arm/stm32/stm32f769-overview.rst
deleted file mode 100644
index ef31aadee68f..000000000000
--- a/Documentation/arch/arm/stm32/stm32f769-overview.rst
+++ /dev/null
@@ -1,34 +0,0 @@
-==================
-STM32F769 Overview
-==================
-
-Introduction
-------------
-
-The STM32F769 is a Cortex-M7 MCU aimed at various applications.
-It features:
-
-- Cortex-M7 core running up to @216MHz
-- 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM)
-- FMC controller to connect SDRAM, NOR and NAND memories
-- Dual mode QSPI
-- SD/MMC/SDIO support*2
-- Ethernet controller
-- USB OTFG FS & HS controllers
-- I2C*4, SPI*6, CAN*3 buses support
-- Several 16 & 32 bits general purpose timers
-- Serial Audio interface*2
-- LCD controller
-- HDMI-CEC
-- DSI
-- SPDIFRX
-- MDIO salave interface
-
-Resources
----------
-
-Datasheet and reference manual are publicly available on ST website (STM32F769_).
-
-.. _STM32F769: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x9/stm32f769ni.html
-
-:Authors: Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arch/arm/stm32/stm32h743-overview.rst b/Documentation/arch/arm/stm32/stm32h743-overview.rst
deleted file mode 100644
index 7659df24d362..000000000000
--- a/Documentation/arch/arm/stm32/stm32h743-overview.rst
+++ /dev/null
@@ -1,33 +0,0 @@
-==================
-STM32H743 Overview
-==================
-
-Introduction
-------------
-
-The STM32H743 is a Cortex-M7 MCU aimed at various applications.
-It features:
-
-- Cortex-M7 core running up to @400MHz
-- 2MB internal flash, 1MBytes internal RAM
-- FMC controller to connect SDRAM, NOR and NAND memories
-- Dual mode QSPI
-- SD/MMC/SDIO support
-- Ethernet controller
-- USB OTFG FS & HS controllers
-- I2C, SPI, CAN buses support
-- Several 16 & 32 bits general purpose timers
-- Serial Audio interface
-- LCD controller
-- HDMI-CEC
-- SPDIFRX
-- DFSDM
-
-Resources
----------
-
-Datasheet and reference manual are publicly available on ST website (STM32H743_).
-
-.. _STM32H743: http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
-
-:Authors: Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arch/arm/stm32/stm32h750-overview.rst b/Documentation/arch/arm/stm32/stm32h750-overview.rst
deleted file mode 100644
index be032b77d1f1..000000000000
--- a/Documentation/arch/arm/stm32/stm32h750-overview.rst
+++ /dev/null
@@ -1,34 +0,0 @@
-==================
-STM32H750 Overview
-==================
-
-Introduction
-------------
-
-The STM32H750 is a Cortex-M7 MCU aimed at various applications.
-It features:
-
-- Cortex-M7 core running up to @480MHz
-- 128K internal flash, 1MBytes internal RAM
-- FMC controller to connect SDRAM, NOR and NAND memories
-- Dual mode QSPI
-- SD/MMC/SDIO support
-- Ethernet controller
-- USB OTFG FS & HS controllers
-- I2C, SPI, CAN buses support
-- Several 16 & 32 bits general purpose timers
-- Serial Audio interface
-- LCD controller
-- HDMI-CEC
-- SPDIFRX
-- DFSDM
-
-Resources
----------
-
-Datasheet and reference manual are publicly available on ST website (STM32H750_).
-
-.. _STM32H750: https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html
-
-:Authors: Dillon Min <dillon.minfei@gmail.com>
-
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 4e34ff43ef75..dac701197182 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1128,42 +1128,6 @@ choice
If unsure, say N.
- config STM32F4_DEBUG_UART
- bool "Use STM32F4 UART for low-level debug"
- depends on MACH_STM32F429 || MACH_STM32F469
- select DEBUG_STM32_UART
- help
- Say Y here if you want kernel low-level debugging support
- on STM32F4 based platforms, which default UART is wired on
- USART1, but another UART instance can be selected by modifying
- CONFIG_DEBUG_UART_PHYS.
-
- If unsure, say N.
-
- config STM32F7_DEBUG_UART
- bool "Use STM32F7 UART for low-level debug"
- depends on MACH_STM32F746 || MACH_STM32F769
- select DEBUG_STM32_UART
- help
- Say Y here if you want kernel low-level debugging support
- on STM32F7 based platforms, which default UART is wired on
- USART1, but another UART instance can be selected by modifying
- CONFIG_DEBUG_UART_PHYS.
-
- If unsure, say N.
-
- config STM32H7_DEBUG_UART
- bool "Use STM32H7 UART for low-level debug"
- depends on MACH_STM32H743
- select DEBUG_STM32_UART
- help
- Say Y here if you want kernel low-level debugging support
- on STM32H7 based platforms, which default UART is wired on
- USART1, but another UART instance can be selected by modifying
- CONFIG_DEBUG_UART_PHYS.
-
- If unsure, say N.
-
config STM32MP1_DEBUG_UART
bool "Use STM32MP1 UART for low-level debug"
depends on MACH_STM32MP157
@@ -1541,8 +1505,6 @@ config DEBUG_UART_PHYS
default 0x3e000000 if DEBUG_BCM_KONA_UART
default 0x3f201000 if DEBUG_BCM2836
default 0x40010000 if STM32MP1_DEBUG_UART
- default 0x40011000 if STM32F4_DEBUG_UART || STM32F7_DEBUG_UART || \
- STM32H7_DEBUG_UART
default 0x40028000 if DEBUG_AT91_SAMV7_USART1
default 0x40090000 if DEBUG_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile
index 10c5d75f6169..733ae4cc418b 100644
--- a/arch/arm/boot/dts/st/Makefile
+++ b/arch/arm/boot/dts/st/Makefile
@@ -102,17 +102,6 @@ stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \
stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \
dtb-$(CONFIG_ARCH_STM32) += \
- stm32f429-disco.dtb \
- stm32f469-disco.dtb \
- stm32f746-disco.dtb \
- stm32f769-disco.dtb \
- stm32f769-disco-mb1166-reva09.dtb \
- stm32429i-eval.dtb \
- stm32746g-eval.dtb \
- stm32h743i-eval.dtb \
- stm32h743i-disco.dtb \
- stm32h747i-disco.dtb \
- stm32h750i-art-pi.dtb \
stm32mp133c-prihmb.dtb \
stm32mp135f-dhcor-dhsbc.dtb \
stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtb \
diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts
deleted file mode 100644
index f4b1c4eb64f2..000000000000
--- a/arch/arm/boot/dts/st/stm32429i-eval.dts
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f429.dtsi"
-#include "stm32f429-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/media/video-interfaces.h>
-
-/ {
- model = "STMicroelectronics STM32429i-EVAL board";
- compatible = "st,stm32429i-eval", "st,stm32f429";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- clocks {
- clk_ext_camera: clk-ext-camera {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
-
- soc {
- dma-ranges = <0xc0000000 0x0 0x10000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpiog 6 1>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&gpiog 7 1>;
- };
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpiog 10 1>;
- };
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpiog 12 1>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "Wake up";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioa 0 0>;
- };
- button-1 {
- label = "Tamper";
- linux,code = <KEY_RESTART>;
- gpios = <&gpioc 13 0>;
- };
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-
- panel_rgb: panel-rgb {
- compatible = "ampire,am-480272h3tmqw-t01h";
- power-supply = <&vdd_panel>;
- status = "okay";
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-
- vdda: regulator-vdda {
- compatible = "regulator-fixed";
- regulator-name = "vdda";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vref: regulator-vref {
- compatible = "regulator-fixed";
- regulator-name = "vref";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- usbotg_hs_phy: usbphy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- vdd_panel: vdd-panel {
- compatible = "regulator-fixed";
- regulator-name = "vdd_panel";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&adc {
- pinctrl-names = "default";
- pinctrl-0 = <&adc3_in8_pin>;
- vdda-supply = <&vdda>;
- vref-supply = <&vref>;
- status = "okay";
- adc3: adc@200 {
- st,adc-channels = <8>;
- status = "okay";
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&dcmi {
- status = "okay";
-
- port {
- dcmi_0: endpoint {
- remote-endpoint = <&ov2640_0>;
- bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
- bus-width = <8>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- ov2640: camera@30 {
- compatible = "ovti,ov2640";
- reg = <0x30>;
- resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>;
- clocks = <&clk_ext_camera>;
- clock-names = "xvclk";
- status = "okay";
-
- port {
- ov2640_0: endpoint {
- remote-endpoint = <&dcmi_0>;
- };
- };
- };
-
- stmpe1600: stmpe1600@42 {
- compatible = "st,stmpe1600";
- reg = <0x42>;
- interrupts = <8 3>;
- interrupt-parent = <&gpioi>;
- wakeup-source;
-
- stmpegpio: stmpe_gpio {
- compatible = "st,stmpe-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-};
-
-&iwdg {
- status = "okay";
- timeout-sec = <32>;
-};
-
-<dc {
- status = "okay";
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-names = "default";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&mac {
- status = "okay";
- pinctrl-0 = <ðernet_mii>;
- pinctrl-names = "default";
- phy-mode = "mii";
- phy-handle = <&phy1>;
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_pins_od>;
- bus-width = <4>;
- max-frequency = <12500000>;
-};
-
-&timers1 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@0 {
- status = "okay";
- };
-};
-
-&timers3 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm3_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@2 {
- status = "okay";
- };
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "host";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts
deleted file mode 100644
index 6772c1f9d03e..000000000000
--- a/arch/arm/boot/dts/st/stm32746g-eval.dts
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f746.dtsi"
-#include "stm32f746-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32746g-EVAL board";
- compatible = "st,stm32746g-eval", "st,stm32f746";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpiof 10 1>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&stmfx_pinctrl 17 1>;
- };
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpiob 7 1>;
- };
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&stmfx_pinctrl 19 1>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "Wake up";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioc 13 0>;
- };
- };
-
- joystick {
- compatible = "gpio-keys";
- pinctrl-0 = <&joystick_pins>;
- pinctrl-names = "default";
- button-0 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
- };
- button-1 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- };
- button-2 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- };
- button-3 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- };
- button-4 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- stmfx: stmfx@42 {
- compatible = "st,stmfx-0300";
- reg = <0x42>;
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpioi>;
-
- stmfx_pinctrl: pinctrl {
- compatible = "st,stmfx-0300-pinctrl";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-
- joystick_pins: joystick {
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- drive-push-pull;
- bias-pull-up;
- };
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio1 {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- broken-cd;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdio_pins_a>;
- pinctrl-1 = <&sdio_pins_od_a>;
- pinctrl-2 = <&sdio_pins_sleep_a>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
deleted file mode 100644
index 3bb812d6399e..000000000000
--- a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-#include <dt-bindings/mfd/stm32f4-rcc.h>
-
-/ {
- soc {
- pinctrl: pinctrl@40020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
-
- gpioa: gpio@40020000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
- st,bank-name = "GPIOA";
- };
-
- gpiob: gpio@40020400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
- st,bank-name = "GPIOB";
- };
-
- gpioc: gpio@40020800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
- st,bank-name = "GPIOC";
- };
-
- gpiod: gpio@40020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
- st,bank-name = "GPIOD";
- };
-
- gpioe: gpio@40021000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
- st,bank-name = "GPIOE";
- };
-
- gpiof: gpio@40021400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
- st,bank-name = "GPIOF";
- };
-
- gpiog: gpio@40021800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
- st,bank-name = "GPIOG";
- };
-
- gpioh: gpio@40021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
- st,bank-name = "GPIOH";
- };
-
- gpioi: gpio@40022000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
- st,bank-name = "GPIOI";
- };
-
- gpioj: gpio@40022400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
- st,bank-name = "GPIOJ";
- };
-
- gpiok: gpio@40022800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
- st,bank-name = "GPIOK";
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart3_pins_a: usart3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
- bias-disable;
- };
- };
-
- usbotg_fs_pins_a: usbotg-fs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
- <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_fs_pins_b: usbotg-fs-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
- <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
- <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
- <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- ethernet_mii: mii-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
- <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
- <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
- <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
- <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
- <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
- <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
- slew-rate = <2>;
- };
- };
-
- adc3_in8_pin: adc-200 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
- };
- };
-
- pwm1_pins: pwm1-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
- <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
- <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
- };
- };
-
- pwm3_pins: pwm3-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
- <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
- };
- };
-
- i2c1_pins: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
- <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <3>;
- };
- };
-
- ltdc_pins_a: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
- <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
- slew-rate = <2>;
- };
- };
-
- ltdc_pins_b: ltdc-1 {
- pins {
- pinmux = <STM32_PINMUX('C', 6, AF14)>,
- /* LCD_HSYNC */
- <STM32_PINMUX('A', 4, AF14)>,
- /* LCD_VSYNC */
- <STM32_PINMUX('G', 7, AF14)>,
- /* LCD_CLK */
- <STM32_PINMUX('C', 10, AF14)>,
- /* LCD_R2 */
- <STM32_PINMUX('B', 0, AF9)>,
- /* LCD_R3 */
- <STM32_PINMUX('A', 11, AF14)>,
- /* LCD_R4 */
- <STM32_PINMUX('A', 12, AF14)>,
- /* LCD_R5 */
- <STM32_PINMUX('B', 1, AF9)>,
- /* LCD_R6*/
- <STM32_PINMUX('G', 6, AF14)>,
- /* LCD_R7 */
- <STM32_PINMUX('A', 6, AF14)>,
- /* LCD_G2 */
- <STM32_PINMUX('G', 10, AF9)>,
- /* LCD_G3 */
- <STM32_PINMUX('B', 10, AF14)>,
- /* LCD_G4 */
- <STM32_PINMUX('D', 6, AF14)>,
- /* LCD_B2 */
- <STM32_PINMUX('G', 11, AF14)>,
- /* LCD_B3*/
- <STM32_PINMUX('B', 11, AF14)>,
- /* LCD_G5 */
- <STM32_PINMUX('C', 7, AF14)>,
- /* LCD_G6 */
- <STM32_PINMUX('D', 3, AF14)>,
- /* LCD_G7 */
- <STM32_PINMUX('G', 12, AF9)>,
- /* LCD_B4 */
- <STM32_PINMUX('A', 3, AF14)>,
- /* LCD_B5 */
- <STM32_PINMUX('B', 8, AF14)>,
- /* LCD_B6 */
- <STM32_PINMUX('B', 9, AF14)>,
- /* LCD_B7 */
- <STM32_PINMUX('F', 10, AF14)>;
- /* LCD_DE */
- slew-rate = <2>;
- };
- };
-
- spi5_pins: spi5-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF5)>,
- /* SPI5_CLK */
- <STM32_PINMUX('F', 9, AF5)>;
- /* SPI5_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 8, AF5)>;
- /* SPI5_MISO */
- bias-disable;
- };
- };
-
- i2c3_pins: i2c3-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 9, AF4)>,
- /* I2C3_SDA */
- <STM32_PINMUX('A', 8, AF4)>;
- /* I2C3_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <3>;
- };
- };
-
- dcmi_pins: dcmi-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
- <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
- <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
- <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
- <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
- <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
- <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
- <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
- <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
- <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
- <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
- <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
- <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- sdio_pins: sdio-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od: sdio-pins-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- can1_pins_a: can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_a: can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_b: can2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts
deleted file mode 100644
index ded369abee4f..000000000000
--- a/arch/arm/boot/dts/st/stm32f429-disco.dts
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f429.dtsi"
-#include "stm32f429-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32F429i-DISCO board";
- compatible = "st,stm32f429i-disco", "st,stm32f429";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@90000000 {
- device_type = "memory";
- reg = <0x90000000 0x800000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpiog 14 0>;
- };
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpiog 13 0>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_HOME>;
- gpios = <&gpioa 0 0>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-
- /* This turns on vbus for otg for host mode (dwc2) */
- vcc5v_otg: vcc5v-otg-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpioc 4 0>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-};
-
-&clk_hse {
- clock-frequency = <8000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
- clock-frequency = <100000>;
- status = "okay";
-
- stmpe811@41 {
- compatible = "st,stmpe811";
- reg = <0x41>;
- interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpioa>;
- /* 3.25 MHz ADC clock speed */
- st,adc-freq = <1>;
- /* 12-bit ADC */
- st,mod-12b = <1>;
- /* internal ADC reference */
- st,ref-sel = <0>;
- /* ADC converstion time: 80 clocks */
- st,sample-time = <4>;
-
- stmpe_touchscreen {
- compatible = "st,stmpe-ts";
- /* 8 sample average control */
- st,ave-ctrl = <3>;
- /* 7 length fractional part in z */
- st,fraction-z = <7>;
- /*
- * 50 mA typical 80 mA max touchscreen drivers
- * current limit value
- */
- st,i-drive = <1>;
- /* 1 ms panel driver settling time */
- st,settling = <3>;
- /* 5 ms touch detect interrupt delay */
- st,touch-det-delay = <5>;
- };
-
- stmpe_adc {
- compatible = "st,stmpe-adc";
- /* forbid to use ADC channels 3-0 (touch) */
- st,norequest-mask = <0x0F>;
- };
- };
-};
-
-<dc {
- status = "okay";
- pinctrl-0 = <<dc_pins_b>;
- pinctrl-names = "default";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&rtc {
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSI>;
- status = "okay";
-};
-
-&spi5 {
- status = "okay";
- pinctrl-0 = <&spi5_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>;
-
- l3gd20: l3gd20@0 {
- compatible = "st,l3gd20-gyro";
- spi-max-frequency = <10000000>;
- st,drdy-int-pin = <2>;
- interrupt-parent = <&gpioa>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>,
- <2 IRQ_TYPE_EDGE_RISING>;
- reg = <0>;
- status = "okay";
- };
-
- display: display@1 {
- /* Connect panel-ilitek-9341 to ltdc */
- compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341";
- reg = <1>;
- spi-3wire;
- spi-max-frequency = <10000000>;
- dc-gpios = <&gpiod 13 0>;
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- compatible = "st,stm32f4x9-fsotg";
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi
deleted file mode 100644
index e10d7a1f3207..000000000000
--- a/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "stm32f4-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f429-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi
deleted file mode 100644
index ad91b74ddd0d..000000000000
--- a/arch/arm/boot/dts/st/stm32f429.dtsi
+++ /dev/null
@@ -1,800 +0,0 @@
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../armv7-m.dtsi"
-#include <dt-bindings/clock/stm32fx-clock.h>
-#include <dt-bindings/mfd/stm32f4-rcc.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_lsi: clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_i2s_ckin: i2s-ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
- };
-
- soc {
- romem: efuse@1fff7800 {
- compatible = "st,stm32f4-otp";
- reg = <0x1fff7800 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- ts_cal1: calib@22c {
- reg = <0x22c 0x2>;
- };
- ts_cal2: calib@22e {
- reg = <0x22e 0x2>;
- };
- };
-
- timers2: timers@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
- };
-
- timers3: timers@40000400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000400 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- timers4: timers@40000800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000800 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
- };
-
- timers5: timers@40000c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000C00 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
- };
-
- timers6: timers@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
- clock-names = "int";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timers@40001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001400 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
- clock-names = "int";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- timers12: timers@40001800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001800 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timers@40001c00 {
- compatible = "st,stm32-timers";
- reg = <0x40001C00 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers14: timers@40002000 {
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- rtc: rtc@40002800 {
- compatible = "st,stm32-rtc";
- reg = <0x40002800 0x400>;
- clocks = <&rcc 1 CLK_RTC>;
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSE>;
- interrupt-parent = <&exti>;
- interrupts = <17 1>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- iwdg: watchdog@40003000 {
- compatible = "st,stm32-iwdg";
- reg = <0x40003000 0x400>;
- clocks = <&clk_lsi>;
- clock-names = "lsi";
- status = "disabled";
- };
-
- spi2: spi@40003800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40003800 0x400>;
- interrupts = <36>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
- status = "disabled";
- };
-
- spi3: spi@40003c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40003c00 0x400>;
- interrupts = <51>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
- status = "disabled";
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
- status = "disabled";
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
- status = "disabled";
- dmas = <&dma1 1 4 0x400 0x0>,
- <&dma1 3 4 0x400 0x0>;
- dma-names = "rx", "tx";
- };
-
- usart4: serial@40004c00 {
- compatible = "st,stm32-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
- status = "disabled";
- };
-
- usart5: serial@40005000 {
- compatible = "st,stm32-uart";
- reg = <0x40005000 0x400>;
- interrupts = <53>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
- status = "disabled";
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f4-i2c";
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f4-i2c";
- reg = <0x40005c00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@40006400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006400 0x200>;
- interrupts = <19>, <20>, <21>, <22>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
- st,can-primary;
- st,gcan = <&gcan>;
- status = "disabled";
- };
-
- gcan: gcan@40006600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40006600 0x200>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
- };
-
- can2: can@40006800 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006800 0x200>;
- interrupts = <63>, <64>, <65>, <66>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
- st,can-secondary;
- st,gcan = <&gcan>;
- status = "disabled";
- };
-
- dac: dac@40007400 {
- compatible = "st,stm32f4-dac-core";
- reg = <0x40007400 0x400>;
- resets = <&rcc STM32F4_APB1_RESET(DAC)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
- clock-names = "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dac1: dac@1 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <1>;
- status = "disabled";
- };
-
- dac2: dac@2 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <2>;
- status = "disabled";
- };
- };
-
- usart7: serial@40007800 {
- compatible = "st,stm32-uart";
- reg = <0x40007800 0x400>;
- interrupts = <82>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
- status = "disabled";
- };
-
- usart8: serial@40007c00 {
- compatible = "st,stm32-uart";
- reg = <0x40007c00 0x400>;
- interrupts = <83>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
- status = "disabled";
- };
-
- timers1: timers@40010000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010000 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
- };
-
- timers8: timers@40010400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010400 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
- status = "disabled";
- dmas = <&dma2 2 4 0x400 0x0>,
- <&dma2 7 4 0x400 0x0>;
- dma-names = "rx", "tx";
- };
-
- usart6: serial@40011400 {
- compatible = "st,stm32-uart";
- reg = <0x40011400 0x400>;
- interrupts = <71>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
- status = "disabled";
- };
-
- adc: adc@40012000 {
- compatible = "st,stm32f4-adc-core";
- reg = <0x40012000 0x400>;
- interrupts = <18>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
- clock-names = "adc";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
- interrupt-parent = <&adc>;
- interrupts = <0>;
- dmas = <&dma2 0 0 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
-
- adc2: adc@100 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x100>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
- interrupt-parent = <&adc>;
- interrupts = <1>;
- dmas = <&dma2 3 1 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
-
- adc3: adc@200 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x200>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
- interrupt-parent = <&adc>;
- interrupts = <2>;
- dmas = <&dma2 1 2 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
- };
-
- sdio: mmc@40012c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40012c00 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
- clock-names = "apb_pclk";
- interrupts = <49>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- spi1: spi@40013000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40013000 0x400>;
- interrupts = <35>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
- status = "disabled";
- };
-
- spi4: spi@40013400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40013400 0x400>;
- interrupts = <84>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
- status = "disabled";
- };
-
- syscfg: syscon@40013800 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x40013800 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>;
- };
-
- exti: interrupt-controller@40013c00 {
- compatible = "st,stm32-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x40013C00 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
- };
-
- timers9: timers@40014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40014000 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@8 {
- compatible = "st,stm32-timer-trigger";
- reg = <8>;
- status = "disabled";
- };
- };
-
- timers10: timers@40014400 {
- compatible = "st,stm32-timers";
- reg = <0x40014400 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers11: timers@40014800 {
- compatible = "st,stm32-timers";
- reg = <0x40014800 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- spi5: spi@40015000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40015000 0x400>;
- interrupts = <85>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
- dmas = <&dma2 3 2 0x400 0x0>,
- <&dma2 4 2 0x400 0x0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi6: spi@40015400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40015400 0x400>;
- interrupts = <86>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
- status = "disabled";
- };
-
- pwrcfg: power-config@40007000 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x40007000 0x400>;
- };
-
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
- clocks = <&rcc 1 CLK_LCD>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- crc: crc@40023000 {
- compatible = "st,stm32f4-crc";
- reg = <0x40023000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
- status = "disabled";
- };
-
- rcc: rcc@40023800 {
- #reset-cells = <1>;
- #clock-cells = <2>;
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
- reg = <0x40023800 0x400>;
- clocks = <&clk_hse>, <&clk_i2s_ckin>;
- st,syscfg = <&pwrcfg>;
- assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
- assigned-clock-rates = <1000000>;
- };
-
- dma1: dma-controller@40026000 {
- compatible = "st,stm32-dma";
- reg = <0x40026000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
- #dma-cells = <4>;
- };
-
- dma2: dma-controller@40026400 {
- compatible = "st,stm32-dma";
- reg = <0x40026400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
- #dma-cells = <4>;
- st,mem2mem;
- };
-
- mac: ethernet@40028000 {
- compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
- reg = <0x40028000 0x8000>;
- reg-names = "stmmaceth";
- interrupts = <61>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
- <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
- <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
- st,syscon = <&syscfg 0x4>;
- snps,pbl = <8>;
- snps,mixed-burst;
- status = "disabled";
- };
-
- dma2d: dma2d@4002b000 {
- compatible = "st,stm32-dma2d";
- reg = <0x4002b000 0xc00>;
- interrupts = <90>;
- resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
- clock-names = "dma2d";
- status = "disabled";
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "snps,dwc2";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
- clock-names = "otg";
- status = "disabled";
- };
-
- usbotg_fs: usb@50000000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x50000000 0x40000>;
- interrupts = <67>;
- clocks = <&rcc 0 39>;
- clock-names = "otg";
- status = "disabled";
- };
-
- dcmi: dcmi@50050000 {
- compatible = "st,stm32-dcmi";
- reg = <0x50050000 0x400>;
- interrupts = <78>;
- resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
- clock-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&dcmi_pins>;
- dmas = <&dma2 1 1 0x414 0x3>;
- dma-names = "tx";
- status = "disabled";
- };
-
- rng: rng@50060800 {
- compatible = "st,stm32-rng";
- reg = <0x50060800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
-
- };
- };
-};
-
-&systick {
- clocks = <&rcc 1 SYSTICK>;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts
deleted file mode 100644
index 943afba06b5f..000000000000
--- a/arch/arm/boot/dts/st/stm32f469-disco.dts
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f469.dtsi"
-#include "stm32f469-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32F469i-DISCO board";
- compatible = "st,stm32f469i-disco", "st,stm32f469";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x1000000>;
- };
-
- aliases {
- serial0 = &usart3;
- };
-
- vcc_3v3: vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- soc {
- dma-ranges = <0xc0000000 0x0 0x10000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
- };
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
- };
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-
- /* This turns on vbus for otg for host mode (dwc2) */
- vcc5v_otg: vcc5v-otg-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-};
-
-&rcc {
- compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
-};
-
-&clk_hse {
- clock-frequency = <8000000>;
-};
-
-&dma2d {
- status = "okay";
-};
-
-&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- remote-endpoint = <<dc_out_dsi>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- remote-endpoint = <&dsi_panel_in>;
- };
- };
- };
-
- panel@0 {
- compatible = "orisetech,otm8009a";
- reg = <0>; /* dsi virtual channel (0..3) */
- reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
- power-supply = <&vcc_3v3>;
- status = "okay";
-
- port {
- dsi_panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-};
-
-<dc {
- status = "okay";
-
- port {
- ltdc_out_dsi: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&timers1 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@0 {
- status = "okay";
- };
-};
-
-&timers3 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm3_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@2 {
- status = "okay";
- };
-};
-
-&sdio {
- status = "okay";
- vmmc-supply = <&vcc_3v3>;
- cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
- broken-cd;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_pins_od>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart3 {
- pinctrl-0 = <&usart3_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_fs {
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi
deleted file mode 100644
index 6bf60263dff8..000000000000
--- a/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "stm32f4-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f469-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 6>,
- <&pinctrl 12 156 4>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 3 163 5>;
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f469.dtsi b/arch/arm/boot/dts/st/stm32f469.dtsi
deleted file mode 100644
index be002e8a78ac..000000000000
--- a/arch/arm/boot/dts/st/stm32f469.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
-
-#include "stm32f429.dtsi"
-
-/ {
- soc {
- dsi: dsi@40016c00 {
- compatible = "st,stm32-dsi";
- reg = <0x40016c00 0x800>;
- resets = <&rcc STM32F4_APB2_RESET(DSI)>;
- reset-names = "apb";
- clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
- clock-names = "pclk", "ref";
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
deleted file mode 100644
index 97fc3fb5a9ca..000000000000
--- a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
+++ /dev/null
@@ -1,436 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-
-/ {
- soc {
- pinctrl: pinctrl@40020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
-
- gpioa: gpio@40020000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
- st,bank-name = "GPIOA";
- };
-
- gpiob: gpio@40020400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
- st,bank-name = "GPIOB";
- };
-
- gpioc: gpio@40020800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
- st,bank-name = "GPIOC";
- };
-
- gpiod: gpio@40020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
- st,bank-name = "GPIOD";
- };
-
- gpioe: gpio@40021000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
- st,bank-name = "GPIOE";
- };
-
- gpiof: gpio@40021400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
- st,bank-name = "GPIOF";
- };
-
- gpiog: gpio@40021800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
- st,bank-name = "GPIOG";
- };
-
- gpioh: gpio@40021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
- st,bank-name = "GPIOH";
- };
-
- gpioi: gpio@40022000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
- st,bank-name = "GPIOI";
- };
-
- gpioj: gpio@40022400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
- st,bank-name = "GPIOJ";
- };
-
- gpiok: gpio@40022800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
- st,bank-name = "GPIOK";
- };
-
- cec_pins_a: cec-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
- slew-rate = <0>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_pins_b: usart1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- i2c1_pins_b: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
- <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c3_pins_a: i2c3-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */
- <STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
- <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_hs_pins_b: usbotg-hs-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
- <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_fs_pins_a: usbotg-fs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
- <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_a: sdio-pins-a-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od_a: sdio-pins-od-a-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_sleep_a: sdio-pins-sleep-a-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1 D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1 D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1 D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1 D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1 CLK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1 CMD */
- };
- };
-
- sdio_pins_b: sdio-pins-b-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
- <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
- <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
- <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
- <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od_b: sdio-pins-od-b-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
- <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
- <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
- <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_sleep_b: sdio-pins-sleep-b-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 9, ANALOG)>, /* SDMMC2 D0 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* SDMMC2 D1 */
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2 D2 */
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2 D3 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC2 CLK */
- <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC2 CMD */
- };
- };
-
- can1_pins_a: can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can1_pins_b: can1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can1_pins_c: can1-2 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
- bias-pull-up;
-
- };
- };
-
- can1_pins_d: can1-3 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
- bias-pull-up;
-
- };
- };
-
- can2_pins_a: can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_b: can2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can3_pins_a: can3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
- bias-pull-up;
- };
- };
-
- can3_pins_b: can3-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
- bias-pull-up;
- };
- };
-
- ltdc_pins_a: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
- <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
- slew-rate = <2>;
- };
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts
deleted file mode 100644
index 61ca41ea523e..000000000000
--- a/arch/arm/boot/dts/st/stm32f746-disco.dts
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f746.dtsi"
-#include "stm32f746-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32F746-DISCO board";
- compatible = "st,stm32f746-disco", "st,stm32f746";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x800000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- no-map;
- size = <0x80000>;
- linux,dma-default;
- };
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led_usr: led-usr {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_HOME>;
- gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_usr>;
- };
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- /* This turns on vbus for otg fs for host mode (dwc2) */
- vcc5v_otg_fs: vcc5v-otg-fs-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpiod 5 0>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-
- vcc_3v3: vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- backlight: backlight {
- compatible = "gpio-backlight";
- gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- panel_rgb: panel-rgb {
- compatible = "rocktech,rk043fn48h";
- power-supply = <&vcc_3v3>;
- backlight = <&backlight>;
- enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
- status = "okay";
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-0 = <&i2c3_pins_a>;
- pinctrl-names = "default";
- clock-frequency = <400000>;
- status = "okay";
-
- touchscreen@38 {
- compatible = "edt,edt-ft5306";
- reg = <0x38>;
- interrupt-parent = <&gpioi>;
- interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
- touchscreen-size-x = <480>;
- touchscreen-size-y = <272>;
- };
-};
-
-<dc {
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&sdio1 {
- status = "okay";
- vmmc-supply = <&vcc_3v3>;
- cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdio_pins_a>;
- pinctrl-1 = <&sdio_pins_od_a>;
- pinctrl-2 = <&sdio_pins_sleep_a>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_fs {
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "host";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi
deleted file mode 100644
index 139f72b790c0..000000000000
--- a/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32f7-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f746-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi
deleted file mode 100644
index 208f8c6dfc9d..000000000000
--- a/arch/arm/boot/dts/st/stm32f746.dtsi
+++ /dev/null
@@ -1,727 +0,0 @@
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../armv7-m.dtsi"
-#include <dt-bindings/clock/stm32fx-clock.h>
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_i2s_ckin: clk-i2s-ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- };
- };
-
- soc {
- timers2: timers@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
- };
-
- timers3: timers@40000400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000400 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- timers4: timers@40000800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000800 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
- };
-
- timers5: timers@40000c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000C00 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
- };
-
- timers6: timers@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
- clock-names = "int";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timers@40001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001400 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
- clock-names = "int";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- timers12: timers@40001800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001800 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timers@40001c00 {
- compatible = "st,stm32-timers";
- reg = <0x40001C00 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers14: timers@40002000 {
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- lptimer1: timer@40002400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40002400 0x400>;
- interrupts-extended = <&exti 23 IRQ_TYPE_EDGE_RISING>;
- clocks = <&rcc 1 CLK_LPTIMER>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- rtc: rtc@40002800 {
- compatible = "st,stm32-rtc";
- reg = <0x40002800 0x400>;
- clocks = <&rcc 1 CLK_RTC>;
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSE>;
- interrupt-parent = <&exti>;
- interrupts = <17 1>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- spi2: spi@40003800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40003800 0x400>;
- interrupts = <36>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
- status = "disabled";
- };
-
- spi3: spi@40003c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40003c00 0x400>;
- interrupts = <51>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
- status = "disabled";
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- clocks = <&rcc 1 CLK_USART2>;
- status = "disabled";
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- clocks = <&rcc 1 CLK_USART3>;
- status = "disabled";
- };
-
- usart4: serial@40004c00 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- clocks = <&rcc 1 CLK_UART4>;
- status = "disabled";
- };
-
- usart5: serial@40005000 {
- compatible = "st,stm32f7-uart";
- reg = <0x40005000 0x400>;
- interrupts = <53>;
- clocks = <&rcc 1 CLK_UART5>;
- status = "disabled";
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
- clocks = <&rcc 1 CLK_I2C1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@40005800 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005800 0x400>;
- interrupts = <33>,
- <34>;
- resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
- clocks = <&rcc 1 CLK_I2C2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005c00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
- clocks = <&rcc 1 CLK_I2C3>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@40006000 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40006000 0x400>;
- interrupts = <95>,
- <96>;
- resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
- clocks = <&rcc 1 CLK_I2C4>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@40006400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006400 0x200>;
- interrupts = <19>, <20>, <21>, <22>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
- st,can-primary;
- st,gcan = <&gcan1>;
- status = "disabled";
- };
-
- gcan1: gcan@40006600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40006600 0x200>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
- };
-
- can2: can@40006800 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006800 0x200>;
- interrupts = <63>, <64>, <65>, <66>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
- st,can-secondary;
- st,gcan = <&gcan1>;
- status = "disabled";
- };
-
- cec: cec@40006c00 {
- compatible = "st,stm32-cec";
- reg = <0x40006C00 0x400>;
- interrupts = <94>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
- clock-names = "cec", "hdmi-cec";
- status = "disabled";
- };
-
- usart7: serial@40007800 {
- compatible = "st,stm32f7-uart";
- reg = <0x40007800 0x400>;
- interrupts = <82>;
- clocks = <&rcc 1 CLK_UART7>;
- status = "disabled";
- };
-
- usart8: serial@40007c00 {
- compatible = "st,stm32f7-uart";
- reg = <0x40007c00 0x400>;
- interrupts = <83>;
- clocks = <&rcc 1 CLK_UART8>;
- status = "disabled";
- };
-
- timers1: timers@40010000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010000 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
- };
-
- timers8: timers@40010400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010400 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32f7-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- clocks = <&rcc 1 CLK_USART1>;
- status = "disabled";
- };
-
- usart6: serial@40011400 {
- compatible = "st,stm32f7-uart";
- reg = <0x40011400 0x400>;
- interrupts = <71>;
- clocks = <&rcc 1 CLK_USART6>;
- status = "disabled";
- };
-
- sdio2: mmc@40011c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40011c00 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
- clock-names = "apb_pclk";
- interrupts = <103>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- sdio1: mmc@40012c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40012c00 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
- clock-names = "apb_pclk";
- interrupts = <49>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- spi1: spi@40013000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40013000 0x400>;
- interrupts = <35>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
- status = "disabled";
- };
-
- spi4: spi@40013400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40013400 0x400>;
- interrupts = <84>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
- status = "disabled";
- };
-
- syscfg: syscon@40013800 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x40013800 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
- };
-
- exti: interrupt-controller@40013c00 {
- compatible = "st,stm32-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x40013C00 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
- };
-
- timers9: timers@40014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40014000 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@8 {
- compatible = "st,stm32-timer-trigger";
- reg = <8>;
- status = "disabled";
- };
- };
-
- timers10: timers@40014400 {
- compatible = "st,stm32-timers";
- reg = <0x40014400 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers11: timers@40014800 {
- compatible = "st,stm32-timers";
- reg = <0x40014800 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- spi5: spi@40015000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40015000 0x400>;
- interrupts = <85>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
- status = "disabled";
- };
-
- spi6: spi@40015400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f7-spi";
- reg = <0x40015400 0x400>;
- interrupts = <86>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
- status = "disabled";
- };
-
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
- clocks = <&rcc 1 CLK_LCD>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- pwrcfg: power-config@40007000 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x40007000 0x400>;
- };
-
- crc: crc@40023000 {
- compatible = "st,stm32f7-crc";
- reg = <0x40023000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
- status = "disabled";
- };
-
- rcc: rcc@40023800 {
- #reset-cells = <1>;
- #clock-cells = <2>;
- compatible = "st,stm32f746-rcc", "st,stm32-rcc";
- reg = <0x40023800 0x400>;
- clocks = <&clk_hse>, <&clk_i2s_ckin>;
- st,syscfg = <&pwrcfg>;
- assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
- assigned-clock-rates = <1000000>;
- };
-
- dma1: dma-controller@40026000 {
- compatible = "st,stm32-dma";
- reg = <0x40026000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
- #dma-cells = <4>;
- status = "disabled";
- };
-
- dma2: dma-controller@40026400 {
- compatible = "st,stm32-dma";
- reg = <0x40026400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
- #dma-cells = <4>;
- st,mem2mem;
- status = "disabled";
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "st,stm32f7-hsotg";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
- clock-names = "otg";
- g-rx-fifo-size = <256>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- usbotg_fs: usb@50000000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x50000000 0x40000>;
- interrupts = <67>;
- clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
- clock-names = "otg";
- status = "disabled";
- };
- };
-};
-
-&systick {
- clocks = <&rcc 1 0>;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts b/arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts
deleted file mode 100644
index ff7ff32371d0..000000000000
--- a/arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
- */
-
-#include "stm32f769-disco.dts"
-
-&panel0 {
- compatible = "frida,frd400b25025", "novatek,nt35510";
- vddi-supply = <&vcc_3v3>;
- vdd-supply = <&vcc_3v3>;
- /delete-property/power-supply;
-};
diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts
deleted file mode 100644
index e5854fa1071b..000000000000
--- a/arch/arm/boot/dts/st/stm32f769-disco.dts
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32f769.dtsi"
-#include "stm32f769-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32F769-DISCO board";
- compatible = "st,stm32f769-disco", "st,stm32f769";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x1000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- linux,dma {
- compatible = "shared-dma-pool";
- linux,dma-default;
- no-map;
- size = <0x100000>;
- };
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led_usr2: led-usr2 {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- led-usr1 {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
- };
- led-usr3 {
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_HOME>;
- gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_usr2>;
- };
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- vcc_3v3: vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&rcc {
- compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
-};
-
-&cec {
- pinctrl-0 = <&cec_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- remote-endpoint = <<dc_out_dsi>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- remote-endpoint = <&dsi_panel_in>;
- };
- };
- };
-
- panel0: panel@0 {
- compatible = "orisetech,otm8009a";
- reg = <0>; /* dsi virtual channel (0..3) */
- reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>;
- power-supply = <&vcc_3v3>;
- status = "okay";
-
- port {
- dsi_panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-<dc {
- status = "okay";
-
- port {
- ltdc_out_dsi: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio2 {
- status = "okay";
- vmmc-supply = <&vcc_3v3>;
- cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
- broken-cd;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdio_pins_b>;
- pinctrl-1 = <&sdio_pins_od_b>;
- pinctrl-2 = <&sdio_pins_sleep_b>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi
deleted file mode 100644
index 02c2a8b08468..000000000000
--- a/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32f7-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f769-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32f769.dtsi b/arch/arm/boot/dts/st/stm32f769.dtsi
deleted file mode 100644
index e8cbb99e81a6..000000000000
--- a/arch/arm/boot/dts/st/stm32f769.dtsi
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
- */
-
-#include "stm32f746.dtsi"
-
-/ {
- soc {
- can3: can@40003400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40003400 0x200>;
- interrupts = <104>, <105>, <106>, <107>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
- st,gcan = <&gcan3>;
- status = "disabled";
- };
-
- gcan3: gcan@40003600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40003600 0x200>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
- };
-
- dsi: dsi@40016c00 {
- compatible = "st,stm32-dsi";
- reg = <0x40016c00 0x800>;
- clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
- clock-names = "pclk", "ref";
- resets = <&rcc STM32F7_APB2_RESET(DSI)>;
- reset-names = "apb";
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi
deleted file mode 100644
index 8a6db484383d..000000000000
--- a/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-&pinctrl {
-
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
- <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- ethernet_rmii: rmii-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 11, AF11)>,
- <STM32_PINMUX('G', 13, AF11)>,
- <STM32_PINMUX('G', 12, AF11)>,
- <STM32_PINMUX('C', 4, AF11)>,
- <STM32_PINMUX('C', 5, AF11)>,
- <STM32_PINMUX('A', 7, AF11)>,
- <STM32_PINMUX('C', 1, AF11)>,
- <STM32_PINMUX('A', 2, AF11)>,
- <STM32_PINMUX('A', 1, AF11)>;
- slew-rate = <2>;
- };
- };
-
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_dir_pins_a: sdmmc1-dir-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
- slew-rate = <3>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
- };
- };
-
- sdmmc2_b4_pins_a: sdmmc2-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- spi1_pins: spi1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 5, AF5)>,
- /* SPI1_CLK */
- <STM32_PINMUX('B', 5, AF5)>;
- /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 9, AF5)>;
- /* SPI1_MISO */
- bias-disable;
- };
- };
-
- uart4_pins_a: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart8_pins_a: uart8-0 {
- pins1 {
- pinmux = <STM32_PINMUX('J', 8, AF8)>; /* UART8_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('J', 9, AF8)>; /* UART8_RX */
- bias-disable;
- };
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_pins_b: usart1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart2_pins_a: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart3_pins_a: usart3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
- <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
- <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
- <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
- <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
- <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
- <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
- <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
- <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
- <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
- <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
- <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
- <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-};
-
diff --git a/arch/arm/boot/dts/st/stm32h743.dtsi b/arch/arm/boot/dts/st/stm32h743.dtsi
deleted file mode 100644
index 2f19cfbc57ad..000000000000
--- a/arch/arm/boot/dts/st/stm32h743.dtsi
+++ /dev/null
@@ -1,738 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../armv7-m.dtsi"
-#include <dt-bindings/clock/stm32h7-clks.h>
-#include <dt-bindings/mfd/stm32h7-rcc.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_i2s: i2s_ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
- };
-
- soc {
- timer5: timer@40000c00 {
- compatible = "st,stm32-timer";
- reg = <0x40000c00 0x400>;
- interrupts = <50>;
- clocks = <&rcc TIM5_CK>;
- };
-
- lptimer1: timer@40002400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40002400 0x400>;
- clocks = <&rcc LPTIM1_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- spi2: spi@40003800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40003800 0x400>;
- interrupts = <36>;
- resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
- clocks = <&rcc SPI2_CK>;
- status = "disabled";
-
- };
-
- spi3: spi@40003c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40003c00 0x400>;
- interrupts = <51>;
- resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
- clocks = <&rcc SPI3_CK>;
- status = "disabled";
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- status = "disabled";
- clocks = <&rcc USART2_CK>;
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- status = "disabled";
- clocks = <&rcc USART3_CK>;
- };
-
- uart4: serial@40004c00 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- status = "disabled";
- clocks = <&rcc UART4_CK>;
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
- clocks = <&rcc I2C1_CK>;
- status = "disabled";
- };
-
- i2c2: i2c@40005800 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005800 0x400>;
- interrupts = <33>,
- <34>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
- clocks = <&rcc I2C2_CK>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005C00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
- clocks = <&rcc I2C3_CK>;
- status = "disabled";
- };
-
- dac: dac@40007400 {
- compatible = "st,stm32h7-dac-core";
- reg = <0x40007400 0x400>;
- clocks = <&rcc DAC12_CK>;
- clock-names = "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dac1: dac@1 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <1>;
- status = "disabled";
- };
-
- dac2: dac@2 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <2>;
- status = "disabled";
- };
- };
-
- uart8: serial@40007c00 {
- compatible = "st,stm32h7-uart";
- reg = <0x40007c00 0x400>;
- interrupts = <83>;
- status = "disabled";
- clocks = <&rcc UART8_CK>;
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- status = "disabled";
- clocks = <&rcc USART1_CK>;
- };
-
- spi1: spi@40013000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40013000 0x400>;
- interrupts = <35>;
- resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
- clocks = <&rcc SPI1_CK>;
- status = "disabled";
- };
-
- spi4: spi@40013400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40013400 0x400>;
- interrupts = <84>;
- resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
- clocks = <&rcc SPI4_CK>;
- status = "disabled";
- };
-
- spi5: spi@40015000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40015000 0x400>;
- interrupts = <85>;
- resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
- clocks = <&rcc SPI5_CK>;
- status = "disabled";
- };
-
- dma1: dma-controller@40020000 {
- compatible = "st,stm32-dma";
- reg = <0x40020000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc DMA1_CK>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- status = "disabled";
- };
-
- dma2: dma-controller@40020400 {
- compatible = "st,stm32-dma";
- reg = <0x40020400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc DMA2_CK>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- status = "disabled";
- };
-
- dmamux1: dma-router@40020800 {
- compatible = "st,stm32h7-dmamux";
- reg = <0x40020800 0x40>;
- #dma-cells = <3>;
- dma-channels = <16>;
- dma-requests = <128>;
- dma-masters = <&dma1 &dma2>;
- clocks = <&rcc DMA1_CK>;
- };
-
- adc_12: adc@40022000 {
- compatible = "st,stm32h7-adc-core";
- reg = <0x40022000 0x400>;
- interrupts = <18>;
- clocks = <&rcc ADC12_CK>;
- clock-names = "bus";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- interrupt-parent = <&adc_12>;
- interrupts = <0>;
- status = "disabled";
- };
-
- adc2: adc@100 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x100>;
- interrupt-parent = <&adc_12>;
- interrupts = <1>;
- status = "disabled";
- };
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "st,stm32f7-hsotg";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc USB1OTG_CK>;
- clock-names = "otg";
- g-rx-fifo-size = <256>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- usbotg_fs: usb@40080000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x40080000 0x40000>;
- interrupts = <101>;
- clocks = <&rcc USB2OTG_CK>;
- clock-names = "otg";
- status = "disabled";
- };
-
- ltdc: display-controller@50001000 {
- compatible = "st,stm32-ltdc";
- reg = <0x50001000 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
- clocks = <&rcc LTDC_CK>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- mdma1: dma-controller@52000000 {
- compatible = "st,stm32h7-mdma";
- reg = <0x52000000 0x1000>;
- interrupts = <122>;
- clocks = <&rcc MDMA_CK>;
- #dma-cells = <5>;
- dma-channels = <16>;
- dma-requests = <32>;
- };
-
- sdmmc1: mmc@52007000 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x52007000 0x1000>;
- interrupts = <49>;
- clocks = <&rcc SDMMC1_CK>;
- clock-names = "apb_pclk";
- resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- };
-
- sdmmc2: mmc@48022400 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x48022400 0x400>;
- interrupts = <124>;
- clocks = <&rcc SDMMC2_CK>;
- clock-names = "apb_pclk";
- resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- status = "disabled";
- };
-
- exti: interrupt-controller@58000000 {
- compatible = "st,stm32h7-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x58000000 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
- };
-
- syscfg: syscon@58000400 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x58000400 0x400>;
- };
-
- spi6: spi@58001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x58001400 0x400>;
- interrupts = <86>;
- resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
- clocks = <&rcc SPI6_CK>;
- status = "disabled";
- };
-
- i2c4: i2c@58001c00 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x58001C00 0x400>;
- interrupts = <95>,
- <96>;
- resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
- clocks = <&rcc I2C4_CK>;
- status = "disabled";
- };
-
- lptimer2: timer@58002400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x58002400 0x400>;
- clocks = <&rcc LPTIM2_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@1 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- lptimer3: timer@58002800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x58002800 0x400>;
- clocks = <&rcc LPTIM3_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@2 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- lptimer4: timer@58002c00 {
- compatible = "st,stm32-lptimer";
- reg = <0x58002c00 0x400>;
- clocks = <&rcc LPTIM4_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- lptimer5: timer@58003000 {
- compatible = "st,stm32-lptimer";
- reg = <0x58003000 0x400>;
- clocks = <&rcc LPTIM5_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- vrefbuf: regulator@58003c00 {
- compatible = "st,stm32-vrefbuf";
- reg = <0x58003C00 0x8>;
- clocks = <&rcc VREF_CK>;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <2500000>;
- status = "disabled";
- };
-
- rtc: rtc@58004000 {
- compatible = "st,stm32h7-rtc";
- reg = <0x58004000 0x400>;
- clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
- clock-names = "pclk", "rtc_ck";
- assigned-clocks = <&rcc RTC_CK>;
- assigned-clock-parents = <&rcc LSE_CK>;
- interrupt-parent = <&exti>;
- interrupts = <17 IRQ_TYPE_EDGE_RISING>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- rcc: reset-clock-controller@58024400 {
- compatible = "st,stm32h743-rcc", "st,stm32-rcc";
- reg = <0x58024400 0x400>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
- st,syscfg = <&pwrcfg>;
- };
-
- pwrcfg: power-config@58024800 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x58024800 0x400>;
- };
-
- adc_3: adc@58026000 {
- compatible = "st,stm32h7-adc-core";
- reg = <0x58026000 0x400>;
- interrupts = <127>;
- clocks = <&rcc ADC3_CK>;
- clock-names = "bus";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc3: adc@0 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- interrupt-parent = <&adc_3>;
- interrupts = <0>;
- status = "disabled";
- };
- };
-
- mac: ethernet@40028000 {
- compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
- reg = <0x40028000 0x8000>;
- reg-names = "stmmaceth";
- interrupts = <61>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
- clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
- st,syscon = <&syscfg 0x4>;
- snps,pbl = <8>;
- status = "disabled";
- };
-
- pinctrl: pinctrl@58020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32h743-pinctrl";
- ranges = <0 0x58020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
-
- gpioa: gpio@58020000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc GPIOA_CK>;
- st,bank-name = "GPIOA";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@58020400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc GPIOB_CK>;
- st,bank-name = "GPIOB";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@58020800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc GPIOC_CK>;
- st,bank-name = "GPIOC";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@58020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc GPIOD_CK>;
- st,bank-name = "GPIOD";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@58021000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc GPIOE_CK>;
- st,bank-name = "GPIOE";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@58021400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc GPIOF_CK>;
- st,bank-name = "GPIOF";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@58021800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc GPIOG_CK>;
- st,bank-name = "GPIOG";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@58021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc GPIOH_CK>;
- st,bank-name = "GPIOH";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@58022000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc GPIOI_CK>;
- st,bank-name = "GPIOI";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@58022400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc GPIOJ_CK>;
- st,bank-name = "GPIOJ";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@58022800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc GPIOK_CK>;
- st,bank-name = "GPIOK";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
- };
- };
- };
-};
-
-&systick {
- clock-frequency = <250000000>;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts
deleted file mode 100644
index 78d55b77db7c..000000000000
--- a/arch/arm/boot/dts/st/stm32h743i-disco.dts
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright 2017 - Patrice Chotard <patrice.chotard@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32h743.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32H743i-Discovery board";
- compatible = "st,stm32h743i-disco", "st,stm32h743";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@d0000000 {
- device_type = "memory";
- reg = <0xd0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart2;
- };
-
- v3v3: regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- leds {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpioi 12 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
-
- led-orange {
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
- };
-
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpioi 14 GPIO_ACTIVE_LOW>;
- };
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&usart2 {
- pinctrl-0 = <&usart2_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts
deleted file mode 100644
index e5e10b0758ee..000000000000
--- a/arch/arm/boot/dts/st/stm32h743i-eval.dts
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32h743.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32H743i-EVAL board";
- compatible = "st,stm32h743i-eval", "st,stm32h743";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@d0000000 {
- device_type = "memory";
- reg = <0xd0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- led {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpiof 10 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-
- vdda: regulator-vdda {
- compatible = "regulator-fixed";
- regulator-name = "vdda";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- v2v9_sd: regulator-v2v9_sd {
- compatible = "regulator-fixed";
- regulator-name = "v2v9_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- regulator-always-on;
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc USB1ULPI_CK>;
- clock-names = "main_clk";
- };
-};
-
-&adc_12 {
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "okay";
- adc1: adc@0 {
- /* potentiometer */
- st,adc-channels = <0>;
- status = "okay";
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
- broken-cd;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&v2v9_sd>;
- status = "okay";
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- dr_mode = "otg";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/st/stm32h747i-disco.dts
deleted file mode 100644
index c9dcc680e26d..000000000000
--- a/arch/arm/boot/dts/st/stm32h747i-disco.dts
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2025 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
- */
-
-/dts-v1/;
-#include "stm32h743.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "STMicroelectronics STM32H747i-Discovery board";
- compatible = "st,stm32h747i-disco", "st,stm32h747";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@d0000000 {
- device_type = "memory";
- reg = <0xd0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- serial1 = &uart8;
- };
-
- v3v3: regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- leds {
- compatible = "gpio-leds";
- led_green: led-green {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpioi 12 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
- };
- led-red {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpioi 14 GPIO_ACTIVE_LOW>;
- };
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
- };
- button-1 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- gpios = <&gpiok 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- button-2 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- gpios = <&gpiok 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- button-3 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- gpios = <&gpiok 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- button-4 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- gpios = <&gpiok 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- button-5 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- gpios = <&gpiok 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- };
-
- options {
- u-boot {
- compatible = "u-boot,config";
- boot-led = <&led_green>;
- };
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&uart8 {
- pinctrl-0 = <&uart8_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/st/stm32h750.dtsi b/arch/arm/boot/dts/st/stm32h750.dtsi
deleted file mode 100644
index 41e3b1e3a874..000000000000
--- a/arch/arm/boot/dts/st/stm32h750.dtsi
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
-
-#include "stm32h743.dtsi"
-
-
diff --git a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts
deleted file mode 100644
index 56c53e262da7..000000000000
--- a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * For art-pi board resources, you can refer to link:
- * https://art-pi.gitee.io/website/
- */
-
-/dts-v1/;
-#include "stm32h750.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "RT-Thread STM32H750i-ART-PI board";
- compatible = "st,stm32h750i-art-pi", "st,stm32h750";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:2000000n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x2000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- no-map;
- size = <0x100000>;
- linux,dma-default;
- };
- };
-
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- };
-
- leds {
- compatible = "gpio-leds";
- led-red {
- gpios = <&gpioi 8 0>;
- };
- led-green {
- gpios = <&gpioc 15 0>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- v3v3: regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- wlan_pwr: regulator-wlan {
- compatible = "regulator-fixed";
-
- regulator-name = "wl-reg";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&dma1 {
- status = "okay";
-};
-
-&dma2 {
- status = "okay";
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
- broken-cd;
- non-removable;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&wlan_pwr>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-&spi1 {
- status = "okay";
- pinctrl-0 = <&spi1_pins>;
- pinctrl-names = "default";
- cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
- dmas = <&dmamux1 37 0x400 0x05>,
- <&dmamux1 38 0x400 0x05>;
- dma-names = "rx", "tx";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "winbond,w25q128", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <80000000>;
-
- partition@0 {
- label = "root filesystem";
- reg = <0 0x1000000>;
- };
- };
-};
-
-&usart2 {
- pinctrl-0 = <&usart2_pins_a>;
- pinctrl-names = "default";
- status = "disabled";
-};
-
-&usart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&usart3_pins_a>;
- dmas = <&dmamux1 45 0x400 0x05>,
- <&dmamux1 46 0x400 0x05>;
- dma-names = "rx", "tx";
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
- max-speed = <115200>;
- };
-};
-
-&uart4 {
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
deleted file mode 100644
index 7366aade19ad..000000000000
--- a/arch/arm/configs/stm32_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_POSIX_TIMERS is not set
-CONFIG_BASE_SMALL=y
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-# CONFIG_IO_URING is not set
-# CONFIG_ADVISE_SYSCALLS is not set
-# CONFIG_MMU is not set
-CONFIG_ARCH_STM32=y
-CONFIG_CPU_V7M_NUM_IRQ=240
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x90000000
-CONFIG_XIP_KERNEL=y
-CONFIG_XIP_PHYS_ADDR=0x08008000
-# CONFIG_SUSPEND is not set
-# CONFIG_GCC_PLUGINS is not set
-CONFIG_BINFMT_FLAT=y
-# CONFIG_COREDUMP is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_BLK_DEV is not set
-CONFIG_EEPROM_93CX6=y
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_STM32=y
-CONFIG_SERIAL_STM32_CONSOLE=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_STM32F4=y
-CONFIG_I2C_STM32F7=y
-CONFIG_GPIO_STMPE=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_MFD_STMPE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_STM32=y
-CONFIG_DMADEVICES=y
-CONFIG_STM32_DMA=y
-CONFIG_STM32_DMAMUX=y
-CONFIG_STM32_MDMA=y
-# CONFIG_COMMON_CLK_STM32MP is not set
-CONFIG_IIO=y
-CONFIG_STM32_ADC_CORE=y
-CONFIG_STM32_ADC=y
-CONFIG_EXT4_FS=y
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_NLS=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_SLUB_DEBUG is not set
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 4ac3384e397a..6ca8507f9451 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -1,17 +1,15 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_STM32
bool "STMicroelectronics STM32 family"
- depends on ARM_SINGLE_ARMV7M || ARCH_MULTI_V7
- select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
- select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
- select ARM_GIC if ARCH_MULTI_V7
- select ARM_PSCI if ARCH_MULTI_V7
+ depends on ARCH_MULTI_V7
+ select HAVE_ARM_ARCH_TIMER
+ select ARM_GIC
+ select ARM_PSCI
select ARM_AMBA
select ARCH_HAS_RESET_CONTROLLER
select CLKSRC_STM32
select PINCTRL
select RESET_CONTROLLER
- select STM32_EXTI if ARM_SINGLE_ARMV7M
select STM32_FIREWALL
help
Support for STMicroelectronics STM32MP1 processors using Cortex-A7
@@ -20,32 +18,6 @@ menuconfig ARCH_STM32
if ARCH_STM32
-if ARM_SINGLE_ARMV7M
-
-config MACH_STM32F429
- bool "STMicroelectronics STM32F429 (DEPRECATED)"
- default y
-
-config MACH_STM32F469
- bool "STMicroelectronics STM32F469 (DEPRECATED)"
- default y
-
-config MACH_STM32F746
- bool "STMicroelectronics STM32F746 (DEPRECATED)"
- default y
-
-config MACH_STM32F769
- bool "STMicroelectronics STM32F769 (DEPRECATED)"
- default y
-
-config MACH_STM32H743
- bool "STMicroelectronics STM32H743 (DEPRECATED)"
- default y
-
-endif # ARMv7-M
-
-if ARCH_MULTI_V7
-
config MACH_STM32MP157
bool "STMicroelectronics STM32MP157"
select ARM_ERRATA_814220
@@ -59,6 +31,4 @@ config MACH_STM32MP13
Support for STM32MP13 SoCs:
STM32MP131, STM32MP133, STM32MP135
-endif # ARMv7-A
-
endif
diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c
index e6233c8725ae..3d32ce2c1333 100644
--- a/arch/arm/mach-stm32/board-dt.c
+++ b/arch/arm/mach-stm32/board-dt.c
@@ -12,13 +12,6 @@
#endif
static const char *const stm32_compat[] __initconst = {
- "st,stm32f429",
- "st,stm32f469",
- "st,stm32f746",
- "st,stm32f769",
- "st,stm32h743",
- "st,stm32h747",
- "st,stm32h750",
"st,stm32mp131",
"st,stm32mp133",
"st,stm32mp135",
--
2.53.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 12/14] ARM: versatile: remove mps2 support
2026-09-14 14:08 [PATCH v2 00/14] ARM: deprecated platform removal Arnd Bergmann
` (4 preceding siblings ...)
2026-09-14 14:08 ` [PATCH v2 11/14] ARM: stm32: remove stm32f4/f7/h7 MCU support Arnd Bergmann
@ 2026-09-14 14:08 ` Arnd Bergmann
2026-09-16 8:11 ` Andi Shyti
2026-09-21 11:06 ` [PATCH v2 00/14] ARM: deprecated platform removal Yoshifumi SHU
2026-10-01 12:40 ` Krzysztof Kozlowski
7 siblings, 1 reply; 13+ messages in thread
From: Arnd Bergmann @ 2026-09-14 14:08 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, Liviu Dudau, Lorenzo Pieralisi, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andi Shyti,
Ethan Nelson-Moore, devicetree, linux-i2c, Sudeep Holla,
Vladimir Murzin
From: Arnd Bergmann <arnd@arndb.de>
The Arm mps2 platform is the reference implementation for Arm
microcontrollers and is useful for testing but not expected to be used
as a production device.
With all the Cortex-M based products gone, there is no longer a need
for a reference platform either, so remove it as well.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Linus Walleij <linusw@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Andi Shyti <andi.shyti@kernel.org>
Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Acked-by: Sudeep Holla <sudeep.holla@kernel.org>
Acked-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
I have separate patches to remove the now unused clocksource
and uart drivers for this machine.
---
arch/arm/Kconfig | 14 --
arch/arm/boot/dts/arm/Makefile | 3 -
arch/arm/boot/dts/arm/mps2-an385.dts | 92 -----------
arch/arm/boot/dts/arm/mps2-an399.dts | 92 -----------
arch/arm/boot/dts/arm/mps2.dtsi | 220 ---------------------------
arch/arm/configs/mps2_defconfig | 102 -------------
arch/arm/mach-versatile/Makefile | 3 -
arch/arm/mach-versatile/v2m-mps2.c | 17 ---
drivers/i2c/busses/Kconfig | 2 +-
9 files changed, 1 insertion(+), 544 deletions(-)
delete mode 100644 arch/arm/boot/dts/arm/mps2-an385.dts
delete mode 100644 arch/arm/boot/dts/arm/mps2-an399.dts
delete mode 100644 arch/arm/boot/dts/arm/mps2.dtsi
delete mode 100644 arch/arm/configs/mps2_defconfig
delete mode 100644 arch/arm/mach-versatile/v2m-mps2.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b569052bfba1..ffc2f305694c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -457,20 +457,6 @@ source "arch/arm/mach-zte/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
-config ARCH_MPS2
- bool "ARM MPS2 platform (DEPRECATED)"
- depends on ARM_SINGLE_ARMV7M
- select ARM_AMBA
- select CLKSRC_MPS2
- help
- Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
- with a range of available cores like Cortex-M3/M4/M7.
-
- Please, note that depends which Application Note is used memory map
- for the platform may vary, so adjustment of RAM base might be needed.
-
- This platform is scheduled for removal in early 2027
-
# Definitions to make life easier
config ARCH_ACORN
bool
diff --git a/arch/arm/boot/dts/arm/Makefile b/arch/arm/boot/dts/arm/Makefile
index 07ebb64e2cd0..c01593dd197d 100644
--- a/arch/arm/boot/dts/arm/Makefile
+++ b/arch/arm/boot/dts/arm/Makefile
@@ -3,9 +3,6 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \
integratorap.dtb \
integratorap-im-pd1.dtb \
integratorcp.dtb
-dtb-$(CONFIG_ARCH_MPS2) += \
- mps2-an385.dtb \
- mps2-an399.dtb
dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb \
arm-realview-pb11mp.dtb \
diff --git a/arch/arm/boot/dts/arm/mps2-an385.dts b/arch/arm/boot/dts/arm/mps2-an385.dts
deleted file mode 100644
index aebbebfc25d1..000000000000
--- a/arch/arm/boot/dts/arm/mps2-an385.dts
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (C) 2015 ARM Limited
- *
- * Author: Vladimir Murzin <vladimir.murzin@arm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "mps2.dtsi"
-
-/ {
- model = "ARM MPS2 Application Note 385/386";
- compatible = "arm,mps2";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:9600n8";
- };
-
- memory@21000000 {
- device_type = "memory";
- reg = <0x21000000 0x1000000>;
- };
-
- smb {
- ethernet@0,0 {
- compatible = "smsc,lan9220", "smsc,lan9115";
- reg = <0 0x0 0x10000>;
- interrupts = <13>;
- interrupt-parent = <&nvic>;
- smsc,irq-active-high;
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&timer0 {
- status = "okay";
-};
-
-&timer1 {
- status = "okay";
-};
-
-&wdt {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/arm/mps2-an399.dts b/arch/arm/boot/dts/arm/mps2-an399.dts
deleted file mode 100644
index 349abf70b2a5..000000000000
--- a/arch/arm/boot/dts/arm/mps2-an399.dts
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (C) 2015 ARM Limited
- *
- * Author: Vladimir Murzin <vladimir.murzin@arm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "mps2.dtsi"
-
-/ {
- model = "ARM MPS2 Application Note 399/400";
- compatible = "arm,mps2";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:9600n8";
- };
-
- memory@60000000 {
- device_type = "memory";
- reg = <0x60000000 0x1000000>;
- };
-
- smb {
- ethernet@1,0 {
- compatible = "smsc,lan9220", "smsc,lan9115";
- reg = <1 0x0 0x10000>;
- interrupts = <13>;
- interrupt-parent = <&nvic>;
- smsc,irq-active-high;
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&timer0 {
- status = "okay";
-};
-
-&timer1 {
- status = "okay";
-};
-
-&wdt {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/arm/mps2.dtsi b/arch/arm/boot/dts/arm/mps2.dtsi
deleted file mode 100644
index e240bc8aa605..000000000000
--- a/arch/arm/boot/dts/arm/mps2.dtsi
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (C) 2015 ARM Limited
- *
- * Author: Vladimir Murzin <vladimir.murzin@arm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../armv7-m.dtsi"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- oscclk0: clock-50000000 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- };
-
- oscclk1: clock-24576000 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- oscclk2: clock-25000000 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- cfgclk: clock-5000000 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <5000000>;
- };
-
- spicfgclk: clock-75000000 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <75000000>;
- };
-
- sysclk: spiclcd: spicon: i2cclcd: i2caud: clock-sys {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk0>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- audmclk: clk-12388000 {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk1>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- audsclk: clk-3072000 {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk1>;
- #clock-cells = <0>;
- clock-div = <8>;
- clock-mult = <1>;
- };
-
- soc {
- compatible = "simple-bus";
- ranges;
-
- apb@40000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40000000 0x10000>;
-
- timer0: mps2-timer0@0 {
- compatible = "arm,mps2-timer";
- reg = <0x0 0x1000>;
- interrupts = <8>;
- clocks = <&sysclk>;
- status = "disabled";
- };
-
- timer1: mps2-timer1@1000 {
- compatible = "arm,mps2-timer";
- reg = <0x1000 0x1000>;
- interrupts = <9>;
- clocks = <&sysclk>;
- status = "disabled";
- };
-
- timer2: dual-timer@2000 {
- compatible = "arm,sp804", "arm,primecell";
- reg = <0x2000 0x1000>;
- clocks = <&sysclk>, <&sysclk>, <&sysclk>;
- clock-names = "timer0clk", "timer1clk",
- "apb_pclk";
- interrupts = <10>;
- status = "disabled";
- };
-
- uart0: serial@4000 {
- compatible = "arm,mps2-uart";
- reg = <0x4000 0x1000>;
- interrupts = <0>, <1>, <12>;
- clocks = <&sysclk>;
- status = "disabled";
- };
-
- uart1: serial@5000 {
- compatible = "arm,mps2-uart";
- reg = <0x5000 0x1000>;
- interrupts = <2>, <3>, <12>;
- clocks = <&sysclk>;
- status = "disabled";
- };
-
- uart2: serial@6000 {
- compatible = "arm,mps2-uart";
- reg = <0x6000 0x1000>;
- interrupts = <4>, <5>, <12>;
- clocks = <&sysclk>;
- status = "disabled";
- };
-
- wdt: watchdog@8000 {
- compatible = "arm,sp805", "arm,primecell";
- arm,primecell-periphid = <0x00141805>;
- reg = <0x8000 0x1000>;
- interrupts = <0>;
- clocks = <&sysclk>, <&sysclk>;
- clock-names = "wdog_clk", "apb_pclk";
- status = "disabled";
- };
- };
- };
-
- fpga@40020000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40020000 0x10000>;
-
- fpgaio@8000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x8000 0x10>;
-
- ranges = <0x0 0x8000 0x10>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- led@0,0 {
- compatible = "register-bit-led";
- reg = <0x00 0x04>;
- offset = <0x0>;
- mask = <0x01>;
- label = "userled:0";
- linux,default-trigger = "heartbeat";
- default-state = "on";
- };
-
- led@0,1 {
- compatible = "register-bit-led";
- reg = <0x00 0x04>;
- offset = <0x0>;
- mask = <0x02>;
- label = "userled:1";
- linux,default-trigger = "usr";
- default-state = "off";
- };
- };
- };
-
- smb {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0x40200000 0x10000>,
- <1 0 0xa0000000 0x10000>;
- };
-};
diff --git a/arch/arm/configs/mps2_defconfig b/arch/arm/configs/mps2_defconfig
deleted file mode 100644
index cacf3876f6e4..000000000000
--- a/arch/arm/configs/mps2_defconfig
+++ /dev/null
@@ -1,102 +0,0 @@
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-CONFIG_BASE_SMALL=y
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-# CONFIG_MMU is not set
-CONFIG_ARCH_MPS2=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x21000000
-CONFIG_DRAM_SIZE=0x1000000
-# CONFIG_SUSPEND is not set
-# CONFIG_BLOCK is not set
-CONFIG_BINFMT_FLAT=y
-# CONFIG_COREDUMP is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_CORE is not set
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_CADENCE is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_EZCHIP is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_HISILICON is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_QUALCOMM is not set
-# CONFIG_NET_VENDOR_RENESAS is not set
-# CONFIG_NET_VENDOR_ROCKER is not set
-# CONFIG_NET_VENDOR_SAMSUNG is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMSC911X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_MPS2_UART_CONSOLE=y
-CONFIG_SERIAL_MPS2_UART=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_ARM_SP805_WATCHDOG=y
-CONFIG_MFD_SYSCON=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_SYSCON=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_ARM_TIMER_SP804=y
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_DEBUG_FS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_MEMTEST=y
diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile
index d819fb2fc450..07171ef1d6a7 100644
--- a/arch/arm/mach-versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
@@ -22,9 +22,6 @@ obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o
CFLAGS_tc2_pm.o += -march=armv7-a
CFLAGS_REMOVE_tc2_pm.o = -pg
-# mps2
-obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o
-
ifdef CONFIG_SMP
obj-y += headsmp.o platsmp.o
obj-$(CONFIG_ARCH_REALVIEW) += platsmp-realview.o
diff --git a/arch/arm/mach-versatile/v2m-mps2.c b/arch/arm/mach-versatile/v2m-mps2.c
deleted file mode 100644
index 5b50d8e95cd7..000000000000
--- a/arch/arm/mach-versatile/v2m-mps2.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2015 ARM Limited
- *
- * Author: Vladimir Murzin <vladimir.murzin@arm.com>
- */
-
-#include <asm/mach/arch.h>
-
-static const char *const mps2_compat[] __initconst = {
- "arm,mps2",
- NULL
-};
-
-DT_MACHINE_START(MPS2DT, "MPS2 (Device Tree Support)")
- .dt_compat = mps2_compat,
-MACHINE_END
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d7b89508311f..9d60d4b650ec 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1260,7 +1260,7 @@ config I2C_UNIPHIER_F
config I2C_VERSATILE
tristate "ARM Versatile/Realview I2C bus support"
- depends on ARCH_MPS2 || ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS || COMPILE_TEST
+ depends on ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS || COMPILE_TEST
select I2C_ALGOBIT
help
Say yes if you want to support the I2C serial bus on ARMs Versatile
--
2.53.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 12/14] ARM: versatile: remove mps2 support
2026-09-14 14:08 ` [PATCH v2 12/14] ARM: versatile: remove mps2 support Arnd Bergmann
@ 2026-09-16 8:11 ` Andi Shyti
0 siblings, 0 replies; 13+ messages in thread
From: Andi Shyti @ 2026-09-16 8:11 UTC (permalink / raw)
To: Arnd Bergmann
Cc: soc, Arnd Bergmann, Liviu Dudau, Lorenzo Pieralisi, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ethan Nelson-Moore, devicetree, linux-i2c, Sudeep Holla,
Vladimir Murzin
Hi Arnd,
On Mon, Sep 14, 2026 at 04:08:14PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Arm mps2 platform is the reference implementation for Arm
> microcontrollers and is useful for testing but not expected to be used
> as a production device.
>
> With all the Cortex-M based products gone, there is no longer a need
> for a reference platform either, so remove it as well.
>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: Linus Walleij <linusw@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Andi Shyti <andi.shyti@kernel.org>
> Cc: Ethan Nelson-Moore <enelsonmoore@gmail.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-i2c@vger.kernel.org
> Acked-by: Sudeep Holla <sudeep.holla@kernel.org>
> Acked-by: Vladimir Murzin <vladimir.murzin@arm.com>
> Acked-by: Linus Walleij <linusw@kernel.org>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Thanks,
Andi
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 00/14] ARM: deprecated platform removal
2026-09-14 14:08 [PATCH v2 00/14] ARM: deprecated platform removal Arnd Bergmann
` (5 preceding siblings ...)
2026-09-14 14:08 ` [PATCH v2 12/14] ARM: versatile: remove mps2 support Arnd Bergmann
@ 2026-09-21 11:06 ` Yoshifumi SHU
2026-09-25 13:30 ` Linus Walleij
2026-10-01 12:40 ` Krzysztof Kozlowski
7 siblings, 1 reply; 13+ messages in thread
From: Yoshifumi SHU @ 2026-09-21 11:06 UTC (permalink / raw)
To: arnd
Cc: Frank.Li, aaro.koskinen, alexander.sverdlin, alexandre.belloni,
alexandre.torgue, andreas, andrew, arnd, claudiu.beznea, conor+dt,
david, devicetree, enelsonmoore, festevam, geert, gregory.clement,
imx, kernel, khilman, kmehltretter, kristoffer.ericson, krzk,
linusw, linux-arm-kernel, linux-doc, linux-kernel, linux-omap,
linux-stm32, linux, liviu.dudau, lpieralisi, mcoquelin.stm32,
nicolas.ferre, npitre, robert.jarzmik, robh, rogerq, s.hauer,
sebastian.hesselbarth, shawnguo, soc, stefan, sudeep.holla, tony,
vz, thehajime
Hi Arnd and all,
I would like to request that the core Arm Cortex-M support be retained, specifically for v8-M.
I'm heavily using Arm Cortex-M / NOMMU Linux for academic research.
In particular, I frequently run Linux on newer Arm v8-M (Cortex-M33/M55/M85) processors.
However, dropping CONFIG_CPU_V7M also removes support for these newer CPUs.
Because v8-M is highly compatible with the older v7-M (Cortex-M3/M4/M7), the v8-M support is tightly coupled with CONFIG_CPU_V7M, despite the name.
The major differences are essentially CPU IDs and PMSAv8 MPU support.
So I need the majority of CONFIG_CPU_V7M to support Arm v8-M.
Regarding platform support, I don't need Linux-side device drivers.
In my current setup, Linux runs in a virtualized environment hosted by an RTOS (like Zephyr) and accesses devices through virtio served by the RTOS.
I also understand that maintaining legacy MCU platform support is a significant burden.
Therefore, I don't object to removing the platform support, though the MPS platform remains convenient for bare-metal testing.
I am willing to help maintain this support, including modernizing the relevant code. I can regularly test kernels on real Armv8-M hardware.
If an active maintainer is required to keep the support, I am willing to take on that responsibility.
Please let me know how I can help keep the support.
Thanks,
Yoshifumi
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 06/14] ARM: omap2: remove omap24xx support
2026-09-14 14:08 ` [PATCH v2 06/14] ARM: omap2: remove omap24xx support Arnd Bergmann
@ 2026-09-21 16:06 ` Kevin Hilman
0 siblings, 0 replies; 13+ messages in thread
From: Kevin Hilman @ 2026-09-21 16:06 UTC (permalink / raw)
To: Arnd Bergmann, soc
Cc: Arnd Bergmann, Andreas Kemnade, Roger Quadros, Tony Lindgren,
Paul Walmsley, Herbert Xu, David S. Miller, Mauro Carvalho Chehab,
Kyungmin Park, Helge Deller, Tero Kristo, Stephen Boyd,
linux-kernel, linux-omap, devicetree, linux-media, linux-mtd,
linux-fbdev, dri-devel, linux-clk, Thomas Zimmermann,
Aaro Koskinen
Arnd Bergmann <arnd@kernel.org> writes:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The omap24xx SoC platform was used in the Nokia N800 and N810 tablets
> released on 2007 and was among the first ARMv6 CPUs in products that
> made it into products.
>
> Unfortunately the early ARM1136r0 CPU cores had a number of quirks that
> caused a disproportionate amount of work to keep them compatible with
> later ARMv6K/v7/v8 implementations.
>
> Drop the support for this SoC in order to allow removing ARM1136r0.
>
> Cc: Andreas Kemnade <andreas@kemnade.info>
> Cc: Kevin Hilman <khilman@baylibre.com>
> Cc: Roger Quadros <rogerq@kernel.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Paul Walmsley <paul@pwsan.com>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: "David S. Miller" <davem@davemloft.net>
> Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
> Cc: Kyungmin Park <kyungmin.park@samsung.com>
> Cc: Helge Deller <deller@gmx.de>
> Cc: Tero Kristo <kristo@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-omap@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-media@vger.kernel.org
> Cc: linux-mtd@lists.infradead.org
> Cc: linux-fbdev@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-clk@vger.kernel.org
> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> # omapfb
> Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kevin Hilman <khilman@baylibre.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 00/14] ARM: deprecated platform removal
2026-09-21 11:06 ` [PATCH v2 00/14] ARM: deprecated platform removal Yoshifumi SHU
@ 2026-09-25 13:30 ` Linus Walleij
2026-09-26 19:29 ` Yoshifumi SHU
0 siblings, 1 reply; 13+ messages in thread
From: Linus Walleij @ 2026-09-25 13:30 UTC (permalink / raw)
To: Yoshifumi SHU
Cc: arnd, Frank.Li, aaro.koskinen, alexander.sverdlin,
alexandre.belloni, alexandre.torgue, andreas, andrew, arnd,
claudiu.beznea, conor+dt, david, devicetree, enelsonmoore,
festevam, geert, gregory.clement, imx, kernel, khilman,
kmehltretter, kristoffer.ericson, krzk, linux-arm-kernel,
linux-doc, linux-kernel, linux-omap, linux-stm32, linux,
liviu.dudau, lpieralisi, mcoquelin.stm32, nicolas.ferre, npitre,
robert.jarzmik, robh, rogerq, s.hauer, sebastian.hesselbarth,
shawnguo, soc, stefan, sudeep.holla, tony, vz, thehajime
On Mon, Sep 21, 2026 at 1:06 PM Yoshifumi SHU <envzhu@gmail.com> wrote:
> I would like to request that the core Arm Cortex-M support be retained, specifically for v8-M.
(...)
> I am willing to help maintain this support, including modernizing the relevant code. I can regularly test kernels on real Armv8-M hardware.
> If an active maintainer is required to keep the support, I am willing to take on that responsibility.
> Please let me know how I can help keep the support.
All right, now we're talking! Could you test and review this patch:
https://lore.kernel.org/linux-arm-kernel/20260910-arm-generic-irq-entry-v7-1-v3-1-5fd90f6859e1@kernel.org/
I do avoid touching the v7m path and it worked last time I tested
it (on an STM32) but I'd like to see your take on it, AFAICT generic
entry is not really possible (easily) on v7m because of the
pendable service call mechanism but maybe we can think of a
really complicated solution? ;)
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 00/14] ARM: deprecated platform removal
2026-09-25 13:30 ` Linus Walleij
@ 2026-09-26 19:29 ` Yoshifumi SHU
0 siblings, 0 replies; 13+ messages in thread
From: Yoshifumi SHU @ 2026-09-26 19:29 UTC (permalink / raw)
To: Linus Walleij
Cc: arnd, Frank.Li, aaro.koskinen, alexander.sverdlin,
alexandre.belloni, alexandre.torgue, andreas, andrew, arnd,
claudiu.beznea, conor+dt, david, devicetree, enelsonmoore,
festevam, geert, gregory.clement, imx, kernel, khilman,
kmehltretter, kristoffer.ericson, krzk, linux-arm-kernel,
linux-doc, linux-kernel, linux-omap, linux-stm32, linux,
liviu.dudau, lpieralisi, mcoquelin.stm32, nicolas.ferre, npitre,
robert.jarzmik, robh, rogerq, s.hauer, sebastian.hesselbarth,
shawnguo, soc, stefan, sudeep.holla, tony, vz, thehajime
On 2026/09/25 22:30, Linus Walleij wrote:
> All right, now we're talking! Could you test and review this patch:
> https://lore.kernel.org/linux-arm-kernel/20260910-arm-generic-irq-entry-v7-1-v3-1-5fd90f6859e1@kernel.org/
Thanks! I'll take a closer look at the patch and the discussion thread.
> I do avoid touching the v7m path and it worked last time I tested
> it (on an STM32) but I'd like to see your take on it, AFAICT generic
> entry is not really possible (easily) on v7m because of the
> pendable service call mechanism but maybe we can think of a
> really complicated solution? ;)
I have experience wrestling with a PendSV-related problem in an RTOS kernel,
so I believe I can contribute to that part!
Best regards,
Yoshifumi SHU
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 00/14] ARM: deprecated platform removal
2026-09-14 14:08 [PATCH v2 00/14] ARM: deprecated platform removal Arnd Bergmann
` (6 preceding siblings ...)
2026-09-21 11:06 ` [PATCH v2 00/14] ARM: deprecated platform removal Yoshifumi SHU
@ 2026-10-01 12:40 ` Krzysztof Kozlowski
7 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2026-10-01 12:40 UTC (permalink / raw)
To: soc, Arnd Bergmann
Cc: Arnd Bergmann, Rob Herring, Conor Dooley, Russell King,
Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vladimir Zapolskiy, Stefan Agner, Maxime Coquelin,
Alexandre Torgue, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Nicolas Ferre, Alexandre Belloni,
Claudiu Beznea, Andrew Lunn, Sebastian Hesselbarth,
Gregory Clement, Robert Jarzmik, Kristoffer Ericson,
Linus Walleij, Ethan Nelson-Moore, Geert Uytterhoeven,
Alexander Sverdlin, Shawn Guo, Karl Mehltretter,
David Hildenbrand (Arm), Nicolas Pitre, linux-doc, linux-kernel,
linux-arm-kernel, devicetree, imx, linux-stm32, linux-omap
On Mon, 14 Sep 2026 16:08:02 +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> In the 7.3 kernel, I marked a number of platforms and features as
> deprecated, with the plan to keep these around for the LTS kernel, but
> remove them in 7.4, see [1].
>
> Cleaning out the deprecated platform code has turned into a larger effort
> than I expected, currently standing at 300 patches, with a lot of them
> still in need of being split up into smaller ones, see [2] for a current
> snapshot.
>
> [...]
Applied, thanks!
[01/14] ARM: remove sa1100 platform
https://git.kernel.org/soc/soc/c/95664df86fdf6e70e411ad9e3910b402489a22c3
[02/14] ARM: remove footbridge
https://git.kernel.org/soc/soc/c/21b5f207cb8b1d0a819dd1799ef8c56178d5b1d7
[03/14] ARM: remove legacy pxa board files
https://git.kernel.org/soc/soc/c/538532cd1532f44e7c2519ecd3dfbcbed08061e2
[04/14] ARM: orion/dove/mv78xx0: remove all board files
https://git.kernel.org/soc/soc/c/f98cb2a43e0efa32ed8723df8d687acdb69dab06
[05/14] ARM: orion5x: fold plat-orion/pcie.c and hw_pci into pci.c
https://git.kernel.org/soc/soc/c/4fa61946d7c3e6da57a6db11551fa2ac17078370
[06/14] ARM: omap2: remove omap24xx support
https://git.kernel.org/soc/soc/c/cbd33c61480b8fa64046d956f4f68bca5cf68fbe
[07/14] ARM: imx: remove i.MX31 SoC support
https://git.kernel.org/soc/soc/c/104a7a07163962fe259a2e5272fb70446f19793b
[08/14] ARM: versatile: remove Integrator/CM1136JF-S option
https://git.kernel.org/soc/soc/c/1fbbfb51f20f3d0a1da6b542d7f29acc29815403
[09/14] ARM: imx: remove nommu support
https://git.kernel.org/soc/soc/c/2e1031df3c5f64f96660074f695e3b24e4bd3018
[10/14] ARM: lpc18xx: remove entire platform
https://git.kernel.org/soc/soc/c/31431dc97977003efbd4fb25e77aec8744338280
[11/14] ARM: stm32: remove stm32f4/f7/h7 MCU support
https://git.kernel.org/soc/soc/c/6fa463cad26fed984b62a764345e65a98fd0a30a
[12/14] ARM: versatile: remove mps2 support
https://git.kernel.org/soc/soc/c/1b983b0549163d4016574b0043664cdb47eea8cd
[13/14] ARM: at91: remove samv7 support
https://git.kernel.org/soc/soc/c/1b9867b95e1e4a88c80b2e5612b7092b90ae3f88
[14/14] ARM: axxia: remove entire platform
https://git.kernel.org/soc/soc/c/af4f7acd7b73780c7fece5d156e7d9a7791a60af
Best regards,
--
Krzysztof Kozlowski <krzk@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-10-01 12:40 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-14 14:08 [PATCH v2 00/14] ARM: deprecated platform removal Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 06/14] ARM: omap2: remove omap24xx support Arnd Bergmann
2026-09-21 16:06 ` Kevin Hilman
2026-09-14 14:08 ` [PATCH v2 07/14] ARM: imx: remove i.MX31 SoC support Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 09/14] ARM: imx: remove nommu support Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 10/14] ARM: lpc18xx: remove entire platform Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 11/14] ARM: stm32: remove stm32f4/f7/h7 MCU support Arnd Bergmann
2026-09-14 14:08 ` [PATCH v2 12/14] ARM: versatile: remove mps2 support Arnd Bergmann
2026-09-16 8:11 ` Andi Shyti
2026-09-21 11:06 ` [PATCH v2 00/14] ARM: deprecated platform removal Yoshifumi SHU
2026-09-25 13:30 ` Linus Walleij
2026-09-26 19:29 ` Yoshifumi SHU
2026-10-01 12:40 ` Krzysztof Kozlowski
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