[PATCH] arm64: dts: ti: k3-pinctrl: Add virtual GPIO select mux macros

[PATCH] arm64: dts: ti: k3-pinctrl: Add virtual GPIO select mux macros

[Akashdeep Kaur]

Add virtual GPIO select mux macros to allow users to select GPIO
controller bank for pins. The two GPIO controller instances in the
MAIN domain share physical pins, and the vgpio_sel field routes each
pin to either bank 0 or bank 2, enabling GPIO partitioning between
software domains as documented in Technical Reference Manual[1]. The
pad configuration register field description can be referenced at [2].

[1] AM62L TRM (section 10.6): https://www.ti.com/lit/ug/sprujb4a/sprujb4a.pdf
[2] AM62L TRM (section 14.2.1.2.1): https://www.ti.com/lit/ug/sprujb4a/sprujb4a.pdf

Signed-off-by: Akashdeep Kaur <a-kaur@ti.com>
---
 arch/arm64/boot/dts/ti/k3-pinctrl.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
index 4491898d8294..d42c466fcc7b 100644
--- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
+++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
@@ -3,11 +3,12 @@
  * This header provides constants for pinctrl bindings for TI's K3 SoC
  * family.
  *
- * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2026 Texas Instruments Incorporated - https://www.ti.com/
  */
 #ifndef DTS_ARM64_TI_K3_PINCTRL_H
 #define DTS_ARM64_TI_K3_PINCTRL_H
 
+#define VGPIO_SEL_SHIFT         (4)
 #define WKUP_LVL_EN_SHIFT	(7)
 #define WKUP_LVL_POL_SHIFT	(8)
 #define DEBOUNCE_SHIFT		(11)
@@ -111,6 +112,9 @@
 #define PIN_WKUP_EN_LEVEL_HIGH		(WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH)
 #define PIN_WKUP_EN			(WKUP_ENABLE | WKUP_ON_EDGE)
 
+#define PIN_VGPIO_SEL0                  (0 << VGPIO_SEL_SHIFT)
+#define PIN_VGPIO_SEL2                  (1 << VGPIO_SEL_SHIFT)
+
 /* Default mux configuration for gpio-ranges to use with pinctrl */
 #define PIN_GPIO_RANGE_IOPAD	(PIN_INPUT | 7)
 
-- 
2.34.1

Re: [PATCH] arm64: dts: ti: k3-pinctrl: Add virtual GPIO select mux macros

[Kendall Willis]

On 9/17/26 06:15, Akashdeep Kaur wrote:
> Add virtual GPIO select mux macros to allow users to select GPIO
> controller bank for pins. The two GPIO controller instances in the
> MAIN domain share physical pins, and the vgpio_sel field routes each
> pin to either bank 0 or bank 2, enabling GPIO partitioning between
> software domains as documented in Technical Reference Manual[1]. The
> pad configuration register field description can be referenced at [2].
> 
> [1] AM62L TRM (section 10.6): https://www.ti.com/lit/ug/sprujb4a/sprujb4a.pdf
> [2] AM62L TRM (section 14.2.1.2.1): https://www.ti.com/lit/ug/sprujb4a/sprujb4a.pdf
> 
> Signed-off-by: Akashdeep Kaur <a-kaur@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-pinctrl.h | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> index 4491898d8294..d42c466fcc7b 100644
> --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
> +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> @@ -3,11 +3,12 @@
>    * This header provides constants for pinctrl bindings for TI's K3 SoC
>    * family.
>    *
> - * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2018-2026 Texas Instruments Incorporated - https://www.ti.com/
>    */
>   #ifndef DTS_ARM64_TI_K3_PINCTRL_H
>   #define DTS_ARM64_TI_K3_PINCTRL_H
>   
> +#define VGPIO_SEL_SHIFT         (4)
>   #define WKUP_LVL_EN_SHIFT	(7)
>   #define WKUP_LVL_POL_SHIFT	(8)
>   #define DEBOUNCE_SHIFT		(11)
> @@ -111,6 +112,9 @@
>   #define PIN_WKUP_EN_LEVEL_HIGH		(WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH)
>   #define PIN_WKUP_EN			(WKUP_ENABLE | WKUP_ON_EDGE)
>   
> +#define PIN_VGPIO_SEL0                  (0 << VGPIO_SEL_SHIFT)
> +#define PIN_VGPIO_SEL2                  (1 << VGPIO_SEL_SHIFT)

Would a better name be PIN_VGPIO_SEL_GPIO0 and PIN_VGPIO_SEL_GPIO2 so 
that it is clear to users which GPIO bank they're using?

Best,
Kendall

> +
>   /* Default mux configuration for gpio-ranges to use with pinctrl */
>   #define PIN_GPIO_RANGE_IOPAD	(PIN_INPUT | 7)
>   

Re: [PATCH] arm64: dts: ti: k3-pinctrl: Add virtual GPIO select mux macros

[Vignesh Raghavendra]

On 17/09/26 16:45, Akashdeep Kaur wrote:
> Add virtual GPIO select mux macros to allow users to select GPIO
> controller bank for pins. The two GPIO controller instances in the
> MAIN domain share physical pins, and the vgpio_sel field routes each
> pin to either bank 0 or bank 2, enabling GPIO partitioning between
> software domains as documented in Technical Reference Manual[1]. The
> pad configuration register field description can be referenced at [2].
> 
> [1] AM62L TRM (section 10.6): https://www.ti.com/lit/ug/sprujb4a/sprujb4a.pdf
> [2] AM62L TRM (section 14.2.1.2.1): https://www.ti.com/lit/ug/sprujb4a/sprujb4a.pdf
> 
> Signed-off-by: Akashdeep Kaur <a-kaur@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-pinctrl.h | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> index 4491898d8294..d42c466fcc7b 100644
> --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
> +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> @@ -3,11 +3,12 @@
>   * This header provides constants for pinctrl bindings for TI's K3 SoC
>   * family.
>   *
> - * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2018-2026 Texas Instruments Incorporated - https://www.ti.com/
>   */
>  #ifndef DTS_ARM64_TI_K3_PINCTRL_H
>  #define DTS_ARM64_TI_K3_PINCTRL_H
>  
> +#define VGPIO_SEL_SHIFT         (4)
>  #define WKUP_LVL_EN_SHIFT	(7)
>  #define WKUP_LVL_POL_SHIFT	(8)
>  #define DEBOUNCE_SHIFT		(11)
> @@ -111,6 +112,9 @@
>  #define PIN_WKUP_EN_LEVEL_HIGH		(WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH)
>  #define PIN_WKUP_EN			(WKUP_ENABLE | WKUP_ON_EDGE)
>  
> +#define PIN_VGPIO_SEL0                  (0 << VGPIO_SEL_SHIFT)
> +#define PIN_VGPIO_SEL2                  (1 << VGPIO_SEL_SHIFT)
> +

Unfortunately, this field has different meaning in different SoCs. Here
is the definition from J784s4:

Note this field  is irrelevant when Muxmode is not 7.
for MAIN GPIO
00 = GPIO0 or 1 depending on the specific pin (meaning if mode 7 has
GPIO0.x then it is GPIO0 and if GPIO1.x then GPIO1)
01 - GPIO2 or 3 depending on the specific pin (meaning if mode 7 has
GPIO0.x then it is GPIO2 and if GPIO1.x then GPIO3)
10 - GPIO4 or 5 depending on the specific pin (meaning if mode 7 has
GPIO0.x then it is GPIO4 and if GPIO1.x then GPIO5)
11 - GPIO6 or 7 depending on the specific pin (meaning if mode 7 has
GPIO0.x then it is GPIO6 and if GPIO1.x then GPIO7)
Note this field  is irrelevant when Muxmode is not 7.

Thus, macros need to be generic or it should just open code the constant.

>  /* Default mux configuration for gpio-ranges to use with pinctrl */
>  #define PIN_GPIO_RANGE_IOPAD	(PIN_INPUT | 7)
>  

-- 
Regards
Vignesh
https://ti.com/opensource

Re: [PATCH] arm64: dts: ti: k3-pinctrl: Add virtual GPIO select mux macros

[Akashdeep Kaur]

Hi Vignesh,

On 18/09/26 13:57, Vignesh Raghavendra wrote:
> 
> 
> On 17/09/26 16:45, Akashdeep Kaur wrote:
>> Add virtual GPIO select mux macros to allow users to select GPIO
>> controller bank for pins. The two GPIO controller instances in the
>> MAIN domain share physical pins, and the vgpio_sel field routes each
...
>>   
>> +#define VGPIO_SEL_SHIFT         (4)
>>   #define WKUP_LVL_EN_SHIFT	(7)
>>   #define WKUP_LVL_POL_SHIFT	(8)
>>   #define DEBOUNCE_SHIFT		(11)
>> @@ -111,6 +112,9 @@
>>   #define PIN_WKUP_EN_LEVEL_HIGH		(WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH)
>>   #define PIN_WKUP_EN			(WKUP_ENABLE | WKUP_ON_EDGE)
>>   
>> +#define PIN_VGPIO_SEL0                  (0 << VGPIO_SEL_SHIFT)
>> +#define PIN_VGPIO_SEL2                  (1 << VGPIO_SEL_SHIFT)
>> +
> 
> Unfortunately, this field has different meaning in different SoCs. Here
> is the definition from J784s4:
> 
> Note this field  is irrelevant when Muxmode is not 7.
> for MAIN GPIO
> 00 = GPIO0 or 1 depending on the specific pin (meaning if mode 7 has
> GPIO0.x then it is GPIO0 and if GPIO1.x then GPIO1)
> 01 - GPIO2 or 3 depending on the specific pin (meaning if mode 7 has
> GPIO0.x then it is GPIO2 and if GPIO1.x then GPIO3)
> 10 - GPIO4 or 5 depending on the specific pin (meaning if mode 7 has
> GPIO0.x then it is GPIO4 and if GPIO1.x then GPIO5)
> 11 - GPIO6 or 7 depending on the specific pin (meaning if mode 7 has
> GPIO0.x then it is GPIO6 and if GPIO1.x then GPIO7)
> Note this field  is irrelevant when Muxmode is not 7.
> 
> Thus, macros need to be generic or it should just open code the constant.

Thank you for the feedback and the detailed J784S4 example. You're
absolutely right that the naming was too AM62L-specific. I've addressed 
this in v2 by using generic value-based naming (PIN_VGPIO_SEL0/1/2/3) 
and adding all four values. The commit message now clarifies that the 
meaning is SoC-specific.

Thanks and Regards,
Akashdeep Kaur
> 
>>   /* Default mux configuration for gpio-ranges to use with pinctrl */
>>   #define PIN_GPIO_RANGE_IOPAD	(PIN_INPUT | 7)
>>   
>