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From: sashiko-bot@kernel.org
To: "Shawn Guo" <shengchao.guo@oss.qualcomm.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes
Date: Tue, 22 Sep 2026 11:22:30 +0000	[thread overview]
Message-ID: <20260922112230.D0FC51F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260922111354.533902-1-shengchao.guo@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] arm64: dts: qcom: missing status disabled for adreno SMMUs causes probe panic
--

commit 8a1e674673fbb99f1a306ac8158a2cd1f163f274
Author: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>

arm64: dts: qcom: nord: Add adreno SMMU nodes

This commit adds the Adreno GPU SMMUs (MMU-500) for both GPU instances to
the base nord dtsi. It also notes that the required clock and power domain
resources are wired up in nord-embedded.dtsi.

Dependencies:
- SMMU binding: https://lore.kernel.org/all/20260902013858.130887-1-shengchao.guo@oss.qualcomm.com/

> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index e0496fd40c308..6c53246d5ad05 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -1518,6 +1518,80 @@ tcsr: syscon@1f60000 {
>  			reg = <0x0 0x01f60000 0x0 0xa0000>;
>  		};
>  
> +		adreno_smmu_0: iommu@3da0000 {
> +			compatible = "qcom,nord-smmu-500",
> +				     "qcom,adreno-smmu",
> +				     "qcom,smmu-500",
> +				     "arm,mmu-500";

[Severity: High]
Should this node be marked with status = "disabled" by default?

Because it lacks clocks and power-domains here in the base nord.dtsi
(which the commit message mentions are added in nord-embedded.dtsi), it is
enabled for all boards including this dtsi. This causes
devm_clk_bulk_get_all() in the arm-smmu driver to return 0 clocks and
succeed. The driver then accesses the SMMU registers without enabling the
required power resources, leading to a kernel panic (synchronous external
abort) during boot.

> +			reg = <0x0 0x03da0000 0x0 0x40000>;
> +			#iommu-cells = <2>;
> +			#global-interrupts = <1>;

[ ... ]

> +		adreno_smmu_1: iommu@98a0000 {
> +			compatible = "qcom,nord-smmu-500",
> +				     "qcom,adreno-smmu",
> +				     "qcom,smmu-500",
> +				     "arm,mmu-500";

[Severity: High]
Similarly, should this node also default to status = "disabled"?

Like the adreno_smmu_0 node, this will cause a synchronous external abort
on probe if the required power resources are missing but the node remains
enabled.

> +			reg = <0x0 0x098a0000 0x0 0x40000>;
> +			#iommu-cells = <2>;
> +			#global-interrupts = <1>;

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922111354.533902-1-shengchao.guo@oss.qualcomm.com?part=1

  reply	other threads:[~2026-09-22 11:22 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22 11:13 [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes Shawn Guo
2026-09-22 11:22 ` sashiko-bot [this message]
2026-09-23  8:18 ` Bartosz Golaszewski
2026-09-23 12:37 ` Konrad Dybcio
2026-09-24  8:34   ` Shawn Guo

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