Re: [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes

[Shawn Guo <shengchao.guo@oss.qualcomm.com>]

On Wed, Sep 23, 2026 at 02:37:18PM +0200, Konrad Dybcio wrote:
> On 9/22/26 1:13 PM, Shawn Guo wrote:
> > From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
> > 
> > Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances.
> > 
> > Wire up the gpucc clock and power domain on both adreno SMMU nodes in
> > nord-embedded.dtsi for embedded Nord variants where gpucc is available.
> > 
> > Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
> > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> > ---
> > Dependencies:
> > - SMMU binding: https://lore.kernel.org/all/20260902013858.130887-1-shengchao.guo@oss.qualcomm.com/
> > 
> >  arch/arm64/boot/dts/qcom/nord.dtsi | 74 ++++++++++++++++++++++++++++++
> >  1 file changed, 74 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> > index e0496fd40c30..6c53246d5ad0 100644
> > --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> > @@ -1518,6 +1518,80 @@ tcsr: syscon@1f60000 {
> >  			reg = <0x0 0x01f60000 0x0 0xa0000>;
> >  		};
> >  
> > +		adreno_smmu_0: iommu@3da0000 {
> > +			compatible = "qcom,nord-smmu-500",
> > +				     "qcom,adreno-smmu",
> > +				     "qcom,smmu-500",
> > +				     "arm,mmu-500";
> > +			reg = <0x0 0x03da0000 0x0 0x40000>;
> > +			#iommu-cells = <2>;
> > +			#global-interrupts = <1>;
> > +			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> 
> 674

I wonder why you are always able to spot such errors. Thank you, Konrad!

Shawn