* [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes
@ 2026-09-22 11:13 Shawn Guo
2026-09-22 11:22 ` sashiko-bot
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Shawn Guo @ 2026-09-22 11:13 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, devicetree, linux-arm-msm, linux-kernel,
Bibek Kumar Patro, Shawn Guo
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances.
Wire up the gpucc clock and power domain on both adreno SMMU nodes in
nord-embedded.dtsi for embedded Nord variants where gpucc is available.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
Dependencies:
- SMMU binding: https://lore.kernel.org/all/20260902013858.130887-1-shengchao.guo@oss.qualcomm.com/
arch/arm64/boot/dts/qcom/nord.dtsi | 74 ++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index e0496fd40c30..6c53246d5ad0 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -1518,6 +1518,80 @@ tcsr: syscon@1f60000 {
reg = <0x0 0x01f60000 0x0 0xa0000>;
};
+ adreno_smmu_0: iommu@3da0000 {
+ compatible = "qcom,nord-smmu-500",
+ "qcom,adreno-smmu",
+ "qcom,smmu-500",
+ "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ };
+
+ adreno_smmu_1: iommu@98a0000 {
+ compatible = "qcom,nord-smmu-500",
+ "qcom,adreno-smmu",
+ "qcom,smmu-500",
+ "arm,mmu-500";
+ reg = <0x0 0x098a0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 932 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 937 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 938 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 939 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 940 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 941 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 942 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 924 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,nord-pdc",
"qcom,pdc";
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes
2026-09-22 11:13 [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes Shawn Guo
@ 2026-09-22 11:22 ` sashiko-bot
2026-09-23 8:18 ` Bartosz Golaszewski
2026-09-23 12:37 ` Konrad Dybcio
2 siblings, 0 replies; 5+ messages in thread
From: sashiko-bot @ 2026-09-22 11:22 UTC (permalink / raw)
To: Shawn Guo; +Cc: robh, conor+dt, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] arm64: dts: qcom: missing status disabled for adreno SMMUs causes probe panic
--
commit 8a1e674673fbb99f1a306ac8158a2cd1f163f274
Author: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
arm64: dts: qcom: nord: Add adreno SMMU nodes
This commit adds the Adreno GPU SMMUs (MMU-500) for both GPU instances to
the base nord dtsi. It also notes that the required clock and power domain
resources are wired up in nord-embedded.dtsi.
Dependencies:
- SMMU binding: https://lore.kernel.org/all/20260902013858.130887-1-shengchao.guo@oss.qualcomm.com/
> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index e0496fd40c308..6c53246d5ad05 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -1518,6 +1518,80 @@ tcsr: syscon@1f60000 {
> reg = <0x0 0x01f60000 0x0 0xa0000>;
> };
>
> + adreno_smmu_0: iommu@3da0000 {
> + compatible = "qcom,nord-smmu-500",
> + "qcom,adreno-smmu",
> + "qcom,smmu-500",
> + "arm,mmu-500";
[Severity: High]
Should this node be marked with status = "disabled" by default?
Because it lacks clocks and power-domains here in the base nord.dtsi
(which the commit message mentions are added in nord-embedded.dtsi), it is
enabled for all boards including this dtsi. This causes
devm_clk_bulk_get_all() in the arm-smmu driver to return 0 clocks and
succeed. The driver then accesses the SMMU registers without enabling the
required power resources, leading to a kernel panic (synchronous external
abort) during boot.
> + reg = <0x0 0x03da0000 0x0 0x40000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
[ ... ]
> + adreno_smmu_1: iommu@98a0000 {
> + compatible = "qcom,nord-smmu-500",
> + "qcom,adreno-smmu",
> + "qcom,smmu-500",
> + "arm,mmu-500";
[Severity: High]
Similarly, should this node also default to status = "disabled"?
Like the adreno_smmu_0 node, this will cause a synchronous external abort
on probe if the required power resources are missing but the node remains
enabled.
> + reg = <0x0 0x098a0000 0x0 0x40000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260922111354.533902-1-shengchao.guo@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes
2026-09-22 11:13 [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes Shawn Guo
2026-09-22 11:22 ` sashiko-bot
@ 2026-09-23 8:18 ` Bartosz Golaszewski
2026-09-23 12:37 ` Konrad Dybcio
2 siblings, 0 replies; 5+ messages in thread
From: Bartosz Golaszewski @ 2026-09-23 8:18 UTC (permalink / raw)
To: Shawn Guo
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, devicetree, linux-arm-msm, linux-kernel,
Bibek Kumar Patro, Bjorn Andersson
On Tue, 22 Sep 2026 13:13:54 +0200, Shawn Guo
<shengchao.guo@oss.qualcomm.com> said:
> From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>
> Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances.
>
> Wire up the gpucc clock and power domain on both adreno SMMU nodes in
> nord-embedded.dtsi for embedded Nord variants where gpucc is available.
>
> Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes
2026-09-22 11:13 [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes Shawn Guo
2026-09-22 11:22 ` sashiko-bot
2026-09-23 8:18 ` Bartosz Golaszewski
@ 2026-09-23 12:37 ` Konrad Dybcio
2026-09-24 8:34 ` Shawn Guo
2 siblings, 1 reply; 5+ messages in thread
From: Konrad Dybcio @ 2026-09-23 12:37 UTC (permalink / raw)
To: Shawn Guo, Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, devicetree, linux-arm-msm, linux-kernel,
Bibek Kumar Patro
On 9/22/26 1:13 PM, Shawn Guo wrote:
> From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>
> Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances.
>
> Wire up the gpucc clock and power domain on both adreno SMMU nodes in
> nord-embedded.dtsi for embedded Nord variants where gpucc is available.
>
> Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---
> Dependencies:
> - SMMU binding: https://lore.kernel.org/all/20260902013858.130887-1-shengchao.guo@oss.qualcomm.com/
>
> arch/arm64/boot/dts/qcom/nord.dtsi | 74 ++++++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index e0496fd40c30..6c53246d5ad0 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -1518,6 +1518,80 @@ tcsr: syscon@1f60000 {
> reg = <0x0 0x01f60000 0x0 0xa0000>;
> };
>
> + adreno_smmu_0: iommu@3da0000 {
> + compatible = "qcom,nord-smmu-500",
> + "qcom,adreno-smmu",
> + "qcom,smmu-500",
> + "arm,mmu-500";
> + reg = <0x0 0x03da0000 0x0 0x40000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
674
[...]
> + adreno_smmu_1: iommu@98a0000 {
> + compatible = "qcom,nord-smmu-500",
> + "qcom,adreno-smmu",
> + "qcom,smmu-500",
> + "arm,mmu-500";
> + reg = <0x0 0x098a0000 0x0 0x40000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 932 IRQ_TYPE_LEVEL_HIGH>,
this one is correct
with that
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes
2026-09-23 12:37 ` Konrad Dybcio
@ 2026-09-24 8:34 ` Shawn Guo
0 siblings, 0 replies; 5+ messages in thread
From: Shawn Guo @ 2026-09-24 8:34 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bartosz Golaszewski, devicetree, linux-arm-msm,
linux-kernel, Bibek Kumar Patro
On Wed, Sep 23, 2026 at 02:37:18PM +0200, Konrad Dybcio wrote:
> On 9/22/26 1:13 PM, Shawn Guo wrote:
> > From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
> >
> > Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances.
> >
> > Wire up the gpucc clock and power domain on both adreno SMMU nodes in
> > nord-embedded.dtsi for embedded Nord variants where gpucc is available.
> >
> > Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
> > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> > ---
> > Dependencies:
> > - SMMU binding: https://lore.kernel.org/all/20260902013858.130887-1-shengchao.guo@oss.qualcomm.com/
> >
> > arch/arm64/boot/dts/qcom/nord.dtsi | 74 ++++++++++++++++++++++++++++++
> > 1 file changed, 74 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> > index e0496fd40c30..6c53246d5ad0 100644
> > --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> > @@ -1518,6 +1518,80 @@ tcsr: syscon@1f60000 {
> > reg = <0x0 0x01f60000 0x0 0xa0000>;
> > };
> >
> > + adreno_smmu_0: iommu@3da0000 {
> > + compatible = "qcom,nord-smmu-500",
> > + "qcom,adreno-smmu",
> > + "qcom,smmu-500",
> > + "arm,mmu-500";
> > + reg = <0x0 0x03da0000 0x0 0x40000>;
> > + #iommu-cells = <2>;
> > + #global-interrupts = <1>;
> > + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
>
> 674
I wonder why you are always able to spot such errors. Thank you, Konrad!
Shawn
^ permalink raw reply [flat|nested] 5+ messages in thread
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2026-09-22 11:13 [PATCH] arm64: dts: qcom: nord: Add adreno SMMU nodes Shawn Guo
2026-09-22 11:22 ` sashiko-bot
2026-09-23 8:18 ` Bartosz Golaszewski
2026-09-23 12:37 ` Konrad Dybcio
2026-09-24 8:34 ` Shawn Guo
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