Re: [PATCH 2/2] spi: mt65xx: support wider tick delay field on IPM v59

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] spi: mt65xx: unused macro SPI_CMD_IPM_GET_TICKDLY_OFFSET
--

commit 7585a8851ec5ccd32f23459c09b756cd0dc48ccd
Author: Tim Kuo <Tim.Kuo@mediatek.com>
spi: mt65xx: support wider tick delay field on IPM v59

This commit adds support for the wider 7-bit tick delay field in IPM v59 by
introducing a per-SoC mask. It updates the driver to use field_prep()
instead of hardcoded shifts and masks.

> diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
> index b845a599f7c6c..27ed9be1b1213 100644
> --- a/drivers/spi/spi-mt65xx.c
> +++ b/drivers/spi/spi-mt65xx.c

[ ... ]

> @@ -81,6 +82,7 @@
>  #define SPI_CMD_IPM_GET_TICKDLY_OFFSET	22

[Severity: Low]
Should SPI_CMD_IPM_GET_TICKDLY_OFFSET be removed here? Since this patch
migrates the tick delay handling to field_prep() below, this macro appears
to be left as unused dead code.

>  #define SPI_CMD_IPM_GET_TICKDLY_MASK	GENMASK(24, 22)
> +#define SPI_CMD_IPM_V59_GET_TICKDLY_MASK	GENMASK(28, 22)
>  
>  #define PIN_MODE_CFG(x)	((x) / 2)

[ ... ]

> @@ -443,10 +460,10 @@ static int mtk_spi_hw_init(struct spi_controller *host,
>  	/* tick delay */
>  	if (mdata->dev_comp->enhance_timing) {
>  		if (mdata->dev_comp->ipm_design) {
> +			mask = mdata->dev_comp->tick_dly_mask;
>  			reg_val = readl(mdata->base + SPI_CMD_REG);
> -			reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
> -			reg_val |= ((chip_config->tick_delay & 0x7)
> -				    << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
> +			reg_val &= ~mask;
> +			reg_val |= field_prep(mask, chip_config->tick_delay);
>  			writel(reg_val, mdata->base + SPI_CMD_REG);
>  		} else {
>  			reg_val = readl(mdata->base + SPI_CFG1_REG);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260924031211.2199921-1-Tim.Kuo@mediatek.com?part=2