[PATCH v2 0/4] arm64: dts: renesas: Enable ISP and IVC on RZ/V2H EVK

[PATCH v2 0/4] arm64: dts: renesas: Enable ISP and IVC on RZ/V2H EVK

[Linus Walleij]

Describe the optional ISP DMA line-tick and IVC frame-start/frame-stop
interrupts. Add the RZ/V2H(P) IVC and Arm Mali-C55 ISP nodes, connect their
video endpoints, and enable both blocks on the RZ/V2H EVK.

After these patches, and enabling the right Linux drivers, we get
this in the console:
mali-c55 16080000.isp: Detected Mali-C55 ISP 9000043.31032022.0

This was done in order to enable booting mainline with mainline
device trees.

Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
Changes in v2:
- Add separate IVC and ISP binding patches describing the optional IVC
  frame-start/frame-stop completion and ISP DMA line-tick IRQs.
  Show all six IRQs in the examples using consecutive mock numbers.
- Add the IVC frame-start/stop and ISP DMA line-tick interrupt lines
  using the confirmed SPI assignments, addressing Geert's IRQ review.
- Correct the IVC and ISP register sizes to 64 KiB and 512 KiB,
  respectively, as requested by Geert. GPV_VIDEO0 is a separate bus
  interconnect region.
- Compact the clock and reset properties and remove blank lines between
  properties, following Geert's review.
- Link to v1: https://patch.msgid.link/20260922-mali-c55-renesas-dts-v1-0-cd63cdb51033@kernel.org

---
Daniel Scally (2):
      arm64: dts: renesas: r9a09g057: Add IVC and ISP nodes
      arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add ISP and IVC nodes

Linus Walleij (2):
      dt-bindings: media: renesas,r9a09g057-ivc: Describe additional interrupts
      dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts

 .../devicetree/bindings/media/arm,mali-c55.yaml    | 11 ++++--
 .../bindings/media/renesas,r9a09g057-ivc.yaml      | 11 ++++--
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi         | 41 ++++++++++++++++++++++
 .../boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts    |  8 +++++
 4 files changed, 67 insertions(+), 4 deletions(-)
---
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
change-id: 20260922-mali-c55-renesas-dts-74d4727f59e5

Best regards,
--  
Linus Walleij <linusw@kernel.org>

[PATCH v2 1/4] dt-bindings: media: renesas,r9a09g057-ivc: Describe additional interrupts

[Linus Walleij]

The RZ/V2H IVC provides input frame-start and frame-stop completion
interrupts alongside its input frame-end interrupt.

Describe these optional interrupts, keeping frame end first and requiring
only that entry to preserve support for existing device trees. Extend the
example to show all three interrupts using mock interrupt numbers.

Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 .../devicetree/bindings/media/renesas,r9a09g057-ivc.yaml      | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
index c09cbd8c9e35..3eeb1a92c9cf 100644
--- a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
@@ -21,7 +21,11 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: Image input frame-end interrupt
+      - description: Image input frame-start interrupt
+      - description: Frame-stop processing completion interrupt
 
   clocks:
     items:
@@ -92,7 +96,10 @@ examples:
                <&cpg 0xd3>;
       reset-names = "reg", "axi", "isp";
 
-      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
+      /* Example interrupt numbers. */
+      interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 
       port {
         ivc_out: endpoint {

-- 
2.55.0

Re: [PATCH v2 1/4] dt-bindings: media: renesas,r9a09g057-ivc: Describe additional interrupts

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 75 bytes --]

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

[-- Attachment #2: signature.asc --]
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[PATCH v2 2/4] dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts

[Linus Walleij]

Mali-C55 exposes separate full-resolution and UV DMA writer line-tick
interrupts in addition to its combined core interrupt.

Describe these optional interrupts, keeping the core interrupt first and
requiring only that entry to preserve support for existing device trees.
Extend the example to show all three interrupts using mock interrupt
numbers.

Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 Documentation/devicetree/bindings/media/arm,mali-c55.yaml | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
index fc4fcd19922a..8fcc46660b75 100644
--- a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
+++ b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
@@ -18,7 +18,11 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: Combined ISP core interrupt
+      - description: Full-resolution DMA writer line-tick interrupt
+      - description: Full-resolution UV DMA writer line-tick interrupt
 
   clocks:
     items:
@@ -75,7 +79,10 @@ examples:
       clock-names = "vclk", "aclk", "hclk";
       resets = <&resets 0>, <&resets 1>, <&resets 2>;
       reset-names = "vresetn", "aresetn", "hresetn";
-      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
+      /* Example interrupt numbers. */
+      interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                   <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
 
       port {
         isp_in: endpoint {

-- 
2.55.0

[PATCH v2 3/4] arm64: dts: renesas: r9a09g057: Add IVC and ISP nodes

[Linus Walleij]

From: Daniel Scally <dan.scally@ideasonboard.com>

Add the Input Video Control Block and Arm Mali-C55 ISP to the device
tree file for the RZ/V2H(P) SoC.

[Rebase onto v7.3-rc1, place the nodes in address order, add the
 missing interrupt and sort them. - Linus Walleij]

Assisted-by: LLM
Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 ++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 639693d464a7..f04180c35866 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -1839,6 +1839,47 @@ queue3 {
 			};
 		};
 
+		ivc: isp-input@16040000 {
+			compatible = "renesas,r9a09g057-ivc";
+			reg = <0 0x16040000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0xe3>, <&cpg CPG_MOD 0xe4>,
+				 <&cpg CPG_MOD 0xe5>;
+			clock-names = "reg", "axi", "isp";
+			interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&cpg>;
+			resets = <&cpg 0xd4>, <&cpg 0xd1>, <&cpg 0xd3>;
+			reset-names = "reg", "axi", "isp";
+			status = "disabled";
+
+			port {
+				ivc_out: endpoint {
+					remote-endpoint = <&isp_in>;
+				};
+			};
+		};
+
+		isp: isp@16080000 {
+			compatible = "arm,mali-c55";
+			reg = <0 0x16080000 0 0x80000>;
+			clocks = <&cpg CPG_MOD 0xe2>, <&cpg CPG_MOD 0xe4>,
+				 <&cpg CPG_MOD 0xe5>;
+			clock-names = "vclk", "aclk", "hclk";
+			interrupts = <GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 865 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 866 IRQ_TYPE_EDGE_RISING>;
+			resets = <&cpg 0xd2>, <&cpg 0xd1>, <&cpg 0xd3>;
+			reset-names = "vresetn", "aresetn", "hresetn";
+			status = "disabled";
+
+			port {
+				isp_in: endpoint {
+					remote-endpoint = <&ivc_out>;
+				};
+			};
+		};
+
 		dsi: dsi@16430000 {
 			compatible = "renesas,r9a09g057-mipi-dsi";
 			reg = <0 0x16430000 0 0x20000>;

-- 
2.55.0

Re: [PATCH v2 3/4] arm64: dts: renesas: r9a09g057: Add IVC and ISP nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] arm64: dts: renesas: swapped vclk and hclk clock/reset mapping in mali-c55 ISP node
- [High] arm64: dts: renesas: missing power-domains property in mali-c55 ISP node
--

commit f1f95e2c7f1fc7d73c0351518cd19bf0ac773a31
Author: Daniel Scally <dan.scally@ideasonboard.com>

arm64: dts: renesas: r9a09g057: Add IVC and ISP nodes

Add the Input Video Control Block and Arm Mali-C55 ISP to the device
tree file for the RZ/V2H(P) SoC.

> diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> index 639693d464a77..f04180c35866a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
[ ... ]
> +		isp: isp@16080000 {
> +			compatible = "arm,mali-c55";
> +			reg = <0 0x16080000 0 0x80000>;

[Severity: High]
Does this node need a power-domains property?

The isp node appears to omit power-domains = <&cpg>;. On Renesas SoCs, this
property attaches the device to the Clock Pulse Generator (CPG) generic power
domain, which is responsible for clearing the BUS_MSTOP bits during
pm_runtime_resume. 

Without it, pm_runtime_resume_and_get() in the driver might not trigger the
genpd domain hooks to clear MSTOP, which could cause register accesses to hang
the bus or leave the hardware inaccessible.

> +			clocks = <&cpg CPG_MOD 0xe2>, <&cpg CPG_MOD 0xe4>,
> +				 <&cpg CPG_MOD 0xe5>;
> +			clock-names = "vclk", "aclk", "hclk";

[Severity: High]
Are the vclk and hclk clock mappings swapped here?

The arm,mali-c55 driver expects vclk to be the video clock and hclk to be the
AHB register clock. Here, vclk is assigned to CPG_MOD 0xe2 (isp_0_reg_aclk)
and hclk is assigned to CPG_MOD 0xe5 (isp_0_isp_sclk). 

This appears to reverse their roles and could cause the driver to configure
the wrong clock frequencies.

> +			interrupts = <GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 865 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 866 IRQ_TYPE_EDGE_RISING>;
> +			resets = <&cpg 0xd2>, <&cpg 0xd1>, <&cpg 0xd3>;
> +			reset-names = "vresetn", "aresetn", "hresetn";

[Severity: High]
Are the vresetn and hresetn reset mappings also swapped?

Similar to the clocks, this maps the register reset (0xd2 ISP_0_REG_ARESETN)
to vresetn and the ISP video reset (0xd3) to hresetn. This could lead to
reset domains being incorrectly managed, resulting in hardware initialization
failures.

> +			status = "disabled";
> +
> +			port {
> +				isp_in: endpoint {
> +					remote-endpoint = <&ivc_out>;
> +				};
> +			};
> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260925-mali-c55-renesas-dts-v2-0-69f728a474a2@kernel.org?part=3

[PATCH v2 4/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add ISP and IVC nodes

[Linus Walleij]

From: Daniel Scally <dan.scally@ideasonboard.com>

Add nodes to devicetree enabling the ISP and IVC that are found on
the RZ/V2H(P) SoC.

[Rebase onto v7.3-rc1 and sort the board overrides by label.
 - Linus Walleij]

Assisted-by: LLM
Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index 637fc92dcc26..74b75be599ae 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -305,6 +305,14 @@ versa3: clock-generator@69 {
 	};
 };
 
+&isp {
+	status = "okay";
+};
+
+&ivc {
+	status = "okay";
+};
+
 &mdio0 {
 	phy0: ethernet-phy@0 {
 		compatible = "ethernet-phy-id0022.1640";

-- 
2.55.0

Re: [PATCH v2 4/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add ISP and IVC nodes

[Linus Walleij]

On Fri, Sep 25, 2026 at 2:56 PM Linus Walleij <linusw@kernel.org> wrote:
On Fri, Sep 25, 2026 at 11:30 AM Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Tue, Sep 22, 2026 at 03:34:01PM +0200, Linus Walleij wrote:

> > From: Daniel Scally <dan.scally@ideasonboard.com>
> >
> > Add nodes to devicetree enabling the ISP and IVC that are found on
> > the RZ/V2H(P) SoC.
> >
> > [Rebase onto v7.3-rc1 and sort the board overrides by label.
> >  - Linus Walleij]
>
> Geert commented on the commit message in the original series, that
> comment seems to have been ignored.

Hm I managed to send out the v2 series before re-checking the mailing
list for more comments, sorry :(

Maybe Geert can augment when applying, else I can send a v3.

> > Assisted-by: LLM
>
> This gives the impression that Dan's original patch was LLM-assisted,
> which wasn't the case.

This can also be dropped when applying.

I am kind of over-reporting LLM use because I absolutely don't want
people to get wrong information here, and the tag is a kind of
all-encompassing.

What I actually use it for is pretty silly: I use an LLM to query the
datasheets for information, the rest is mostly done interactively,
but well, it was used, like I use the evince PDF reader but that
we don't have an Assisted-by tag for.

Yours,
Linus Walleij