[PATCH v3 0/8] Add Renesas RZ/G3L TSU support

[PATCH v3 0/8] Add Renesas RZ/G3L TSU support

[Biju Das]

The Thermal sensor unit (a.k.a TSU) IP found on the RZ/G3L SoC is similar
to the RZ/G3S, but it has different calibration constants. Moreover, the
TSU is connected to A/D converter of TSU (a.k.a ADC1) on the RZ/G3L,
whereas it is connected to ADC0 on the RZ/G3S.

Compared to ADC0, there are no A/D conversion result registers(ADCR0 to
ADCR7) on the RZ/G3L, and the INTEN bits in the A/D converter interrupt
control register(a.k.a ADINT)  are also different.

This patch series aims to add support for TSU along with ADC1.

Merge strategy:
  * patch #1 clk subsystem
  * patch #2-#4 thermal subsystem
  * patch #5-#7 iio subsystem
  * patch #8 SoC subsystem

v2->v3:
 * Collected tags
 * Dropped required property '#io-channel-cells' from bindings.
 * Renamed num_channels to max_channels in struct rzg2l_adc_hw_params
v1->v2:
 * Merged TSU and ADC1 series together.
 * Moved the clk patch.

Biju Das (8):
  clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
  dt-bindings: thermal: r9a08g045-tsu: Document RZ/G3L TSU
  thermal/drivers/renesas/rzg3s: Convert calibration defaults to per-SoC
    match data
  thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support
  dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
  iio: adc: rzg2l_adc: Rename num_channels to max_channels
  iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU
  arm64: dts: renesas: r9a08g046: Enable TSU

 .../bindings/iio/adc/renesas,rzg2l-adc.yaml   | 17 ++++-
 .../thermal/renesas,r9a08g045-tsu.yaml        |  4 +-
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi    | 66 +++++++++++++++++++
 drivers/clk/renesas/r9a08g046-cpg.c           | 10 +++
 drivers/iio/adc/rzg2l_adc.c                   | 29 +++++---
 drivers/thermal/renesas/rzg3s_thermal.c       | 38 ++++++++---
 6 files changed, 143 insertions(+), 21 deletions(-)

-- 
2.43.0

[PATCH v3 2/8] dt-bindings: thermal: r9a08g045-tsu: Document RZ/G3L TSU

[Biju Das]

Add the renesas,r9a08g046-tsu compatible string for the RZ/G3L Thermal
Sensor Unit (a.k.a TSU), which is similar to the RZ/G3S TSU but uses
different calibration constants. TSU is connected to a dedicated ADC IP
(a.k.a ADC1) on RZ/G3L.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * Collected tags
v1->v2:
 * Updated commit description.
---
 .../devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml    | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
index 573e2b9d3752..20fc1a8000e3 100644
--- a/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
+++ b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
@@ -17,7 +17,9 @@ $ref: thermal-sensor.yaml#
 
 properties:
   compatible:
-    const: renesas,r9a08g045-tsu
+    enum:
+      - renesas,r9a08g045-tsu
+      - renesas,r9a08g046-tsu
 
   reg:
     maxItems: 1
-- 
2.43.0

[PATCH v3 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Biju Das]

Add the renesas,r9a08g046-adc1 compatible string for the ADC1
instance on RZ/G3L, which is dedicated to the on-chip TSU (thermal
sensor unit). Unlike the other ADC instances, this one only exposes
a single channel (channel@8), so restrict the allowed channel nodes
accordingly.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * Dropped required property '#io-channel-cells'.
v1->v2:
 * No Change.
---
 .../bindings/iio/adc/renesas,rzg2l-adc.yaml     | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
index 40341d541726..f08f5439d127 100644
--- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
@@ -25,7 +25,9 @@ properties:
               - renesas,r9a07g054-adc   # RZ/V2L
           - const: renesas,rzg2l-adc
       - items:
-          - const: renesas,r9a08g045-adc  # RZ/G3S
+          - enum:
+              - renesas,r9a08g045-adc   # RZ/G3S
+              - renesas,r9a08g046-adc1  # RZ/G3L ADC for TSU
 
   reg:
     maxItems: 1
@@ -121,6 +123,19 @@ allOf:
             reg:
               maximum: 7
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a08g046-adc1
+    then:
+      patternProperties:
+        "^channel@[0-7]$": false
+        "^channel@[8]$":
+          properties:
+            reg:
+              const: 8
+
 additionalProperties: false
 
 examples:
-- 
2.43.0

[PATCH v3 6/8] iio: adc: rzg2l_adc: Rename num_channels to max_channels

[Biju Das]

Rename the num_channels member of struct rzg2l_adc_hw_params to
max_channels, as it represents the maximum channel supported by
the ADC hardware rather than a count of channels currently in use.

No functional change intended.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3:
 * New patch.
---
 drivers/iio/adc/rzg2l_adc.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index 408fbf8c29cc..aaf7e2ceff8a 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -62,7 +62,7 @@
  * @adsmp_mask: ADC sampling period mask (see ADM3 register)
  * @adint_inten_mask: conversion end interrupt mask (see ADINT register)
  * @default_adcmp: default ADC cmp (see ADM3 register)
- * @num_channels: number of supported channels
+ * @max_channels: the maximum channel for the ADC
  * @adivc: specifies if ADVIC register is available
  */
 struct rzg2l_adc_hw_params {
@@ -70,7 +70,7 @@ struct rzg2l_adc_hw_params {
 	u16 adsmp_mask;
 	u16 adint_inten_mask;
 	u8 default_adcmp;
-	u8 num_channels;
+	u8 max_channels;
 	bool adivc;
 };
 
@@ -196,7 +196,7 @@ static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
 
 	/* Select analog input channel subjected to conversion. */
 	reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));
-	reg &= ~GENMASK(hw_params->num_channels - 1, 0);
+	reg &= ~GENMASK(hw_params->max_channels - 1, 0);
 	reg |= BIT(ch);
 	rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
 
@@ -307,11 +307,11 @@ static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id)
 		return IRQ_HANDLED;
 	}
 
-	intst = reg & GENMASK(hw_params->num_channels - 1, 0);
+	intst = reg & GENMASK(hw_params->max_channels - 1, 0);
 	if (!intst)
 		return IRQ_NONE;
 
-	for_each_set_bit(ch, &intst, hw_params->num_channels)
+	for_each_set_bit(ch, &intst, hw_params->max_channels)
 		adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
 
 	/* clear the channel interrupt */
@@ -341,12 +341,12 @@ static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l
 
 	num_channels = devm_iio_adc_device_alloc_chaninfo_se(&pdev->dev,
 						&rzg2l_adc_chan_template,
-						hw_params->num_channels - 1,
+						hw_params->max_channels - 1,
 						&chan_array);
 	if (num_channels < 0)
 		return num_channels;
 
-	if (num_channels > hw_params->num_channels)
+	if (num_channels > hw_params->max_channels)
 		return dev_err_probe(&pdev->dev, -EINVAL,
 				     "num of channel children out of range\n");
 
@@ -429,7 +429,7 @@ static int rzg2l_adc_probe(struct platform_device *pdev)
 	adc = iio_priv(indio_dev);
 
 	adc->hw_params = device_get_match_data(dev);
-	if (!adc->hw_params || adc->hw_params->num_channels > RZG2L_ADC_MAX_CHANNELS)
+	if (!adc->hw_params || adc->hw_params->max_channels > RZG2L_ADC_MAX_CHANNELS)
 		return -EINVAL;
 
 	ret = rzg2l_adc_parse_properties(pdev, adc);
@@ -484,7 +484,7 @@ static int rzg2l_adc_probe(struct platform_device *pdev)
 }
 
 static const struct rzg2l_adc_hw_params rzg2l_hw_params = {
-	.num_channels = 8,
+	.max_channels = 8,
 	.default_adcmp = 0xe,
 	.default_adsmp = { 0x578 },
 	.adsmp_mask = GENMASK(15, 0),
@@ -493,7 +493,7 @@ static const struct rzg2l_adc_hw_params rzg2l_hw_params = {
 };
 
 static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
-	.num_channels = 9,
+	.max_channels = 9,
 	.default_adcmp = 0x1d,
 	.default_adsmp = { 0x7f, 0xff },
 	.adsmp_mask = GENMASK(7, 0),
-- 
2.43.0

[PATCH v3 7/8] iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU

[Biju Das]

Add renesas,r9a08g046-adc1 compatible string and its hardware
parameters for the ADC1 IP on RZ/G3L, which is dedicated to
the on-chip TSU (thermal sensor unit).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No Change.
v1->v2:
 * No Change.
---
 drivers/iio/adc/rzg2l_adc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index aaf7e2ceff8a..c892e355b739 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -500,8 +500,17 @@ static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
 	.adint_inten_mask = GENMASK(11, 0),
 };
 
+static const struct rzg2l_adc_hw_params rzg3l_adc1_hw_params = {
+	.max_channels = 9,
+	.default_adcmp = 0x1d,
+	.default_adsmp = { 0x7f, 0xff },
+	.adsmp_mask = GENMASK(7, 0),
+	.adint_inten_mask = BIT(8),
+};
+
 static const struct of_device_id rzg2l_adc_match[] = {
 	{ .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params },
+	{ .compatible = "renesas,r9a08g046-adc1", .data = &rzg3l_adc1_hw_params },
 	{ .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
 	{ }
 };
-- 
2.43.0

[PATCH v3 8/8] arm64: dts: renesas: r9a08g046: Enable TSU

[Biju Das]

Add #cooling-cells to the CPU nodes, and describe the ADC1 (used
exclusively by the TSU) and TSU nodes along with a CPU thermal zone
using passive and critical trip points, with CPU frequency cooling
maps for thermal mitigation.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No Change.
v1->v2:
 * No Change.
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 66 ++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 53e68b1c3258..29ce1ab2a57f 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -179,6 +179,7 @@ cpu0: cpu@0 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC0>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -189,6 +190,7 @@ cpu1: cpu@100 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC1>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -199,6 +201,7 @@ cpu2: cpu@200 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC2>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -209,6 +212,7 @@ cpu3: cpu@300 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G046_CLK_IC3>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -374,6 +378,37 @@ scif5: serial@1004e000 {
 			status = "disabled";
 		};
 
+		adc1: adc@108c0000 {
+			compatible = "renesas,r9a08g046-adc1";
+			reg = <0 0x108c0000 0 0x10000>;
+			interrupts = <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD R9A08G046_ADC1_ADCLK>,
+				 <&cpg CPG_MOD R9A08G046_ADC1_PCLK>;
+			clock-names = "adclk", "pclk";
+			resets = <&cpg R9A08G046_ADC1_PRESETN>,
+				 <&cpg R9A08G046_ADC1_ADRST_N>;
+			reset-names = "presetn", "adrst-n";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			channel@8 {
+				reg = <8>;
+			};
+		};
+
+		tsu: thermal@108d0000 {
+			compatible = "renesas,r9a08g046-tsu";
+			reg = <0 0x108d0000 0 0x10000>;
+			clocks = <&cpg CPG_MOD R9A08G046_TSU_PCLK>;
+			resets = <&cpg R9A08G046_TSU_PRESETN>;
+			power-domains = <&cpg>;
+			#thermal-sensor-cells = <0>;
+			io-channels = <&adc1 0>;
+			io-channel-names = "tsu";
+		};
+
 		i2c0: i2c@100ae000 {
 			compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
 			reg = <0 0x100ae000 0 0x400>;
@@ -1570,6 +1605,37 @@ stmmac_axi_setup: stmmac-axi-config {
 		snps,blen = <16 8 4 0 0 0 0>;
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&tsu>;
+
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
+							 <&cpu2 0 3>, <&cpu3 0 3>;
+					contribution = <1024>;
+				};
+			};
+
+			trips {
+				sensor_crit: sensor-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+
+				target: trip-point {
+					temperature = <95000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-- 
2.43.0

Re: [PATCH v3 7/8] iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] iio: adc: rzg2l_adc: missing channel validation for RZ/G3L ADC1 causes state leaks and potential crashes
--

commit 6a30a731629fb5bab54f976d5c01c9fd5c2d8432
Author: Biju Das <biju.das.jz@bp.renesas.com>

iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU

Add renesas,r9a08g046-adc1 compatible string and its hardware
parameters for the ADC1 IP on RZ/G3L, which is dedicated to
the on-chip TSU (thermal sensor unit).

> diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
> index aaf7e2ceff8ab..c892e355b7398 100644
> --- a/drivers/iio/adc/rzg2l_adc.c
> +++ b/drivers/iio/adc/rzg2l_adc.c
> @@ -500,8 +500,17 @@ static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
>  	.adint_inten_mask = GENMASK(11, 0),
>  };
>  
> +static const struct rzg2l_adc_hw_params rzg3l_adc1_hw_params = {
> +	.max_channels = 9,
> +	.default_adcmp = 0x1d,
> +	.default_adsmp = { 0x7f, 0xff },
> +	.adsmp_mask = GENMASK(7, 0),
> +	.adint_inten_mask = BIT(8),

[Severity: High]
Does this mask inadvertently leak the interrupt enable state for channels 0-7 if
they are incorrectly configured in the device tree?

With max_channels set to 9, rzg2l_adc_probe() accepts channels 0 through 8 from
the device tree. If an unsupported channel (e.g., 0) is probed and accessed via
sysfs, rzg2l_adc_conversion_setup() sets BIT(0) in the interrupt enable
register.

However, because adint_inten_mask is restricted to BIT(8), the driver's timeout
and cleanup paths will fail to clear BIT(0):

drivers/iio/adc/rzg2l_adc.c:rzg2l_adc_conversion() {
    ...
		rzg2l_adc_writel(adc, RZG2L_ADINT,
				 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~hw_params->adint_inten_mask);
    ...
}

Additionally, reading an unsupported channel data register in the ISR could
cause a synchronous external abort:

drivers/iio/adc/rzg2l_adc.c:rzg2l_adc_isr() {
    ...
	for_each_set_bit(ch, &intst, hw_params->max_channels)
		adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
    ...
}

> +};
> +
>  static const struct of_device_id rzg2l_adc_match[] = {
>  	{ .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params },
> +	{ .compatible = "renesas,r9a08g046-adc1", .data = &rzg3l_adc1_hw_params },
>  	{ .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
>  	{ }
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922042707.116378-1-biju.das.jz@bp.renesas.com?part=7

Re: [PATCH v3 8/8] arm64: dts: renesas: r9a08g046: Enable TSU

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: io-channels specifier uses software array index instead of hardware channel
--

commit e43366f80cfffd32ae026b33a6ad6c170b125e78
Author: Biju Das <biju.das.jz@bp.renesas.com>

arm64: dts: renesas: r9a08g046: Enable TSU

This commit adds cooling cells to CPU nodes and describes the ADC1 and
TSU nodes to establish a CPU thermal zone. It configures passive and
critical trip points along with cooling maps for thermal mitigation.

> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index c63a857f0e5b0..a2f6718c0043a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
[ ... ]
> @@ -270,6 +274,37 @@ scif5: serial@1004e000 {
>  			status = "disabled";
>  		};
>  
> +		adc1: adc@108c0000 {
> +			compatible = "renesas,r9a08g046-adc1";
[ ... ]
> +			#io-channel-cells = <1>;
> +
> +			channel@8 {
> +				reg = <8>;
> +			};
> +		};
> +
> +		tsu: thermal@108d0000 {
> +			compatible = "renesas,r9a08g046-tsu";
> +			reg = <0 0x108d0000 0 0x10000>;
> +			clocks = <&cpg CPG_MOD R9A08G046_TSU_PCLK>;
> +			resets = <&cpg R9A08G046_TSU_PRESETN>;
> +			power-domains = <&cpg>;
> +			#thermal-sensor-cells = <0>;
> +			io-channels = <&adc1 0>;

[Severity: Medium]
Does this io-channels property correctly map to the hardware channel, or does
it bake a Linux-specific software index into the device tree?

In the tsu node of arch/arm64/boot/dts/renesas/r9a08g046.dtsi, the ADC node
explicitly defines channel 8 (channel@8), but this property uses index 0.
This violates DT principles by encoding the driver's internal software array
index rather than the physical hardware channel ID.

Because the rzg2l_adc driver currently lacks a fwnode_xlate callback, it
falls back to __fwnode_iio_simple_xlate(). The driver populates
indio_dev->channels with the single active DT channel, so
indio_dev->num_channels is 1. If the DT correctly specified <&adc1 8>, the
fallback translator would fail since 8 >= 1.

Does bypassing this failure by using <&adc1 0> introduce a brittle dependency
on the subnode order that will silently break the TSU if other channels are
ever added?

> +			io-channel-names = "tsu";
> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922042707.116378-1-biju.das.jz@bp.renesas.com?part=8

RE: [PATCH v3 8/8] arm64: dts: renesas: r9a08g046: Enable TSU

[Biju Das]

Hi Sashiko,

> -----Original Message-----
> From: sashiko-bot@kernel.org <sashiko-bot@kernel.org>
> Sent: 22 September 2026 05:44
> Subject: Re: [PATCH v3 8/8] arm64: dts: renesas: r9a08g046: Enable TSU
> 
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] arm64: dts: io-channels specifier uses software array index instead of hardware channel
> --
> 
> commit e43366f80cfffd32ae026b33a6ad6c170b125e78
> Author: Biju Das <biju.das.jz@bp.renesas.com>
> 
> arm64: dts: renesas: r9a08g046: Enable TSU
> 
> This commit adds cooling cells to CPU nodes and describes the ADC1 and TSU nodes to establish a CPU
> thermal zone. It configures passive and critical trip points along with cooling maps for thermal
> mitigation.
> 
> > diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > index c63a857f0e5b0..a2f6718c0043a 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> [ ... ]
> > @@ -270,6 +274,37 @@ scif5: serial@1004e000 {
> >  			status = "disabled";
> >  		};
> >
> > +		adc1: adc@108c0000 {
> > +			compatible = "renesas,r9a08g046-adc1";
> [ ... ]
> > +			#io-channel-cells = <1>;
> > +
> > +			channel@8 {
> > +				reg = <8>;
> > +			};
> > +		};
> > +
> > +		tsu: thermal@108d0000 {
> > +			compatible = "renesas,r9a08g046-tsu";
> > +			reg = <0 0x108d0000 0 0x10000>;
> > +			clocks = <&cpg CPG_MOD R9A08G046_TSU_PCLK>;
> > +			resets = <&cpg R9A08G046_TSU_PRESETN>;
> > +			power-domains = <&cpg>;
> > +			#thermal-sensor-cells = <0>;
> > +			io-channels = <&adc1 0>;
> 
> [Severity: Medium]
> Does this io-channels property correctly map to the hardware channel, or does it bake a Linux-specific
> software index into the device tree?

Yes, Please check the code[1] which maps Linux-specific software index 0
to hardware channel 8.

https://elixir.bootlin.com/linux/v7.3-rc3/source/drivers/iio/adc/rzg2l_adc.c#L354

Cheers,
Biju

RE: [PATCH v3 7/8] iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU

[Biju Das]

Hi Sashiko,

> -----Original Message-----
> From: sashiko-bot@kernel.org <sashiko-bot@kernel.org>
> Sent: 22 September 2026 05:42
> Subject: Re: [PATCH v3 7/8] iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU
> 
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] iio: adc: rzg2l_adc: missing channel validation for RZ/G3L ADC1 causes state leaks and potential
> crashes
> --
> 
> commit 6a30a731629fb5bab54f976d5c01c9fd5c2d8432
> Author: Biju Das <biju.das.jz@bp.renesas.com>
> 
> iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU
> 
> Add renesas,r9a08g046-adc1 compatible string and its hardware parameters for the ADC1 IP on RZ/G3L, which
> is dedicated to the on-chip TSU (thermal sensor unit).
> 
> > diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
> > index aaf7e2ceff8ab..c892e355b7398 100644
> > --- a/drivers/iio/adc/rzg2l_adc.c
> > +++ b/drivers/iio/adc/rzg2l_adc.c
> > @@ -500,8 +500,17 @@ static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
> >  	.adint_inten_mask = GENMASK(11, 0),
> >  };
> >
> > +static const struct rzg2l_adc_hw_params rzg3l_adc1_hw_params = {
> > +	.max_channels = 9,
> > +	.default_adcmp = 0x1d,
> > +	.default_adsmp = { 0x7f, 0xff },
> > +	.adsmp_mask = GENMASK(7, 0),
> > +	.adint_inten_mask = BIT(8),
> 
> [Severity: High]
> Does this mask inadvertently leak the interrupt enable state for channels 0-7 if they are incorrectly
> configured in the device tree?

Binding checks captures such incorrect configuration.

> 
> With max_channels set to 9, rzg2l_adc_probe() accepts channels 0 through 8 from the device tree. If an
> unsupported channel (e.g., 0) is probed and accessed via sysfs, rzg2l_adc_conversion_setup() sets BIT(0)
> in the interrupt enable register.

rzg2l_adc_parse_properties() maps array 0 to hardware channel 8. Since .adint_inten_mask = BIT(8)
only hardware channel 8 interrupt occurs in the system.

> 
> However, because adint_inten_mask is restricted to BIT(8), the driver's timeout and cleanup paths will
> fail to clear BIT(0):

We haven't set BIT(0). So there is no way we get interrupt on channel 0.
Also, I don't see a time out as it configures channel 8 only. See the logs.

[   86.336715] ##########rzg2l_adc_conversion_setup 8

> 
> drivers/iio/adc/rzg2l_adc.c:D() {
>     ...
> 		rzg2l_adc_writel(adc, RZG2L_ADINT,
> 				 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~hw_params->adint_inten_mask);

This clearly 
>     ...
> }
> 
> Additionally, reading an unsupported channel data register in the ISR could cause a synchronous external
> abort:

First of all, since BI(8) is configured, we get only interrupts from channel 8.
There is no spurious IRQ's on the system to generate interrupts on other channels.

On a worst case even if it happens it won't lead to synchronous external abort as
it is safe to read the register and written value will be ignored for
reserved bits(unsupported channels) in this register.

Cheers,
Biju

Re: [PATCH v3 6/8] iio: adc: rzg2l_adc: Rename num_channels to max_channels

[Geert Uytterhoeven]

Hi Biju,

Thanks for your patch!

On Tue, 22 Sept 2026 at 06:28, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Rename the num_channels member of struct rzg2l_adc_hw_params to
> max_channels, as it represents the maximum channel supported by

... maximum number of channels...

"the maximum channel" (aka singular "max_channel") would be equal to
the maximum number of channels minus one.

> the ADC hardware rather than a count of channels currently in use.
>
> No functional change intended.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

> --- a/drivers/iio/adc/rzg2l_adc.c
> +++ b/drivers/iio/adc/rzg2l_adc.c
> @@ -62,7 +62,7 @@
>   * @adsmp_mask: ADC sampling period mask (see ADM3 register)
>   * @adint_inten_mask: conversion end interrupt mask (see ADINT register)
>   * @default_adcmp: default ADC cmp (see ADM3 register)
> - * @num_channels: number of supported channels
> + * @max_channels: the maximum channel for the ADC

"maximum number of channels", to avoid confusion.

>   * @adivc: specifies if ADVIC register is available
>   */
>  struct rzg2l_adc_hw_params {

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 6/8] iio: adc: rzg2l_adc: Rename num_channels to max_channels

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 22 September 2026 15:34
> Subject: Re: [PATCH v3 6/8] iio: adc: rzg2l_adc: Rename num_channels to max_channels
> 
> Hi Biju,
> 
> Thanks for your patch!
> 
> On Tue, 22 Sept 2026 at 06:28, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Rename the num_channels member of struct rzg2l_adc_hw_params to
> > max_channels, as it represents the maximum channel supported by
> 
> ... maximum number of channels...

Ok.

> 
> "the maximum channel" (aka singular "max_channel") would be equal to the maximum number of channels minus
> one.
> 
> > the ADC hardware rather than a count of channels currently in use.
> >
> > No functional change intended.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> > --- a/drivers/iio/adc/rzg2l_adc.c
> > +++ b/drivers/iio/adc/rzg2l_adc.c
> > @@ -62,7 +62,7 @@
> >   * @adsmp_mask: ADC sampling period mask (see ADM3 register)
> >   * @adint_inten_mask: conversion end interrupt mask (see ADINT register)
> >   * @default_adcmp: default ADC cmp (see ADM3 register)
> > - * @num_channels: number of supported channels
> > + * @max_channels: the maximum channel for the ADC
> 
> "maximum number of channels", to avoid confusion.

Agreed. Will fix this in next version.

Cheers,
Biju

Re: [PATCH v3 6/8] iio: adc: rzg2l_adc: Rename num_channels to max_channels

[Jonathan Cameron]

On Wed, 23 Sep 2026 08:21:29 +0000
Biju Das <biju.das.jz@bp.renesas.com> wrote:

> Hi Geert,
> 
> Thanks for the feedback.
FWIW other than fixing this up, the ADC parts of this series
look good to me.  I'm assuming they can go through IIO whilst
the rest goes through whatever tree makes sense?

Jonathan

RE: [PATCH v3 6/8] iio: adc: rzg2l_adc: Rename num_channels to max_channels

[Biju Das]

Hi Jonathan Cameron,

> -----Original Message-----
> From: Jonathan Cameron <jic23@kernel.org>
> Sent: 25 September 2026 03:55
> Subject: Re: [PATCH v3 6/8] iio: adc: rzg2l_adc: Rename num_channels to max_channels
> 
> On Wed, 23 Sep 2026 08:21:29 +0000
> Biju Das <biju.das.jz@bp.renesas.com> wrote:
> 
> > Hi Geert,
> >
> > Thanks for the feedback.
> FWIW other than fixing this up, the ADC parts of this series look good to me.  I'm assuming they can go
> through IIO whilst the rest goes through whatever tree makes sense?

I think so. Binding + driver patches can go via IIO.
I will send v4 with fixing driver + Rob' Rb tag for binding[1].

[1] https://lore.kernel.org/all/TY3PR01MB11346568D44110BCA1CDD146D86802@TY3PR01MB11346.jpnprd01.prod.outlook.com/

Cheers,
Biju

Re: [PATCH v3 6/8] iio: adc: rzg2l_adc: Rename num_channels to max_channels

[Jonathan Cameron]

On Tue, 22 Sep 2026 16:33:51 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:

> Hi Biju,
> 
> Thanks for your patch!
> 
> On Tue, 22 Sept 2026 at 06:28, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Rename the num_channels member of struct rzg2l_adc_hw_params to
> > max_channels, as it represents the maximum channel supported by  
> 
> ... maximum number of channels...
> 
> "the maximum channel" (aka singular "max_channel") would be equal to
> the maximum number of channels minus one.

Ah. I just looked at v4 and realised I'd not been paying attention.
The number isn't the maximum number of channels because it's a sparse
set for the new part being added.  It is the oddity of maximum channel
number and as such.  Ah well. I think at this stage this distinction
doesn't really matter.

Jonathan

> 
> > the ADC hardware rather than a count of channels currently in use.
> >
> > No functional change intended.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>  
> 
> > --- a/drivers/iio/adc/rzg2l_adc.c
> > +++ b/drivers/iio/adc/rzg2l_adc.c
> > @@ -62,7 +62,7 @@
> >   * @adsmp_mask: ADC sampling period mask (see ADM3 register)
> >   * @adint_inten_mask: conversion end interrupt mask (see ADINT register)
> >   * @default_adcmp: default ADC cmp (see ADM3 register)
> > - * @num_channels: number of supported channels
> > + * @max_channels: the maximum channel for the ADC  
> 
> "maximum number of channels", to avoid confusion.
> 
> >   * @adivc: specifies if ADVIC register is available
> >   */
> >  struct rzg2l_adc_hw_params {  
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

Re: [PATCH v3 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Krzysztof Kozlowski]

On Tue, Sep 22, 2026 at 05:26:57AM +0100, Biju Das wrote:
> Add the renesas,r9a08g046-adc1 compatible string for the ADC1
> instance on RZ/G3L, which is dedicated to the on-chip TSU (thermal

Is there ADC2 instance?

> sensor unit). Unlike the other ADC instances, this one only exposes
> a single channel (channel@8), so restrict the allowed channel nodes
> accordingly.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * Dropped required property '#io-channel-cells'.
> v1->v2:
>  * No Change.
> ---
>  .../bindings/iio/adc/renesas,rzg2l-adc.yaml     | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
> index 40341d541726..f08f5439d127 100644
> --- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
> @@ -25,7 +25,9 @@ properties:
>                - renesas,r9a07g054-adc   # RZ/V2L
>            - const: renesas,rzg2l-adc
>        - items:
> -          - const: renesas,r9a08g045-adc  # RZ/G3S
> +          - enum:
> +              - renesas,r9a08g045-adc   # RZ/G3S
> +              - renesas,r9a08g046-adc1  # RZ/G3L ADC for TSU
>  
>    reg:
>      maxItems: 1
> @@ -121,6 +123,19 @@ allOf:
>              reg:
>                maximum: 7
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a08g046-adc1
> +    then:
> +      patternProperties:
> +        "^channel@[0-7]$": false
> +        "^channel@[8]$":

Why number 8? Does datasheet actually calls it that way?

> +          properties:
> +            reg:
> +              const: 8

Best regards,
Krzysztof

RE: [PATCH v3 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Biju Das]

Hi Krzysztof Kozlowski,

Thanks for the feedback.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 28 September 2026 07:05
> Subject: Re: [PATCH v3 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
> 
> On Tue, Sep 22, 2026 at 05:26:57AM +0100, Biju Das wrote:
> > Add the renesas,r9a08g046-adc1 compatible string for the ADC1 instance
> > on RZ/G3L, which is dedicated to the on-chip TSU (thermal
> 
> Is there ADC2 instance?

There is no ADC2 IP on RZ/G3L SoC.

> 
> > sensor unit). Unlike the other ADC instances, this one only exposes a
> > single channel (channel@8), so restrict the allowed channel nodes
> > accordingly.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2->v3:
> >  * Dropped required property '#io-channel-cells'.
> > v1->v2:
> >  * No Change.
> > ---
> >  .../bindings/iio/adc/renesas,rzg2l-adc.yaml     | 17 ++++++++++++++++-
> >  1 file changed, 16 insertions(+), 1 deletion(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
> > b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
> > index 40341d541726..f08f5439d127 100644
> > --- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
> > +++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
> > @@ -25,7 +25,9 @@ properties:
> >                - renesas,r9a07g054-adc   # RZ/V2L
> >            - const: renesas,rzg2l-adc
> >        - items:
> > -          - const: renesas,r9a08g045-adc  # RZ/G3S
> > +          - enum:
> > +              - renesas,r9a08g045-adc   # RZ/G3S
> > +              - renesas,r9a08g046-adc1  # RZ/G3L ADC for TSU
> >
> >    reg:
> >      maxItems: 1
> > @@ -121,6 +123,19 @@ allOf:
> >              reg:
> >                maximum: 7
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,r9a08g046-adc1
> > +    then:
> > +      patternProperties:
> > +        "^channel@[0-7]$": false
> > +        "^channel@[8]$":
> 
> Why number 8? Does datasheet actually calls it that way?

Yes , Hardware manual mentions it.

For ADC1 IP, the source is ADC_CH8(TSU) for the Analog Input Channel.

Cheers,
Biju

Re: [PATCH v3 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Krzysztof Kozlowski]

On 28/09/2026 08:25, Biju Das wrote:
> Hi Krzysztof Kozlowski,
> 
> Thanks for the feedback.
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 28 September 2026 07:05
>> Subject: Re: [PATCH v3 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
>>
>> On Tue, Sep 22, 2026 at 05:26:57AM +0100, Biju Das wrote:
>>> Add the renesas,r9a08g046-adc1 compatible string for the ADC1 instance
>>> on RZ/G3L, which is dedicated to the on-chip TSU (thermal
>>
>> Is there ADC2 instance?
> 
> There is no ADC2 IP on RZ/G3L SoC.

Then I am a bit confused calling it ADC1 here and in the compatible.

Best regards,
Krzysztof

RE: [PATCH v3 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Biju Das]

Hi Krzysztof Kozlowski,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 28 September 2026 07:27
> Subject: Re: [PATCH v3 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
> 
> On 28/09/2026 08:25, Biju Das wrote:
> > Hi Krzysztof Kozlowski,
> >
> > Thanks for the feedback.
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: 28 September 2026 07:05
> >> Subject: Re: [PATCH v3 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc:
> >> Document RZ/G3L ADC for TSU
> >>
> >> On Tue, Sep 22, 2026 at 05:26:57AM +0100, Biju Das wrote:
> >>> Add the renesas,r9a08g046-adc1 compatible string for the ADC1
> >>> instance on RZ/G3L, which is dedicated to the on-chip TSU (thermal
> >>
> >> Is there ADC2 instance?
> >
> > There is no ADC2 IP on RZ/G3L SoC.
> 
> Then I am a bit confused calling it ADC1 here and in the compatible.


Hardware manual mentions this IP as "A/D Converter for TSU (ADC1)"
that is the reason compatible has adc1.

Cheers,
Biju

Re: [PATCH v3 5/8] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU

[Krzysztof Kozlowski]

On 22/09/2026 06:26, Biju Das wrote:
> Add the renesas,r9a08g046-adc1 compatible string for the ADC1
> instance on RZ/G3L, which is dedicated to the on-chip TSU (thermal
> sensor unit). Unlike the other ADC instances, this one only exposes
> a single channel (channel@8), so restrict the allowed channel nodes
> accordingly.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof