Re: [PATCH v4 7/7] arm64: dts: renesas: r9a08g046: Enable TSU

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dts: r9a08g046: io-channels uses logical array index instead of hw channel id
--

commit d469fb6214e936db705b38d76e1e6de3a390e861
Author: Biju Das <biju.das.jz@bp.renesas.com>

arm64: dts: renesas: r9a08g046: Enable TSU

This commit adds cooling cells to the CPU nodes and describes the ADC1 and
TSU nodes. It sets up a CPU thermal zone using passive and critical trip
points for thermal mitigation.

> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index c63a857f0e5b0..a2f6718c0043a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
[ ... ]
> @@ -270,6 +274,37 @@ scif5: serial@1004e000 {
>  			status = "disabled";
>  		};
>  
> +		adc1: adc@108c0000 {
> +			compatible = "renesas,r9a08g046-adc1";
> +			reg = <0 0x108c0000 0 0x10000>;
> +			interrupts = <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>;
> +			clocks = <&cpg CPG_MOD R9A08G046_ADC1_ADCLK>,
> +				 <&cpg CPG_MOD R9A08G046_ADC1_PCLK>;
> +			clock-names = "adclk", "pclk";
> +			resets = <&cpg R9A08G046_ADC1_PRESETN>,
> +				 <&cpg R9A08G046_ADC1_ADRST_N>;
> +			reset-names = "presetn", "adrst-n";
> +			power-domains = <&cpg>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#io-channel-cells = <1>;
> +
> +			channel@8 {
> +				reg = <8>;
> +			};
> +		};
> +
> +		tsu: thermal@108d0000 {
> +			compatible = "renesas,r9a08g046-tsu";
> +			reg = <0 0x108d0000 0 0x10000>;
> +			clocks = <&cpg CPG_MOD R9A08G046_TSU_PCLK>;
> +			resets = <&cpg R9A08G046_TSU_PRESETN>;
> +			power-domains = <&cpg>;
> +			#thermal-sensor-cells = <0>;
> +			io-channels = <&adc1 0>;

[Severity: Medium]
Does this io-channels assignment in the tsu node incorrectly use a logical
array index instead of the hardware channel ID?

The renesas,r9a08g046-adc1 ADC provides a temperature channel at hardware
index 8 (channel@8), but this configuration uses index 0. Because the
rzg2l_adc driver lacks a custom .fwnode_xlate callback, the IIO core falls
back to __fwnode_iio_simple_xlate(). This fallback bounds-checks the
requested channel against the allocated array length (which is 1 here),
meaning the correct hardware ID <&adc1 8> would fail with -EINVAL.

Using <&adc1 0> works around this driver limitation by matching the 0th
element, but it leaks the Linux kernel internal array layout into the
hardware description. If another channel is ever added to the device tree
in arch/arm64/boot/dts/renesas/r9a08g046.dtsi, the array indices will shift
and <&adc1 0> could silently bind the TSU to the wrong ADC channel.

> +			io-channel-names = "tsu";
> +		};
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260925061617.127349-1-biju.das.jz@bp.renesas.com?part=7