From: Jonathan Cameron <jic23@kernel.org>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Daniel Lezcano <daniel.lezcano@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Zhang Rui <rui.zhang@intel.com>,
Lukasz Luba <lukasz.luba@arm.com>,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v4 0/7] Add Renesas RZ/G3L TSU support
Date: Sun, 27 Sep 2026 19:22:11 +0100 [thread overview]
Message-ID: <20260927192211.03ebd188@jic23-hlaptop> (raw)
In-Reply-To: <20260925061617.127349-1-biju.das.jz@bp.renesas.com>
On Fri, 25 Sep 2026 07:15:58 +0100
Biju Das <biju.das.jz@bp.renesas.com> wrote:
> The Thermal sensor unit (a.k.a TSU) IP found on the RZ/G3L SoC is similar
> to the RZ/G3S, but it has different calibration constants. Moreover, the
> TSU is connected to A/D converter of TSU (a.k.a ADC1) on the RZ/G3L,
> whereas it is connected to ADC0 on the RZ/G3S.
>
> Compared to ADC0, there are no A/D conversion result registers(ADCR0 to
> ADCR7) on the RZ/G3L, and the INTEN bits in the A/D converter interrupt
> control register(a.k.a ADINT) are also different.
>
> This patch series aims to add support for TSU along with ADC1.
>
> Merge strategy:
> * patch #1-#3 thermal subsystem
> * patch #4-#6 iio subsystem
Applied these to the testing branch of iio.git. That will show
up in linux-next once 0-day has taken a first look at it.
Thanks,
Jonathan
> * patch #7 SoC subsystem
>
> v3->v4:
> * Dropped clk patch as it is accepted.
> * Collected tag.
> * Updated commit description for patch#5.
> * Updated kernel doc comment for max_channels.
> v2->v3:
> * Collected tags
> * Dropped required property '#io-channel-cells' from bindings.
> * Renamed num_channels to max_channels in struct rzg2l_adc_hw_params
> v1->v2:
> * Merged TSU and ADC1 series together.
> * Moved the clk patch.
>
> Biju Das (7):
> dt-bindings: thermal: r9a08g045-tsu: Document RZ/G3L TSU
> thermal/drivers/renesas/rzg3s: Convert calibration defaults to per-SoC
> match data
> thermal/drivers/renesas/rzg3s: Add RZ/G3L TSU support
> dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU
> iio: adc: rzg2l_adc: Rename num_channels to max_channels
> iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU
> arm64: dts: renesas: r9a08g046: Enable TSU
>
> .../bindings/iio/adc/renesas,rzg2l-adc.yaml | 17 ++++-
> .../thermal/renesas,r9a08g045-tsu.yaml | 4 +-
> arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 66 +++++++++++++++++++
> drivers/iio/adc/rzg2l_adc.c | 29 +++++---
> drivers/thermal/renesas/rzg3s_thermal.c | 38 ++++++++---
> 5 files changed, 133 insertions(+), 21 deletions(-)
>
next prev parent reply other threads:[~2026-09-27 18:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-25 6:15 [PATCH v4 0/7] Add Renesas RZ/G3L TSU support Biju Das
2026-09-25 6:15 ` [PATCH v4 1/7] dt-bindings: thermal: r9a08g045-tsu: Document RZ/G3L TSU Biju Das
2026-09-25 8:37 ` Claudiu Beznea
2026-09-25 6:16 ` [PATCH v4 4/7] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3L ADC for TSU Biju Das
2026-09-25 6:16 ` [PATCH v4 5/7] iio: adc: rzg2l_adc: Rename num_channels to max_channels Biju Das
2026-09-25 6:16 ` [PATCH v4 6/7] iio: adc: rzg2l_adc: Add RZ/G3L ADC support for TSU Biju Das
2026-09-25 6:16 ` [PATCH v4 7/7] arm64: dts: renesas: r9a08g046: Enable TSU Biju Das
2026-09-25 6:28 ` sashiko-bot
2026-09-27 18:22 ` Jonathan Cameron [this message]
2026-09-27 21:02 ` [PATCH v4 0/7] Add Renesas RZ/G3L TSU support Daniel Lezcano
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