Re: [PATCH 2/8] iio: adc: rzt2h: Wait for the analog part to stop after a forced stop

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] iio: adc: rzt2h: missing MMIO flush before ndelay() in rzt2h_adc_stop()
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commit 1a5e9531ca2dbd42c2e42cbda9b1697ed221201c
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

iio: adc: rzt2h: Wait for the analog part to stop after a forced stop

When ADCSR.ADST is cleared to forcibly stop a conversion, the analog part
of the A/D converter can take up to 2 ADCLK cycles to stop operating. This
commit adds a delay after clearing the bit to ensure the hardware stops
before reconfiguring it.

> diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c
> index 8ba7b0fde8a19..d53888730f003 100644
> --- a/drivers/iio/adc/rzt2h_adc.c
> +++ b/drivers/iio/adc/rzt2h_adc.c
[ ... ]
> @@ -124,6 +126,13 @@ static void rzt2h_adc_stop(struct rzt2h_adc *adc)
>  	reg &= ~(RZT2H_ADCSR_ADIE_MASK | RZT2H_ADCSR_ADST_MASK);
>  
>  	writew(reg, adc->base + RZT2H_ADCSR_REG);
> +
> +	/*
> +	 * When a conversion is forcibly stopped, the analog part of the A/D
> +	 * converter takes up to 2 ADCLK cycles to stop operating.
> +	 */
> +	ndelay(DIV_ROUND_UP_ULL((u64)RZT2H_ADC_STOP_CYCLES * NSEC_PER_SEC,
> +				adc->adclk_rate));

[Severity: Medium]
Will this short delay complete before the write has actually reached the ADC
hardware?

Since writew() is a posted write on ARM architectures, the CPU does not block
until the transaction reaches the peripheral. Because ndelay() is called
immediately afterward and the delay is very short, the CPU might finish
waiting before the stop command even arrives at the ADC hardware.

Does this need a dummy readback (e.g., readw()) to flush the write buffer
before calling ndelay(), to guarantee the stop command has arrived before
timing the 2 ADCLK cycles?

>  }

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Sashiko AI review · https://sashiko.dev/#/patchset/20260929124248.237032-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=2