* [PATCH 0/4] Add ADC support for RZ/V2H(P) and RZ/V2N SoCs
@ 2026-09-29 12:48 Prabhakar
2026-09-29 12:48 ` [PATCH 1/4] arm64: dts: renesas: r9a09g057: Add ADC node Prabhakar
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Prabhakar @ 2026-09-29 12:48 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Cosmin Tanislav
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi all,
This series aims to add ADC support for the RZ/V2H(P) and RZ/V2N SoCs
and enable it on the respective EVKs.
Note this series depends on below:
- https://lore.kernel.org/all/20260929124248.237032-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
- https://lore.kernel.org/all/20260929122407.219448-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
Lad Prabhakar (4):
arm64: dts: renesas: r9a09g057: Add ADC node
arm64: dts: renesas: r9a09g056: Add ADC nodes
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable ADC
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable ADC
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 144 ++++++++++++++++++
.../dts/renesas/r9a09g056n48-rzv2n-evk.dts | 12 ++
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 48 ++++++
.../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 4 +
4 files changed, 208 insertions(+)
--
2.55.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/4] arm64: dts: renesas: r9a09g057: Add ADC node 2026-09-29 12:48 [PATCH 0/4] Add ADC support for RZ/V2H(P) and RZ/V2N SoCs Prabhakar @ 2026-09-29 12:48 ` Prabhakar 2026-09-29 12:48 ` [PATCH 2/4] arm64: dts: renesas: r9a09g056: Add ADC nodes Prabhakar ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Prabhakar @ 2026-09-29 12:48 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Cosmin Tanislav Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add the ADC device node to the RZ/V2H(P) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index bbaab75681c2..d40d38c6a31c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -608,6 +608,54 @@ wdt1: watchdog@14400000 { status = "disabled"; }; + adc: adc@11c00000 { + compatible = "renesas,r9a09g057-adc"; + reg = <0 0x11c00000 0 0x400>; + interrupts = <GIC_SPI 918 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 919 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 920 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi"; + clocks = <&cpg CPG_MOD 0x108>, <&cpg CPG_MOD 0x107>; + clock-names = "adclk", "pclk"; + resets = <&cpg 0xf6>; + power-domains = <&cpg>; + dmas = <&dmac0 0x24c8>, <&dmac1 0x24c8>, <&dmac2 0x24c8>, + <&dmac3 0x24c8>, <&dmac4 0x24c8>; + dma-names = "rx", "rx", "rx", "rx", "rx"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; + }; + rtc: rtc@11c00800 { compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3"; reg = <0 0x11c00800 0 0x400>; -- 2.55.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/4] arm64: dts: renesas: r9a09g056: Add ADC nodes 2026-09-29 12:48 [PATCH 0/4] Add ADC support for RZ/V2H(P) and RZ/V2N SoCs Prabhakar 2026-09-29 12:48 ` [PATCH 1/4] arm64: dts: renesas: r9a09g057: Add ADC node Prabhakar @ 2026-09-29 12:48 ` Prabhakar 2026-09-29 13:13 ` sashiko-bot 2026-09-29 12:48 ` [PATCH 3/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable ADC Prabhakar 2026-09-29 12:48 ` [PATCH 4/4] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: " Prabhakar 3 siblings, 1 reply; 6+ messages in thread From: Prabhakar @ 2026-09-29 12:48 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Cosmin Tanislav Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add the three ADC device nodes to the RZ/V2N SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 144 +++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 175e24c98e11..51370f38989d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -626,6 +626,150 @@ wdt1: watchdog@14400000 { status = "disabled"; }; + adc0: adc@11c00000 { + compatible = "renesas,r9a09g056-adc", "renesas,r9a09g057-adc"; + reg = <0 0x11c00000 0 0x400>; + interrupts = <GIC_SPI 918 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 919 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 920 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi"; + clocks = <&cpg CPG_MOD 0x108>, <&cpg CPG_MOD 0x107>; + clock-names = "adclk", "pclk"; + resets = <&cpg 0xf6>; + power-domains = <&cpg>; + dmas = <&dmac0 0x24c8>, <&dmac1 0x24c8>, <&dmac2 0x24c8>, + <&dmac3 0x24c8>, <&dmac4 0x24c8>; + dma-names = "rx", "rx", "rx", "rx", "rx"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; + }; + + adc1: adc@11c02800 { + compatible = "renesas,r9a09g056-adc", "renesas,r9a09g057-adc"; + reg = <0 0x11c02800 0 0x400>; + interrupts = <GIC_SPI 926 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 927 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 928 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 930 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi"; + clocks = <&cpg CPG_MOD 0x108>, <&cpg CPG_MOD 0x107>; + clock-names = "adclk", "pclk"; + resets = <&cpg 0xf6>; + power-domains = <&cpg>; + dmas = <&dmac0 0x25b5>, <&dmac1 0x25b5>, <&dmac2 0x25b5>, + <&dmac3 0x25b5>, <&dmac4 0x25b5>; + dma-names = "rx", "rx", "rx", "rx", "rx"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; + }; + + adc2: adc@11c02c00 { + compatible = "renesas,r9a09g056-adc", "renesas,r9a09g057-adc"; + reg = <0 0x11c02c00 0 0x400>; + interrupts = <GIC_SPI 931 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 932 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 933 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 934 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 935 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi"; + clocks = <&cpg CPG_MOD 0x108>, <&cpg CPG_MOD 0x107>; + clock-names = "adclk", "pclk"; + resets = <&cpg 0xf6>; + power-domains = <&cpg>; + dmas = <&dmac0 0x25ba>, <&dmac1 0x25ba>, <&dmac2 0x25ba>, + <&dmac3 0x25ba>, <&dmac4 0x25ba>; + dma-names = "rx", "rx", "rx", "rx", "rx"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; + }; + rtc: rtc@11c00800 { compatible = "renesas,r9a09g056-rtca3", "renesas,rz-rtca3"; reg = <0 0x11c00800 0 0x400>; -- 2.55.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/4] arm64: dts: renesas: r9a09g056: Add ADC nodes 2026-09-29 12:48 ` [PATCH 2/4] arm64: dts: renesas: r9a09g056: Add ADC nodes Prabhakar @ 2026-09-29 13:13 ` sashiko-bot 0 siblings, 0 replies; 6+ messages in thread From: sashiko-bot @ 2026-09-29 13:13 UTC (permalink / raw) To: Prabhakar; +Cc: wsa+renesas, robh, devicetree, conor+dt Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] arm64: dts: undefined CPG module clocks and reset IDs in ADC nodes - [High] arm64: dts: adc1 and adc2 nodes incorrectly share adc0 clocks and resets - [Medium] arm64: dts: missing #io-channel-cells property in ADC nodes -- commit 227934acdf450f4bc0b48d576add5c164d83a5ed Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> arm64: dts: renesas: r9a09g056: Add ADC nodes This commit adds three ADC device nodes (adc0, adc1, and adc2) to the Renesas RZ/V2N SoC device tree. > diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi > index 77c2221a9e2a3..f03855f705312 100644 > --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi > @@ -626,6 +626,150 @@ wdt1: watchdog@14400000 { > status = "disabled"; > }; > > + adc0: adc@11c00000 { > + compatible = "renesas,r9a09g056-adc", "renesas,r9a09g057-adc"; > + reg = <0 0x11c00000 0 0x400>; > + interrupts = <GIC_SPI 918 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 919 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 920 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "adi", "gbadi", "gcadi", > + "cmpai", "cmpbi"; > + clocks = <&cpg CPG_MOD 0x108>, <&cpg CPG_MOD 0x107>; > + clock-names = "adclk", "pclk"; > + resets = <&cpg 0xf6>; [Severity: High] Are these CPG module clock IDs (0x107, 0x108) and reset ID (0xf6) defined in the r9a09g056-cpg.c clock driver? If they are not implemented, the rzg2l_adc driver will fail to probe or infinitely defer when it calls clk_get() and devm_reset_control_get_exclusive_deasserted() during probe. > + power-domains = <&cpg>; > + dmas = <&dmac0 0x24c8>, <&dmac1 0x24c8>, <&dmac2 0x24c8>, > + <&dmac3 0x24c8>, <&dmac4 0x24c8>; > + dma-names = "rx", "rx", "rx", "rx", "rx"; > + status = "disabled"; > + > + #address-cells = <1>; > + #size-cells = <0>; [Severity: Medium] Should there be an #io-channel-cells = <1>; property defined here? Without it, the ADC nodes cannot function as IIO providers via device tree phandles. Any consumer driver trying to reference the ADC via an io-channels property will fail to parse when calling iio_channel_get() to look up its provider. [ ... ] > + adc1: adc@11c02800 { [ ... ] > + clocks = <&cpg CPG_MOD 0x108>, <&cpg CPG_MOD 0x107>; > + clock-names = "adclk", "pclk"; > + resets = <&cpg 0xf6>; [ ... ] > + adc2: adc@11c02c00 { [ ... ] > + clocks = <&cpg CPG_MOD 0x108>, <&cpg CPG_MOD 0x107>; > + clock-names = "adclk", "pclk"; > + resets = <&cpg 0xf6>; [Severity: High] Do adc1 and adc2 use the exact same clocks and reset lines as adc0? Since the rzg2l_adc driver requests exclusive reset lines via devm_reset_control_get_exclusive_deasserted(), probing adc1 and adc2 will fail with -EBUSY because adc0 already holds the exclusive reset line. If they were shared instead, resetting one active ADC instance would inadvertently reset the others, leading to state corruption. -- Sashiko AI review · https://sashiko.dev/#/patchset/20260929124829.237997-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=2 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable ADC 2026-09-29 12:48 [PATCH 0/4] Add ADC support for RZ/V2H(P) and RZ/V2N SoCs Prabhakar 2026-09-29 12:48 ` [PATCH 1/4] arm64: dts: renesas: r9a09g057: Add ADC node Prabhakar 2026-09-29 12:48 ` [PATCH 2/4] arm64: dts: renesas: r9a09g056: Add ADC nodes Prabhakar @ 2026-09-29 12:48 ` Prabhakar 2026-09-29 12:48 ` [PATCH 4/4] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: " Prabhakar 3 siblings, 0 replies; 6+ messages in thread From: Prabhakar @ 2026-09-29 12:48 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Cosmin Tanislav Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Enable the ADC on the RZ/V2H EVK. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 0926ab891fa5..8939e35639a5 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -130,6 +130,10 @@ y1: y1-clock { }; }; +&adc { + status = "okay"; +}; + &audio_extal_clk { clock-frequency = <22579200>; }; -- 2.55.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable ADC 2026-09-29 12:48 [PATCH 0/4] Add ADC support for RZ/V2H(P) and RZ/V2N SoCs Prabhakar ` (2 preceding siblings ...) 2026-09-29 12:48 ` [PATCH 3/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable ADC Prabhakar @ 2026-09-29 12:48 ` Prabhakar 3 siblings, 0 replies; 6+ messages in thread From: Prabhakar @ 2026-09-29 12:48 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Cosmin Tanislav Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Enable the ADCs on the RZ/V2N EVK. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index c43325dd1c55..5daad7f37e3d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -122,6 +122,18 @@ y1: y1-clock { }; }; +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&adc2 { + status = "okay"; +}; + &audio_extal_clk { clock-frequency = <22579200>; }; -- 2.55.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-09-29 13:13 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-09-29 12:48 [PATCH 0/4] Add ADC support for RZ/V2H(P) and RZ/V2N SoCs Prabhakar 2026-09-29 12:48 ` [PATCH 1/4] arm64: dts: renesas: r9a09g057: Add ADC node Prabhakar 2026-09-29 12:48 ` [PATCH 2/4] arm64: dts: renesas: r9a09g056: Add ADC nodes Prabhakar 2026-09-29 13:13 ` sashiko-bot 2026-09-29 12:48 ` [PATCH 3/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable ADC Prabhakar 2026-09-29 12:48 ` [PATCH 4/4] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: " Prabhakar
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox