* [PATCH v5 1/4] arm64: dts: qcom: shikra: Add MDSS display subsystem
2026-09-30 11:15 [PATCH v5 0/4] arm64: qcom: dts: Add display support for Qualcomm Shikra Nabige Aala
@ 2026-09-30 11:15 ` Nabige Aala
2026-09-30 11:25 ` sashiko-bot
2026-09-30 11:15 ` [PATCH v5 2/4] arm64: dts: qcom: shikra-cqs-evk: Enable display and add ili7807s panel Nabige Aala
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Nabige Aala @ 2026-09-30 11:15 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Abel Vesa
Cc: Arpit Saini, Nabige Aala, linux-arm-msm, devicetree, linux-kernel,
Dmitry Baryshkov, Konrad Dybcio
Add the SoC-level display subsystem nodes for Qualcomm Shikra:
MDSS wrapper,DPU display controller, DSI host controller, and
14nm DSI PHY.
Qualcomm Shikra uses DPU 6.5 hardware (same as QCM2290). Platform-specific
compatible strings are used as the primary match with QCM2290 fallbacks
to reuse the existing driver support.
The dispcc clock inputs for the DSI byte and pixel PLLs are wired
from mdss_dsi0_phy.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 206 ++++++++++++++++++++++++++++++++++-
1 file changed, 204 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 9823c591b02b..4ff85c1c8fdd 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-audiocorecc.h>
@@ -2809,6 +2810,207 @@ adreno_smmu: iommu@59a0000 {
power-domains = <&gpucc GPU_CX_GDSC>;
};
+ mdss: display-subsystem@5e00000 {
+ compatible = "qcom,shikra-mdss", "qcom,qcm2290-mdss";
+ reg = <0x0 0x05e00000 0x0 0x1000>;
+ reg-names = "mdss";
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core";
+
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ iommus = <&apps_smmu 0x420 0x2>;
+ interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdp: display-controller@5e01000 {
+ compatible = "qcom,shikra-dpu", "qcom,qcm2290-dpu";
+ reg = <0x0 0x05e01000 0x0 0x8f000>,
+ <0x0 0x05eb0000 0x0 0x3000>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "core",
+ "lut",
+ "vsync";
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmpd_opp_min_svs>;
+ };
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-256000000 {
+ opp-hz = /bits/ 64 <256000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@5e94000 {
+ compatible = "qcom,shikra-dsi-ctrl",
+ "qcom,qcm2290-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0x0 0x05e94000 0x0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
+ phys = <&mdss_dsi0_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmpd_opp_min_svs>;
+ };
+
+ opp-164000000 {
+ opp-hz = /bits/ 64 <164000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@5e94400 {
+ compatible = "qcom,dsi-phy-14nm-2290";
+ reg = <0x0 0x05e94400 0x0 0x100>,
+ <0x0 0x05e94500 0x0 0x300>,
+ <0x0 0x05e94800 0x0 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface",
+ "ref";
+
+ power-domains = <&rpmpd RPMPD_VDDMX>;
+ required-opps = <&rpmpd_opp_nom>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
dispcc: clock-controller@5f00000 {
compatible = "qcom,shikra-dispcc", "qcom,qcm2290-dispcc";
reg = <0x0 0x05f00000 0x0 0x20000>;
@@ -2816,8 +3018,8 @@ dispcc: clock-controller@5f00000 {
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
- <0>,
- <0>;
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"gcc_disp_gpll0_clk_src",
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 2/4] arm64: dts: qcom: shikra-cqs-evk: Enable display and add ili7807s panel
2026-09-30 11:15 [PATCH v5 0/4] arm64: qcom: dts: Add display support for Qualcomm Shikra Nabige Aala
2026-09-30 11:15 ` [PATCH v5 1/4] arm64: dts: qcom: shikra: Add MDSS display subsystem Nabige Aala
@ 2026-09-30 11:15 ` Nabige Aala
2026-09-30 11:27 ` sashiko-bot
2026-09-30 11:15 ` [PATCH v5 3/4] arm64: dts: qcom: shikra-cqm-evk: " Nabige Aala
2026-09-30 11:15 ` [PATCH v5 4/4] arm64: defconfig: Enable ILI7807S DSI panel driver Nabige Aala
3 siblings, 1 reply; 8+ messages in thread
From: Nabige Aala @ 2026-09-30 11:15 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Abel Vesa
Cc: Arpit Saini, Nabige Aala, linux-arm-msm, devicetree, linux-kernel
From: Arpit Saini <arpit.saini@oss.qualcomm.com>
Enable the Shikra MDSS display subsystem on the Qualcomm Shikra CQS EVK
board and add the DLC0697 MIPI DSI display panel node.
Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
Signed-off-by: Arpit Saini <arpit.saini@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 110 ++++++++++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index 7a2f3e1518fd..5e49a5c71a77 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -23,6 +23,86 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ lcd_bias: regulator-lcd-bias {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd_bias";
+ gpio = <&tlmm 151 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-0 = <&lcd_bias_en>;
+ pinctrl-names = "default";
+ };
+
+ vreg_disp_n: regulator-vreg-disp-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_disp_n";
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ vin-supply = <&lcd_bias>;
+ };
+
+ vreg_disp_p: regulator-vreg-disp-p {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_disp_p";
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ vin-supply = <&lcd_bias>;
+ };
+
+ vreg_wled: regulator-wled {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_wled";
+ gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&pm4125_l5>;
+
+ status = "okay";
+
+ panel@0 {
+ compatible = "dlc,dlc0697", "ilitek,ili7807s";
+ reg = <0>;
+
+ reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+
+ vddi-supply = <&pm4125_l15>;
+ avdd-supply = <&vreg_disp_p>;
+ avee-supply = <&vreg_disp_n>;
+ wled-supply = <&vreg_wled>;
+
+ pinctrl-0 = <&panel_rst_n &panel_te_pin>;
+ pinctrl-1 = <&panel_rst_n_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+};
+
+&pm4125_l5 {
+ /* DSI VDDA - must be at NOM voltage for PHY PLL lock */
+ regulator-min-microvolt = <1232000>;
+ regulator-max-microvolt = <1232000>;
+ regulator-allow-set-load;
};
&remoteproc_cdsp {
@@ -89,3 +169,33 @@ &usb_2_hsphy {
status = "okay";
};
+
+&tlmm {
+ panel_rst_n: panel-rst-n-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ panel_rst_n_suspend: panel-rst-n-suspend-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ panel_te_pin: panel-te-pin-state {
+ pins = "gpio86";
+ function = "mdp_vsync_p";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ lcd_bias_en: lcd-bias-en-state {
+ pins = "gpio151";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 3/4] arm64: dts: qcom: shikra-cqm-evk: Enable display and add ili7807s panel
2026-09-30 11:15 [PATCH v5 0/4] arm64: qcom: dts: Add display support for Qualcomm Shikra Nabige Aala
2026-09-30 11:15 ` [PATCH v5 1/4] arm64: dts: qcom: shikra: Add MDSS display subsystem Nabige Aala
2026-09-30 11:15 ` [PATCH v5 2/4] arm64: dts: qcom: shikra-cqs-evk: Enable display and add ili7807s panel Nabige Aala
@ 2026-09-30 11:15 ` Nabige Aala
2026-09-30 11:26 ` sashiko-bot
2026-09-30 11:15 ` [PATCH v5 4/4] arm64: defconfig: Enable ILI7807S DSI panel driver Nabige Aala
3 siblings, 1 reply; 8+ messages in thread
From: Nabige Aala @ 2026-09-30 11:15 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Abel Vesa
Cc: Arpit Saini, Nabige Aala, linux-arm-msm, devicetree, linux-kernel
From: Arpit Saini <arpit.saini@oss.qualcomm.com>
Enable the Shikra MDSS display subsystem on the Qualcomm
Shikra CQM EVK board and add the DLC0697 MIPI DSI display
panel node. Pin pm4125_l5 to 1.232V with regulator-allow-set-load
for DSI PHY PLL stability.
Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
Signed-off-by: Arpit Saini <arpit.saini@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 110 ++++++++++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 6ad90df3b415..c42669164457 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -23,6 +23,86 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ lcd_bias: regulator-lcd-bias {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd_bias";
+ gpio = <&tlmm 151 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-0 = <&lcd_bias_en>;
+ pinctrl-names = "default";
+ };
+
+ vreg_disp_n: regulator-vreg-disp-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_disp_n";
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ vin-supply = <&lcd_bias>;
+ };
+
+ vreg_disp_p: regulator-vreg-disp-p {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_disp_p";
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ vin-supply = <&lcd_bias>;
+ };
+
+ vreg_wled: regulator-wled {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_wled";
+ gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&pm4125_l5>;
+
+ status = "okay";
+
+ panel@0 {
+ compatible = "dlc,dlc0697", "ilitek,ili7807s";
+ reg = <0>;
+
+ reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+
+ vddi-supply = <&pm4125_l15>;
+ avdd-supply = <&vreg_disp_p>;
+ avee-supply = <&vreg_disp_n>;
+ wled-supply = <&vreg_wled>;
+
+ pinctrl-0 = <&panel_rst_n &panel_te_pin>;
+ pinctrl-1 = <&panel_rst_n_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+};
+
+&pm4125_l5 {
+ /* DSI VDDA - must be at NOM voltage for PHY PLL lock */
+ regulator-min-microvolt = <1232000>;
+ regulator-max-microvolt = <1232000>;
+ regulator-allow-set-load;
};
&audiocorecc {
@@ -93,3 +173,33 @@ &usb_2_hsphy {
status = "okay";
};
+
+&tlmm {
+ panel_rst_n: panel-rst-n-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ panel_rst_n_suspend: panel-rst-n-suspend-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ panel_te_pin: panel-te-pin-state {
+ pins = "gpio86";
+ function = "mdp_vsync_p";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ lcd_bias_en: lcd-bias-en-state {
+ pins = "gpio151";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread