Re: [PATCH v2 1/3] dt-bindings: mfd: as3722: Convert to json-schema

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] dt-bindings: mfd: as3722 strict 'pinmux' property name prevents multiple pinctrl states
- [Medium] dt-bindings: mfd: as3722 pinmux child node regex incorrectly rejects hyphens
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commit b7aefbb600a8c4a41917fc0749a39bff2e1a88d7
Author: Thierry Reding <treding@nvidia.com>

dt-bindings: mfd: as3722: Convert to json-schema

This commit converts the AMS AS3722 PMIC bindings from the free-form text
format to json-schema.

> diff --git a/Documentation/devicetree/bindings/mfd/ams,as3722.yaml b/Documentation/devicetree/bindings/mfd/ams,as3722.yaml
> new file mode 100644
> index 0000000000000..51910042c6216
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/ams,as3722.yaml
[ ... ]
> +  pinmux:
> +    description:
> +      Device has 8 GPIO pins which can be configured as GPIO as well as the
> +      special IO functions.
> +
> +    type: object
> +    additionalProperties: false

[Severity: Medium]
Does strictly naming this property "pinmux" prevent device trees from
declaring multiple unique pinctrl child nodes?

The original text binding supported pinctrl[0...n], but this strict naming and
additionalProperties: false will reject secondary pinctrl states like
pinmux-sleep since sibling nodes must have unique names. Should this be a
pattern property like "^(pinmux|pinctrl)(-[0-9a-z]+)?$" instead?

> +
> +    patternProperties:
> +      "^gpio[0-7_]+$":

[Severity: Medium]
Does this regex incorrectly reject hyphens in node names?

Existing device tree configurations such as gpio0-1-3-4-5-6 in
arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi use hyphens to group pins. Since
additionalProperties is set to false for the pinmux object, this regex will
cause valid existing nodes to fail schema validation.

> +        description:
> +          Child nodes of the pinmux node represent some desired configuration
> +          for a list of pins. This configuration can include the mux function
> +          to select on those pin(s), and various pin configuration parameters,
> +          such as pull-up, open drain.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260930-as3722-bindings-v2-0-a3bba649ebf9@nvidia.com?part=1