* [PATCH v1 1/8] dt-bindings: pinctrl: Add starfive,jhb100-adc0-pinctrl
2026-10-17 5:25 [PATCH v1 0/8] Add ADC, eMMC and VGA pinctrl for StarFive JHB100 SoC Changhuang Liang
@ 2026-10-17 5:25 ` Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 2/8] pinctrl: starfive: Add StarFive JHB100 adc0 controller driver Changhuang Liang
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Changhuang Liang @ 2026-10-17 5:25 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Arnd Bergmann, Bartosz Golaszewski, linux-gpio, linux-kernel,
devicetree, Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC ADC-0(adc0) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-adc0-pinctrl.yaml | 168 ++++++++++++++++++
1 file changed, 168 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc0-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc0-pinctrl.yaml
new file mode 100644
index 000000000000..5b4b44c5776c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc0-pinctrl.yaml
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-adc0-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 ADC-0 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "adc0" pinctrl domain.
+
+ The "adc0" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the ADC-0 Pin Controller, there are 8 multi-function GPIO_PADs. Each of
+ them can be multiplexed to several peripherals through function selection.
+ Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3. Function 0
+ is the default function which is generally the GPIO function. Function 1,
+ 2, and 3 are the alternate functions or peripheral signals that can be
+ routed to an iopad. The function selection can be carried out by writing
+ the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-adc0-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: ADC0 IOMUX
+ - description: ADC0 core
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce and
+ drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ adc, gpio, host0_port80, smbalert ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 5, 8, 10, 14, 16, 18, 20 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 5000, 8000, 10000, 14000, 16000, 18000, 20000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_adc0: pinctrl@11bc2800 {
+ compatible = "starfive,jhb100-adc0-pinctrl";
+ reg = <0x0 0x11bc2800 0x0 0x400>;
+ clocks = <&per2crg 67>;
+ resets = <&per2crg 10>,
+ <&per2crg 11>;
+ interrupts = <147>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_adc0 0 0 8>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v1 2/8] pinctrl: starfive: Add StarFive JHB100 adc0 controller driver
2026-10-17 5:25 [PATCH v1 0/8] Add ADC, eMMC and VGA pinctrl for StarFive JHB100 SoC Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 1/8] dt-bindings: pinctrl: Add starfive,jhb100-adc0-pinctrl Changhuang Liang
@ 2026-10-17 5:25 ` Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 3/8] dt-bindings: pinctrl: Add starfive,jhb100-adc1-pinctrl Changhuang Liang
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Changhuang Liang @ 2026-10-17 5:25 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Arnd Bergmann, Bartosz Golaszewski, linux-gpio, linux-kernel,
devicetree, Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC ADC-0(adc0) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-adc0.c | 85 +++++++++++++++++++
3 files changed, 97 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-adc0.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 7ff506a15dd8..1622cc73d9ae 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -54,6 +54,17 @@ config PINCTRL_STARFIVE_JHB100
select GPIOLIB
select GPIOLIB_IRQCHIP
+config PINCTRL_STARFIVE_JHB100_ADC0
+ tristate "StarFive JHB100 SoC ADC-0 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support ADC-0 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_PER0
tristate "StarFive JHB100 SoC Peripheral-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 351fce524fec..1113e73657d7 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_ADC0) += pinctrl-starfive-jhb100-adc0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-adc0.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-adc0.c
new file mode 100644
index 000000000000..8aaa4fca52e6
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-adc0.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC ADC-0 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_adc0_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 8, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_adc0_pinctrl_crl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 8,
+ .fields[PAD_CFG_DRIVE_STRENGTH_3BIT] = { .shift = 0, .width = 3 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 7, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct starfive_pinctrl_regs jhb100_adc0_pinctrl_regs = {
+ .func_sel = { .reg = 0x2c, .width_per_pin = 2 },
+ .config = 0x00,
+ .output = 0x20,
+ .output_en = 0x24,
+ .gpio_status = 0x28,
+ .irq_en = 0x30,
+ .irq_status = 0x34,
+ .irq_clr = 0x38,
+ .irq_trigger = 0x3c,
+ .irq_level = 0x40,
+ .irq_both_edge = 0x44,
+ .irq_edge = 0x48,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_adc0[] = {
+ { .func = "adc", .val = 1 },
+ { .func = "gpio", .val = 0 },
+ { .func = "host0_port80", .val = 3 },
+ { .func = "smbalert", .val = 2 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_adc0_pinctrl_info = {
+ .name = "jhb100-adc0",
+ .pl_desc = jhb100_adc0_pl_desc,
+ .crl_desc = jhb100_adc0_pinctrl_crl_desc,
+ .regs = &jhb100_adc0_pinctrl_regs,
+ .fmaps = jhb100_func_maps_adc0,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_adc0),
+};
+
+static const struct of_device_id jhb100_adc0_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-adc0-pinctrl",
+ .data = &jhb100_adc0_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_adc0_pinctrl_of_match);
+
+static struct platform_driver jhb100_adc0_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-adc0-pinctrl",
+ .of_match_table = jhb100_adc0_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_adc0_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC ADC-0 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v1 3/8] dt-bindings: pinctrl: Add starfive,jhb100-adc1-pinctrl
2026-10-17 5:25 [PATCH v1 0/8] Add ADC, eMMC and VGA pinctrl for StarFive JHB100 SoC Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 1/8] dt-bindings: pinctrl: Add starfive,jhb100-adc0-pinctrl Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 2/8] pinctrl: starfive: Add StarFive JHB100 adc0 controller driver Changhuang Liang
@ 2026-10-17 5:25 ` Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 4/8] pinctrl: starfive: Add StarFive JHB100 adc1 controller driver Changhuang Liang
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Changhuang Liang @ 2026-10-17 5:25 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Arnd Bergmann, Bartosz Golaszewski, linux-gpio, linux-kernel,
devicetree, Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC ADC-1(adc1) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-adc1-pinctrl.yaml | 168 ++++++++++++++++++
1 file changed, 168 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc1-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc1-pinctrl.yaml
new file mode 100644
index 000000000000..6f1486b4a8bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc1-pinctrl.yaml
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-adc1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 ADC-1 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "adc1" pinctrl domain.
+
+ The "adc1" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the ADC-1 Pin Controller, there are 8 multi-function GPIO_PADs. Each of
+ them can be multiplexed to several peripherals through function selection.
+ Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3. Function 0
+ is the default function which is generally the GPIO function. Function 1,
+ 2, and 3 are the alternate functions or peripheral signals that can be
+ routed to an iopad. The function selection can be carried out by writing
+ the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-adc1-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: ADC1 IOMUX
+ - description: ADC1 core
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce and
+ drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ adc, gpio, host1_port80, scap_trigger ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 5, 8, 10, 14, 16, 18, 20 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 5000, 8000, 10000, 14000, 16000, 18000, 20000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_adc1: pinctrl@11bc2c00 {
+ compatible = "starfive,jhb100-adc1-pinctrl";
+ reg = <0x0 0x11bc2c00 0x0 0x400>;
+ clocks = <&per2crg 68>;
+ resets = <&per2crg 12>,
+ <&per2crg 13>;
+ interrupts = <148>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_adc1 0 0 8>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v1 4/8] pinctrl: starfive: Add StarFive JHB100 adc1 controller driver
2026-10-17 5:25 [PATCH v1 0/8] Add ADC, eMMC and VGA pinctrl for StarFive JHB100 SoC Changhuang Liang
` (2 preceding siblings ...)
2026-10-17 5:25 ` [PATCH v1 3/8] dt-bindings: pinctrl: Add starfive,jhb100-adc1-pinctrl Changhuang Liang
@ 2026-10-17 5:25 ` Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 5/8] dt-bindings: pinctrl: Add starfive,jhb100-emmc-pinctrl Changhuang Liang
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Changhuang Liang @ 2026-10-17 5:25 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Arnd Bergmann, Bartosz Golaszewski, linux-gpio, linux-kernel,
devicetree, Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC ADC-1(adc1) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-adc1.c | 85 +++++++++++++++++++
3 files changed, 97 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-adc1.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 1622cc73d9ae..f869c474fc50 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -65,6 +65,17 @@ config PINCTRL_STARFIVE_JHB100_ADC0
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_ADC1
+ tristate "StarFive JHB100 SoC ADC-1 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support ADC-1 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_PER0
tristate "StarFive JHB100 SoC Peripheral-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 1113e73657d7..cc8ce1e67d4b 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_ADC0) += pinctrl-starfive-jhb100-adc0.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_ADC1) += pinctrl-starfive-jhb100-adc1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-adc1.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-adc1.c
new file mode 100644
index 000000000000..9264e9684b41
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-adc1.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC ADC-1 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_adc1_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 8, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_adc1_pinctrl_crl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 8,
+ .fields[PAD_CFG_DRIVE_STRENGTH_3BIT] = { .shift = 0, .width = 3 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 7, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct starfive_pinctrl_regs jhb100_adc1_pinctrl_regs = {
+ .func_sel = { .reg = 0x2c, .width_per_pin = 2 },
+ .config = 0x00,
+ .output = 0x20,
+ .output_en = 0x24,
+ .gpio_status = 0x28,
+ .irq_en = 0x30,
+ .irq_status = 0x34,
+ .irq_clr = 0x38,
+ .irq_trigger = 0x3c,
+ .irq_level = 0x40,
+ .irq_both_edge = 0x44,
+ .irq_edge = 0x48,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_adc1[] = {
+ { .func = "adc", .val = 1 },
+ { .func = "gpio", .val = 0 },
+ { .func = "host1_port80", .val = 2 },
+ { .func = "scap_trigger", .val = 3 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_adc1_pinctrl_info = {
+ .name = "jhb100-adc1",
+ .pl_desc = jhb100_adc1_pl_desc,
+ .crl_desc = jhb100_adc1_pinctrl_crl_desc,
+ .regs = &jhb100_adc1_pinctrl_regs,
+ .fmaps = jhb100_func_maps_adc1,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_adc1),
+};
+
+static const struct of_device_id jhb100_adc1_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-adc1-pinctrl",
+ .data = &jhb100_adc1_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_adc1_pinctrl_of_match);
+
+static struct platform_driver jhb100_adc1_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-adc1-pinctrl",
+ .of_match_table = jhb100_adc1_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_adc1_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC ADC-1 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v1 5/8] dt-bindings: pinctrl: Add starfive,jhb100-emmc-pinctrl
2026-10-17 5:25 [PATCH v1 0/8] Add ADC, eMMC and VGA pinctrl for StarFive JHB100 SoC Changhuang Liang
` (3 preceding siblings ...)
2026-10-17 5:25 ` [PATCH v1 4/8] pinctrl: starfive: Add StarFive JHB100 adc1 controller driver Changhuang Liang
@ 2026-10-17 5:25 ` Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 6/8] pinctrl: starfive: Add StarFive JHB100 emmc controller driver Changhuang Liang
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Changhuang Liang @ 2026-10-17 5:25 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Arnd Bergmann, Bartosz Golaszewski, linux-gpio, linux-kernel,
devicetree, Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC eMMC(emmc) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-emmc-pinctrl.yaml | 129 ++++++++++++++++++
1 file changed, 129 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-emmc-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-emmc-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-emmc-pinctrl.yaml
new file mode 100644
index 000000000000..4533209d9965
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-emmc-pinctrl.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-emmc-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 eMMC Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "emmc" pinctrl domain.
+
+ The "emmc" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the eMMC Pin Controller, there are 12 multi-function GPIO_PADs. Each of
+ them can be multiplexed to several peripherals through function selection.
+ Each iopad has a maximum of up to 2 functions - 0 and 1. Function 0
+ is the default function which is generally the GPIO function. Function 1
+ is the alternate functions or peripheral signals that can be routed to an
+ iopad. The function selection can be carried out by writing the function
+ number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input debounce
+ nanoseconds.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-emmc-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection and input debounce.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ emmc, gpio ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_emmc: pinctrl@11b42800 {
+ compatible = "starfive,jhb100-emmc-pinctrl";
+ reg = <0x0 0x11b42800 0x0 0x800>;
+ interrupts = <119>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_emmc 0 0 12>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v1 6/8] pinctrl: starfive: Add StarFive JHB100 emmc controller driver
2026-10-17 5:25 [PATCH v1 0/8] Add ADC, eMMC and VGA pinctrl for StarFive JHB100 SoC Changhuang Liang
` (4 preceding siblings ...)
2026-10-17 5:25 ` [PATCH v1 5/8] dt-bindings: pinctrl: Add starfive,jhb100-emmc-pinctrl Changhuang Liang
@ 2026-10-17 5:25 ` Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 7/8] dt-bindings: pinctrl: Add starfive,jhb100-vga-pinctrl Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 8/8] pinctrl: starfive: Add StarFive JHB100 vga controller driver Changhuang Liang
7 siblings, 0 replies; 9+ messages in thread
From: Changhuang Liang @ 2026-10-17 5:25 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Arnd Bergmann, Bartosz Golaszewski, linux-gpio, linux-kernel,
devicetree, Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC eMMC(emmc) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-emmc.c | 77 +++++++++++++++++++
3 files changed, 89 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-emmc.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index f869c474fc50..76f2d59e8a8d 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -76,6 +76,17 @@ config PINCTRL_STARFIVE_JHB100_ADC1
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_EMMC
+ tristate "StarFive JHB100 SoC eMMC pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support eMMC pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, input debounce and interrupts
+ on input changes.
+
config PINCTRL_STARFIVE_JHB100_PER0
tristate "StarFive JHB100 SoC Peripheral-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index cc8ce1e67d4b..d570b192b260 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_ADC0) += pinctrl-starfive-jhb100-adc0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_ADC1) += pinctrl-starfive-jhb100-adc1.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_EMMC) += pinctrl-starfive-jhb100-emmc.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-emmc.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-emmc.c
new file mode 100644
index 000000000000..32f8c141133b
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-emmc.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC eMMC domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_emmc_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 12, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_emmc_pinctrl_crl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 12,
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 0, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct starfive_pinctrl_regs jhb100_emmc_pinctrl_regs = {
+ .func_sel = { .reg = 0x3c, .width_per_pin = 2 },
+ .config = 0x00,
+ .output = 0x30,
+ .output_en = 0x34,
+ .gpio_status = 0x38,
+ .irq_en = 0x40,
+ .irq_status = 0x44,
+ .irq_clr = 0x48,
+ .irq_trigger = 0x4c,
+ .irq_level = 0x50,
+ .irq_both_edge = 0x54,
+ .irq_edge = 0x58,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_emmc[] = {
+ { .func = "emmc", .val = 1 },
+ { .func = "gpio", .val = 0 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_emmc_pinctrl_info = {
+ .name = "jhb100-emmc",
+ .pl_desc = jhb100_emmc_pl_desc,
+ .crl_desc = jhb100_emmc_pinctrl_crl_desc,
+ .regs = &jhb100_emmc_pinctrl_regs,
+ .fmaps = jhb100_func_maps_emmc,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_emmc),
+};
+
+static const struct of_device_id jhb100_emmc_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-emmc-pinctrl",
+ .data = &jhb100_emmc_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_emmc_pinctrl_of_match);
+
+static struct platform_driver jhb100_emmc_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-emmc-pinctrl",
+ .of_match_table = jhb100_emmc_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_emmc_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC eMMC domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v1 7/8] dt-bindings: pinctrl: Add starfive,jhb100-vga-pinctrl
2026-10-17 5:25 [PATCH v1 0/8] Add ADC, eMMC and VGA pinctrl for StarFive JHB100 SoC Changhuang Liang
` (5 preceding siblings ...)
2026-10-17 5:25 ` [PATCH v1 6/8] pinctrl: starfive: Add StarFive JHB100 emmc controller driver Changhuang Liang
@ 2026-10-17 5:25 ` Changhuang Liang
2026-10-17 5:25 ` [PATCH v1 8/8] pinctrl: starfive: Add StarFive JHB100 vga controller driver Changhuang Liang
7 siblings, 0 replies; 9+ messages in thread
From: Changhuang Liang @ 2026-10-17 5:25 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Arnd Bergmann, Bartosz Golaszewski, linux-gpio, linux-kernel,
devicetree, Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC VGA(vga) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-vga-pinctrl.yaml | 163 ++++++++++++++++++
1 file changed, 163 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-vga-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-vga-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-vga-pinctrl.yaml
new file mode 100644
index 000000000000..f0e35da58eab
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-vga-pinctrl.yaml
@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-vga-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 VGA Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "vga" pinctrl domain.
+
+ The "vga" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the VGA Pin Controller, there are 4 multi-function GPIO_PADs. Each of
+ them can be multiplexed to several peripherals through function selection.
+ Each iopad has a maximum of up to 2 functions - 0 and 1. Function 1
+ is the default function which is generally the GPIO function. Function 0
+ is the alternate functions or peripheral signals that can be routed to an
+ iopad. The function selection can be carried out by writing the function
+ number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-vga-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce and
+ drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ gpio, vga ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 5, 8, 10, 14, 16, 18, 20 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 5000, 8000, 10000, 14000, 16000, 18000, 20000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_vga: pinctrl@11136100 {
+ compatible = "starfive,jhb100-vga-pinctrl";
+ reg = <0x0 0x11136100 0x0 0x100>;
+ resets = <&voutcrg 14>;
+ interrupts = <236>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_vga 0 0 4>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v1 8/8] pinctrl: starfive: Add StarFive JHB100 vga controller driver
2026-10-17 5:25 [PATCH v1 0/8] Add ADC, eMMC and VGA pinctrl for StarFive JHB100 SoC Changhuang Liang
` (6 preceding siblings ...)
2026-10-17 5:25 ` [PATCH v1 7/8] dt-bindings: pinctrl: Add starfive,jhb100-vga-pinctrl Changhuang Liang
@ 2026-10-17 5:25 ` Changhuang Liang
7 siblings, 0 replies; 9+ messages in thread
From: Changhuang Liang @ 2026-10-17 5:25 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Arnd Bergmann, Bartosz Golaszewski, linux-gpio, linux-kernel,
devicetree, Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC VGA(vga) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-vga.c | 86 +++++++++++++++++++
3 files changed, 98 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-vga.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 76f2d59e8a8d..5b10b0a22078 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -185,3 +185,14 @@ config PINCTRL_STARFIVE_JHB100_SYS2
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JHB100_VGA
+ tristate "StarFive JHB100 SoC VGA pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support VGA pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index d570b192b260..170b24a7f29f 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS2) += pinctrl-starfive-jhb100-sys2.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_VGA) += pinctrl-starfive-jhb100-vga.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-vga.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-vga.c
new file mode 100644
index 000000000000..8cdabd91016f
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-vga.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC VGA domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_vga_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 1, .name = "hsync", .gpio_func_sel = 1 },
+ { .pin_start = 1, .pin_cnt = 1, .name = "vsync", .gpio_func_sel = 1 },
+ { .pin_start = 2, .pin_cnt = 1, .name = "ddcclk", .gpio_func_sel = 1 },
+ { .pin_start = 3, .pin_cnt = 1, .name = "ddcdat", .gpio_func_sel = 1 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_vga_pinctrl_crl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 4,
+ .fields[PAD_CFG_DRIVE_STRENGTH_3BIT] = { .shift = 0, .width = 3 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 7, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct starfive_pinctrl_regs jhb100_vga_pinctrl_regs = {
+ .func_sel = { .reg = 0x1c, .width_per_pin = 2 },
+ .config = 0x00,
+ .output = 0x10,
+ .output_en = 0x14,
+ .gpio_status = 0x18,
+ .irq_en = 0x20,
+ .irq_status = 0x24,
+ .irq_clr = 0x28,
+ .irq_trigger = 0x2c,
+ .irq_level = 0x30,
+ .irq_both_edge = 0x34,
+ .irq_edge = 0x38,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_vga[] = {
+ { .func = "gpio", .val = 1 },
+ { .func = "vga", .val = 0 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_vga_pinctrl_info = {
+ .name = "jhb100-vga",
+ .pl_desc = jhb100_vga_pl_desc,
+ .crl_desc = jhb100_vga_pinctrl_crl_desc,
+ .regs = &jhb100_vga_pinctrl_regs,
+ .fmaps = jhb100_func_maps_vga,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_vga),
+};
+
+static const struct of_device_id jhb100_vga_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-vga-pinctrl",
+ .data = &jhb100_vga_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_vga_pinctrl_of_match);
+
+static struct platform_driver jhb100_vga_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-vga-pinctrl",
+ .of_match_table = jhb100_vga_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_vga_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC VGA domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread