[PATCH 0/2] arm64: dts: freescale: Re-enable A72 cluster on i.MX8QM boards

[PATCH 0/2] arm64: dts: freescale: Re-enable A72 cluster on i.MX8QM boards

[Peng Fan (OSS)]

The ERR050104 cache coherency workaround for the NXP i.MX8QuadMax and
i.MX8QuadPlus SoCs has been merged upstream as commit d44e08dab27d
("arm64: errata: Add NXP i.MX8QM/8QP workaround for A53 cache coherency
issue").

The workaround addresses a hardware defect where the upper address bits
of the ARADDR and ACADDR buses within the Cortex-A53 subsystem were
incorrectly connected, causing TLBI and IC maintenance operations
exchanged between the A53 and A72 clusters to be corrupted.

Before the software workaround was available, affected board DTS files
worked around this issue at the DT level by removing the Cortex-A72 CPU
nodes (cpu@100, cpu@101), the cpu-map topology, and associated thermal
zones, effectively running the SoC as a single A53-only cluster.

With the kernel-side fix in place, these DT-level workarounds could be
dropped.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Peng Fan (2):
      arm64: dts: imx8qm-mek: Re-enable A72 cluster after ERR050104 workaround
      arm64: dts: imx8qm-tqma8qm: Re-enable A72 cluster after ERR050104 workaround

 arch/arm64/boot/dts/freescale/imx8qm-mek.dts      | 10 ----------
 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi |  7 -------
 2 files changed, 17 deletions(-)
---
base-commit: 4403278e4ea2f654f8130a5c03eb8b4516a0f201
change-id: 20261022-8qm-875d0b4b3e7d

Best regards,
--  
Peng Fan <peng.fan@nxp.com>

[PATCH 1/2] arm64: dts: imx8qm-mek: Re-enable A72 cluster after ERR050104 workaround

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

The ERR050104 cache coherency workaround for i.MX8QM/8QP has been
merged upstream (d44e08dab27d). The workaround addresses the incorrect
wiring of upper address bits in the A53 subsystem that corrupts TLBI and
IC maintenance operations between A53 and A72 clusters.

Previously the A72 CPUs (cpu@100, cpu@101), the cpu-map, and the
cpu1-thermal zone were removed from the MEK board DT to avoid incorrect
cross-cluster coherency maintenance. With the software workaround in place,
restore all deleted nodes.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 9e49ac377162b..af212fa194cf7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -17,16 +17,6 @@ chosen {
 		stdout-path = &lpuart0;
 	};
 
-	cpus {
-		/delete-node/ cpu-map;
-		/delete-node/ cpu@100;
-		/delete-node/ cpu@101;
-	};
-
-	thermal-zones {
-		/delete-node/ cpu1-thermal;
-	};
-
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x00000000 0x80000000 0 0x40000000>;

-- 
2.34.1

[PATCH 2/2] arm64: dts: imx8qm-tqma8qm: Re-enable A72 cluster after ERR050104 workaround

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

The ERR050104 cache coherency workaround for i.MX8QM/8QP has been
merged upstream (d44e08dab27d). The workaround addresses the incorrect
wiring of upper address bits in the A53 subsystem that corrupts TLBI and
IC maintenance operations between A53 and A72 clusters.

Previously the A72 CPUs (cpu@100, cpu@101) and cpu-map were removed
from the TQMa8QM DTSI with an explicit comment "Due to missing
workaround for ERR050104". With the software workaround is in place,
remove the workaround-comment block and restore the full SMP topology.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
index f0e398eb2aad7..8cd6e75eb87a9 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
@@ -15,13 +15,6 @@ / {
 	model = "TQ-Systems i.MX8QM TQMa8QM";
 	compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm";
 
-	/* Due to missing workaround for ERR050104 */
-	cpus {
-		/delete-node/ cpu-map;
-		/delete-node/ cpu@100;
-		/delete-node/ cpu@101;
-	};
-
 	memory@80000000 {
 		device_type = "memory";
 		/*

-- 
2.34.1

Re: [PATCH 2/2] arm64: dts: imx8qm-tqma8qm: Re-enable A72 cluster after ERR050104 workaround

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] arm64: dts: imx8qm-tqma8qm: missing cpu1-thermal restore for A72 cluster
--

commit 187cd9d157965a8b6ed40b9b4b40d998a0f0385a
Author: Peng Fan <peng.fan@nxp.com>

arm64: dts: imx8qm-tqma8qm: Re-enable A72 cluster after ERR050104 workaround

This commit removes the /delete-node/ directives for cpu-map, cpu@100, and
cpu@101 in imx8qm-tqma8qm.dtsi to re-enable the Cortex-A72 cluster now that
the ERR050104 workaround has been merged.

> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
> index f0e398eb2aad7..8cd6e75eb87a9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
> @@ -15,13 +15,6 @@ / {
>  	model = "TQ-Systems i.MX8QM TQMa8QM";
>  	compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm";
>  
> -	/* Due to missing workaround for ERR050104 */
> -	cpus {
> -		/delete-node/ cpu-map;
> -		/delete-node/ cpu@100;
> -		/delete-node/ cpu@101;
> -	};
> -

[Severity: High]
When commit 5d20f1ccb3393a ("arm64: dts: imx8qm-tqma8qm-mba8x: Disable
Cortex-A72 cluster") disabled cpu@100 and cpu@101 due to the missing
ERR050104 workaround, it also removed the thermal management configuration
for the Cortex-A72 cluster.

In arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi, thermal_zones still
deletes cpu1-thermal and omits A72_0 and A72_1 from the pmic0-thermal
cooling-maps:

&thermal_zones {
	/delete-node/ cpu1-thermal;

	pmic0-thermal {
		...
		cooling-maps {
			map0 {
				trip = <&pmic_alert0>;
				cooling-device =
					<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};

Deleting cpu1-thermal also leaves the cpu_alert1 and cpu_crit1 trip point
overrides in arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi unused:

&cpu_alert1 {
	temperature = <95000>;
};

&cpu_crit1 {
	temperature = <100000>;
};

In addition, commit 5d20f1ccb3393a removed the cpu1-thermal active trip
points and fan0 cooling-maps from thermal-zones in
arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts.

Unlike companion commit 72b6162dd6e2 ("arm64: dts: imx8qm-mek: Re-enable A72
cluster after ERR050104 workaround"), which removed /delete-node/
cpu1-thermal alongside the /cpus deletions, booting a board using
imx8qm-tqma8qm.dtsi (such as imx8qm-tqma8qm-mba8x.dts) with this change
brings cpu@100 and cpu@101 online without cpu1-thermal (monitoring
IMX_SC_R_A72), leaving the A72 cluster without passive cpufreq throttling at
95 C, thermal shutdown at 100 C, pmic0-thermal alert throttling, or active
fan cooling under sustained load.

Should commit 5d20f1ccb3393a be reverted completely so that cpu1-thermal and
the A72 cooling maps are restored together with the Cortex-A72 CPU nodes?

>  	memory@80000000 {
>  		device_type = "memory";
>  		/*

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261022-8qm-v1-0-2a597cb3debd@nxp.com?part=2

Re: [PATCH 2/2] arm64: dts: imx8qm-tqma8qm: Re-enable A72 cluster after ERR050104 workaround

[Alexander Stein]

Hi Peng,

thanks for the patch.

Am Donnerstag, 22. Oktober 2026, 03:50:02 Mitteleuropäische Sommerzeit schrieb Peng Fan (OSS):
> From: Peng Fan <peng.fan@nxp.com>
> 
> The ERR050104 cache coherency workaround for i.MX8QM/8QP has been
> merged upstream (d44e08dab27d). The workaround addresses the incorrect
> wiring of upper address bits in the A53 subsystem that corrupts TLBI and
> IC maintenance operations between A53 and A72 clusters.
> 
> Previously the A72 CPUs (cpu@100, cpu@101) and cpu-map were removed
> from the TQMa8QM DTSI with an explicit comment "Due to missing
> workaround for ERR050104". With the software workaround is in place,
> remove the workaround-comment block and restore the full SMP topology.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi | 7 -------
>  1 file changed, 7 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
> index f0e398eb2aad7..8cd6e75eb87a9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi
> @@ -15,13 +15,6 @@ / {
>  	model = "TQ-Systems i.MX8QM TQMa8QM";
>  	compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm";
>  
> -	/* Due to missing workaround for ERR050104 */
> -	cpus {
> -		/delete-node/ cpu-map;
> -		/delete-node/ cpu@100;
> -		/delete-node/ cpu@101;
> -	};
> -

While the patch itself is correct, it is not sufficient. Instead please
revert commit 5d20f1ccb3393 ("arm64: dts: imx8qm-tqma8qm-mba8x: Disable
Cortex-A72 cluster"). This will restore the thermal zone for cpu1-cluster.
This commit was created with the intention to be reverted, once the
errata has been dealt with.
With the revert:
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Thanks and best regards,
Alexander

>  	memory@80000000 {
>  		device_type = "memory";
>  		/*
> 
> 


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