[PATCH v2 0/4] clk: qcom: Add SM8350 camera clock controller

[Vladimir Zapolskiy <vz@kernel.org>]

Add the camera clock controller (CAMCC) for Qualcomm SM8350 SoC, the
clock configuration was taken from camcc-lahaina.c from msm-5.10.

CAM_CC_PLL0 runs at 1200MHz, which requires the SVS_L1 level of the MX
rail, so it is set as the MX performance state in the device tree node.

Changes from v1 to v2:
* removed linux/mod_devicetable.h explicit include per ask (Uwe),
* PLL2 AUX2 input cannot be used in a meaningful way, removed it (Sashiko bot),
* Lucid 5LPE PLLs should not fallback to Trion configuration (Sashiko bot).

Link to v1:
* https://lore.kernel.org/all/20261104001704.2744766-1-vz@kernel.org/

Vladimir Zapolskiy (4):
  dt-bindings: clock: qcom: Add SM8350 camera clock controller
  clk: qcom: clk-alpha-pll: Add Lucid 5LPE PLL type
  clk: qcom: Add SM8350 camera clock controller driver
  arm64: dts: qcom: sm8350: Add camera clock controller

 .../bindings/clock/qcom,sm8350-camcc.yaml     |   69 +
 arch/arm64/boot/dts/qcom/sm8350.dtsi          |   15 +
 drivers/clk/qcom/Kconfig                      |    9 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/camcc-sm8350.c               | 2646 +++++++++++++++++
 drivers/clk/qcom/clk-alpha-pll.c              |   19 +
 drivers/clk/qcom/clk-alpha-pll.h              |    1 +
 include/dt-bindings/clock/qcom,sm8350-camcc.h |  149 +
 8 files changed, 2909 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8350-camcc.yaml
 create mode 100644 drivers/clk/qcom/camcc-sm8350.c
 create mode 100644 include/dt-bindings/clock/qcom,sm8350-camcc.h

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2.51.0