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From: Vladimir Zapolskiy <vz@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>,
	Abel Vesa <abelvesa@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>
Cc: "Stephen Boyd" <sboyd@kernel.org>,
	"Brian Masney" <bmasney+clk@redhat.com>,
	"Jerome Brunet" <jbrunet+clk@baylibre.com>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Uwe Kleine-König" <u.kleine-koenig@baylibre.com>,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: [PATCH v2 2/4] clk: qcom: clk-alpha-pll: Add Lucid 5LPE PLL type
Date: Sat,  7 Nov 2026 19:36:19 +0200	[thread overview]
Message-ID: <20261107173621.3538964-3-vz@kernel.org> (raw)
In-Reply-To: <20261107173621.3538964-1-vz@kernel.org>

Lucid 5LPE PLLs have the same register layout as Trion and Lucid PLLs,
but the bitfields are not identical, for instance PLL_UPDATE_BYPASS bit
is not present, and the PLL configuration should be done by calling its
own separate clk_lucid_5lpe_pll_configure() function.

Add a separate Lucid 5LPE PLL type to select the proper PLL configuration
function in qcom_clk_alpha_pll_configure().

Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 19 +++++++++++++++++++
 drivers/clk/qcom/clk-alpha-pll.h |  1 +
 2 files changed, 20 insertions(+)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 60173b076cc5..3062b86f07f6 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -147,6 +147,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_OPMODE] = 0x38,
 		[PLL_OFF_ALPHA_VAL] = 0x40,
 	},
+	[CLK_ALPHA_PLL_TYPE_LUCID_5LPE] = {
+		[PLL_OFF_L_VAL] = 0x04,
+		[PLL_OFF_CAL_L_VAL] = 0x08,
+		[PLL_OFF_USER_CTL] = 0x0c,
+		[PLL_OFF_USER_CTL_U] = 0x10,
+		[PLL_OFF_USER_CTL_U1] = 0x14,
+		[PLL_OFF_CONFIG_CTL] = 0x18,
+		[PLL_OFF_CONFIG_CTL_U] = 0x1c,
+		[PLL_OFF_CONFIG_CTL_U1] = 0x20,
+		[PLL_OFF_TEST_CTL] = 0x24,
+		[PLL_OFF_TEST_CTL_U] = 0x28,
+		[PLL_OFF_TEST_CTL_U1] = 0x2c,
+		[PLL_OFF_STATUS] = 0x30,
+		[PLL_OFF_OPMODE] = 0x38,
+		[PLL_OFF_ALPHA_VAL] = 0x40,
+	},
 	[CLK_ALPHA_PLL_TYPE_AGERA] = {
 		[PLL_OFF_L_VAL] = 0x04,
 		[PLL_OFF_ALPHA_VAL] = 0x08,
@@ -3025,6 +3041,9 @@ void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regm
 	case CLK_ALPHA_PLL_TYPE_TRION:
 		clk_trion_pll_configure(pll, regmap, pll->config);
 		break;
+	case CLK_ALPHA_PLL_TYPE_LUCID_5LPE:
+		clk_lucid_5lpe_pll_configure(pll, regmap, pll->config);
+		break;
 	case CLK_ALPHA_PLL_TYPE_HUAYRA_2290:
 		clk_huayra_2290_pll_configure(pll, regmap, pll->config);
 		break;
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 3a2157bebc52..3c26ea917f52 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -21,6 +21,7 @@ enum {
 	CLK_ALPHA_PLL_TYPE_FABIA,
 	CLK_ALPHA_PLL_TYPE_TRION,
 	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
+	CLK_ALPHA_PLL_TYPE_LUCID_5LPE,
 	CLK_ALPHA_PLL_TYPE_AGERA,
 	CLK_ALPHA_PLL_TYPE_ZONDA,
 	CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA,
-- 
2.51.0


  parent reply	other threads:[~2026-11-07 17:37 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-07 17:36 [PATCH v2 0/4] clk: qcom: Add SM8350 camera clock controller Vladimir Zapolskiy
2026-11-07 17:36 ` [PATCH v2 1/4] dt-bindings: clock: " Vladimir Zapolskiy
2026-11-09 12:44   ` Krzysztof Kozlowski
2026-11-07 17:36 ` Vladimir Zapolskiy [this message]
2026-11-09 15:09   ` [PATCH v2 2/4] clk: qcom: clk-alpha-pll: Add Lucid 5LPE PLL type Konrad Dybcio
2026-11-10  9:36   ` Abel Vesa
2026-11-07 17:36 ` [PATCH v2 3/4] clk: qcom: Add SM8350 camera clock controller driver Vladimir Zapolskiy
2026-11-10  9:40   ` Abel Vesa
2026-11-07 17:36 ` [PATCH v2 4/4] arm64: dts: qcom: sm8350: Add camera clock controller Vladimir Zapolskiy
2026-11-09 12:45   ` Krzysztof Kozlowski

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