From: Conor Dooley <conor@kernel.org>
To: Joel Stanley <joel@jms.id.au>
Cc: Paul Walmsley <pjw@kernel.org>, Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>, Alexandre Ghiti <alex@ghiti.fr>,
Thomas Gleixner <tglx@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Nicholas Piggin <npiggin@gmail.com>,
Michael Ellerman <mpe@kernel.org>,
Drew Fustini <fustini@kernel.org>,
Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings
Date: Mon, 9 Nov 2026 19:29:42 +0000 [thread overview]
Message-ID: <20261109-jester-zestfully-a664203cfbd1@spud> (raw)
In-Reply-To: <20261109051050.105623-5-joel@jms.id.au>
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On Mon, Nov 09, 2026 at 03:40:44PM +1030, Joel Stanley wrote:
> Document the RISC-V ACLINT mtimer and mtimecmp hardware, as described
> by the riscv-aclint specification, commit 4e570bfd3201f2 [2].
>
> Multiple vendors are shipping silicon with the hardware as described
> by the specification, which was abandoned[1] as a standalone spec at
> v1.0-rc4. As we have multiple instances of hardware that implement
> the spec, the widespread implementation of the spec is de facto
> ratification, providing a stationary target for the bindings to document
> and an exception to the policy of not accepting things that are
> pre-ratification.
>
> [1] https://lists.riscv.org/g/tech-aia/topic/connections_between_aia_and/107177435
> [2] https://github.com/riscvarchive/riscv-aclint/blob/4e570bfd3201f2c09e5afd290b5091526b0f099a/riscv-aclint.adoc
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> v3:
> - Rework commit message following discussion at LPC
Since I was one of the folks involved in that chat, I am okay with this
obviously. I was convinced to change my mind about the use of the riscv
vendor prefix because of the widespread adoption.
> - Add reg-names, rework description, fix example
> ---
> MAINTAINERS | 1 +
> .../bindings/timer/riscv,aclint-mtimer.yaml | 56 +++++++++++++++++++
> 2 files changed, 57 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 93abbb315065..403875d5932e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -24185,6 +24185,7 @@ S: Maintained
> T: git git://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git
> F: Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
> F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
> +F: Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> F: arch/riscv/boot/dts/tenstorrent/
> F: drivers/clk/tenstorrent/
> F: drivers/reset/reset-tenstorrent-atlantis.c
> diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> new file mode 100644
> index 000000000000..e6f3d08d4f93
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V Advanced Core Local Interruptor (ACLINT) timer
> +
> +maintainers:
> + - Joel Stanley <jms@oss.tenstorrent.com>
> +
> +description:
> + The RISC-V ACLINT specification defines a set of memory mapped devices which
> + provide timer functionality for each hart on a multi-hart RISC-V platform.
> + The mtimer device has a single mtime register and one mtimecmp register per
> + hart. The specification is at https://github.com/riscvarchive/riscv-aclint/
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - tenstorrent,atlantis-aclint-mtimer
> + - const: riscv,aclint-mtimer
So, what are we doing about thead,c900-aclint-mtimer.yaml?
> +
> + reg:
> + items:
> + - description: mtime register
> + - description: mtimecmp registers
For example, I note that you have mtime and mtimecmp in the opposite
order to how the mips folks have had to add the mtime region to that
file:
https://lore.kernel.org/all/20261103-p8700-dts-v2-6-3ac5d49f2c37@htecgroup.com/
> +
> + reg-names:
> + items:
> + - const: mtime
> + - const: mtimecmp
> +
> + interrupts-extended:
> + minItems: 1
> + maxItems: 4095
> +
> +required:
> + - compatible
> + - reg
You've also not made reg-names or interrupts-extended required.
I think we should swap the regs around and make these two required at a
minimum, but also "initialise" this file by renaming the existing file.
My ~assumption~hope is that all of the devices in that file have
implemented the aclint spec at the -rc1 revision that we're citing here.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + timer@a2180000 {
> + compatible = "tenstorrent,atlantis-aclint-mtimer", "riscv,aclint-mtimer";
> + reg = <0xa2180000 0x8000>, <0xa2188000 0x8000>;
> + reg-names = "mtime", "mtimecmp";
> + interrupts-extended = <&cpu1intc 7>,
> + <&cpu2intc 7>,
> + <&cpu3intc 7>,
> + <&cpu4intc 7>;
> + };
> +...
> --
> 2.47.3
>
>
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next prev parent reply other threads:[~2026-11-09 19:29 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-09 5:10 [PATCH v3 0/7] riscv: dts: tenstorrent: Add Atlantis platform Joel Stanley
2026-11-09 5:10 ` [PATCH v3 1/7] dt-bindings: aplic: Add Tenstorrent Atlantis compatible Joel Stanley
2026-11-09 19:30 ` Conor Dooley
2026-11-09 5:10 ` [PATCH v3 2/7] dt-bindings: imsics: " Joel Stanley
2026-11-09 5:10 ` [PATCH v3 3/7] dt-bindings: riscv: cpus: Add Tenstorrent Ascalon Joel Stanley
2026-11-09 5:10 ` [PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings Joel Stanley
2026-11-09 12:37 ` Krzysztof Kozlowski
2026-11-09 19:29 ` Conor Dooley [this message]
2026-11-11 5:04 ` Joel Stanley
2026-11-11 6:21 ` Inochi Amaoto
2026-11-11 10:17 ` Conor Dooley
2026-11-12 15:44 ` Aleksa Paunovic
2026-11-12 17:48 ` Conor Dooley
2026-11-12 16:50 ` Junhui Liu
2026-11-09 5:10 ` [PATCH v3 5/7] dt-bindings: riscv: add Smrnmi extension description Joel Stanley
2026-11-09 5:10 ` [PATCH v3 6/7] dt-bindings: riscv: Add Tenstorrent Atlantis platform Joel Stanley
2026-11-09 5:10 ` [PATCH v3 7/7] riscv: dts: tenstorrent: Add " Joel Stanley
2026-11-09 14:25 ` Anirudh Srinivasan
2026-11-10 19:31 ` Emil Renner Berthing
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