Devicetree
 help / color / mirror / Atom feed
From: "Junhui Liu" <junhui.liu@pigmoral.tech>
To: "Joel Stanley" <joel@jms.id.au>,
	"Conor Dooley" <conor@kernel.org>, <inochiama@gmail.com>,
	<junhui.liu@pigmoral.tech>, <aleksa.paunovic@htecgroup.com>,
	<chen.wang@linux.dev>, <dlan@kernel.org>, <guoren@kernel.org>
Cc: "Paul Walmsley" <pjw@kernel.org>, "Rob Herring" <robh@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Thomas Gleixner" <tglx@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Nicholas Piggin" <npiggin@gmail.com>,
	"Michael Ellerman" <mpe@kernel.org>,
	"Drew Fustini" <fustini@kernel.org>,
	"Anirudh Srinivasan" <asrinivasan@oss.tenstorrent.com>,
	<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings
Date: Fri, 13 Nov 2026 00:50:20 +0800	[thread overview]
Message-ID: <DMTDY3AW6KQF.17C2LVU6RHJOA@pigmoral.tech> (raw)
In-Reply-To: <CACPK8XcnPb9oMQq4YpNFG+RznroP-647E-_O5j84OW_YQ7P=9Q@mail.gmail.com>

Hi there,

On Wed Nov 11, 2026 at 1:04 PM CST, Joel Stanley wrote:
> +cc people who might know more about the various hardware this binding supports.
>
> On Tue, 10 Nov 2026 at 05:59, Conor Dooley <conor@kernel.org> wrote:
>> > +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
>
>> > +properties:
>> > +  compatible:
>> > +    items:
>> > +      - enum:
>> > +          - tenstorrent,atlantis-aclint-mtimer
>> > +      - const: riscv,aclint-mtimer
>>
>> So, what are we doing about thead,c900-aclint-mtimer.yaml?
>
> Once we agree on this binding, I planned to submit a change to bring
> over the devices that implement the common binding. I can do that up
> front instead.
>
>>
>> > +
>> > +  reg:
>> > +    items:
>> > +      - description: mtime register
>> > +      - description: mtimecmp registers
>>
>> For example, I note that you have mtime and mtimecmp in the opposite
>> order to how the mips folks have had to add the mtime region to that
>> file:
>> https://lore.kernel.org/all/20261103-p8700-dts-v2-6-3ac5d49f2c37@htecgroup.com/
>
> This is the order OpenSBI has used since v1.0, when support was added
> about five years ago. It reads mtime followed by mtimecmp when there
> are no reg-names:
>
>  https://github.com/riscv-software-src/opensbi/blob/v1.9/lib/utils/timer/fdt_timer_mtimer.c#L79
>
> QEMU also generates a dt with mtime followed by mtimecmp, and without reg-names.
>
> The MIPS ordering works because it specifies reg-names. OpenSBI uses
> reg-names to parse the reg property so it would continue working, but
> u-boot takes index 0 as mtime and ignores reg-names.
>
>> > +
>> > +  reg-names:
>> > +    items:
>> > +      - const: mtime
>> > +      - const: mtimecmp
>> > +
>> > +  interrupts-extended:
>> > +    minItems: 1
>> > +    maxItems: 4095
>> > +
>> > +required:
>> > +  - compatible
>> > +  - reg
>>
>> You've also not made reg-names or interrupts-extended required.
>
> That was intentional. A mtimer device without harts attached won't
> have interrupts (opensbi supports this), but I haven't come across a
> system that uses it this way. I have no preference here, what do you
> think?
>
>> I think we should swap the regs around and make these two required at a
>> minimum, but also "initialise" this file by renaming the existing file.
>
> Bringing over the other devices sounds like a good idea to me. And I
> appreciate the spelling.
>
> The nuclei/anlogic boards document mtime[1] support:
>
>  - nuclei,ux900-aclint-mtimer
>  - anlogic,dr1v90-aclint-mtimer

I've tested this on DR1V90 and confirmed that the value read from
0x6803cff8 (offset 0x7ff8 from the mtimer base at 0x68035000) tracks the
TIME CSR. This confirms that DR1V90 indeed has an mtime register at that
address.

I'll follow the discussion and update the DR1V90 DTS if needed.

Best regards,
Junhui Liu

>
> K3 has a mtime register (at 0xf181bff8, by experimentation on hardware):
>
>  - spacemit,k3-aclint-mtimer
>
> MIPS has it, as per their patch[2]:
>
>  - gf,mips-p8700-aclint-mtimer
>
> Note that MIPS have mips,p8700-aclint-mtimer in opensbi.
>
> T-Head has no mtime[3], just a set of mtimecmp registers. Sophgo are
> unknown, can we assume it is the same design as T-Head?
>
>  - thead,c900-aclint-mtimer
>  - sophgo,sg2042-aclint-mtimer
>  - sophgo,sg2044-aclint-mtimer
>
> There are two options for T-Head:
>
> 1) Leave it in its own binding, because it doesn't have mtime registers.
>
> 2) Use this binding with an optional reg property for the mtime
> region, which means putting the optional part last.
>
> If we go with 1 we can preserve the mtime, mtimecmp ordering, matching
> u-boot, opensbi, qemu. If we go with 2 we put mtime last and make
> reg-names required.
>
> The current K3 and Anlogic current device trees would need an update
> to their reg property to describe mtime when adding the riscv
> compatible.
>
> I lean towards 1 because it reduces churn in firmware.
>
>> My ~assumption~hope is that all of the devices in that file have
>> implemented the aclint spec at the -rc1 revision that we're citing here.
>
> (-rc4). Yep, we can move the majority of the compatibles into this
> binding. The T-Head family might be the exception.
>
> Cheers,
>
> Joel
>
> [1] https://doc.nucleisys.com/nuclei_spec/isa/timer.html
> [2] https://lore.kernel.org/all/20261103-p8700-dts-v2-6-3ac5d49f2c37@htecgroup.com/
> [3] https://lore.kernel.org/all/IA1PR20MB4953D36ABE26822B62415500BBBBA@IA1PR20MB4953.namprd20.prod.outlook.com/

  parent reply	other threads:[~2026-11-12 16:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-09  5:10 [PATCH v3 0/7] riscv: dts: tenstorrent: Add Atlantis platform Joel Stanley
2026-11-09  5:10 ` [PATCH v3 1/7] dt-bindings: aplic: Add Tenstorrent Atlantis compatible Joel Stanley
2026-11-09 19:30   ` Conor Dooley
2026-11-09  5:10 ` [PATCH v3 2/7] dt-bindings: imsics: " Joel Stanley
2026-11-09  5:10 ` [PATCH v3 3/7] dt-bindings: riscv: cpus: Add Tenstorrent Ascalon Joel Stanley
2026-11-09  5:10 ` [PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings Joel Stanley
2026-11-09 12:37   ` Krzysztof Kozlowski
2026-11-09 19:29   ` Conor Dooley
2026-11-11  5:04     ` Joel Stanley
2026-11-11  6:21       ` Inochi Amaoto
2026-11-11 10:17         ` Conor Dooley
2026-11-12 15:44           ` Aleksa Paunovic
2026-11-12 17:48             ` Conor Dooley
2026-11-12 16:50       ` Junhui Liu [this message]
2026-11-09  5:10 ` [PATCH v3 5/7] dt-bindings: riscv: add Smrnmi extension description Joel Stanley
2026-11-09  5:10 ` [PATCH v3 6/7] dt-bindings: riscv: Add Tenstorrent Atlantis platform Joel Stanley
2026-11-09  5:10 ` [PATCH v3 7/7] riscv: dts: tenstorrent: Add " Joel Stanley
2026-11-09 14:25   ` Anirudh Srinivasan
2026-11-10 19:31   ` Emil Renner Berthing

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=DMTDY3AW6KQF.17C2LVU6RHJOA@pigmoral.tech \
    --to=junhui.liu@pigmoral.tech \
    --cc=aleksa.paunovic@htecgroup.com \
    --cc=alex@ghiti.fr \
    --cc=anup@brainfault.org \
    --cc=asrinivasan@oss.tenstorrent.com \
    --cc=chen.wang@linux.dev \
    --cc=conor+dt@kernel.org \
    --cc=conor@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dlan@kernel.org \
    --cc=fustini@kernel.org \
    --cc=guoren@kernel.org \
    --cc=inochiama@gmail.com \
    --cc=joel@jms.id.au \
    --cc=krzk+dt@kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=mpe@kernel.org \
    --cc=npiggin@gmail.com \
    --cc=palmer@dabbelt.com \
    --cc=pjw@kernel.org \
    --cc=robh@kernel.org \
    --cc=tglx@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox