[PATCH 1/2] arm64: dts: imx94: add NETC switch node

[PATCH 1/2] arm64: dts: imx94: add NETC switch node

[wei.fang]

From: Wei Fang <wei.fang@nxp.com>

The NETC switch of i.MX94 has three user ports and one CPU port. The CPU
port connects to an internal ENETC (enetc3) through the pseudo link. The
"dsa,member" property is used to specify the switch index, which is
reflected in the switch tag as an indication of the switch ID where the
frame originated.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx94.dtsi | 41 ++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index 020aa1da3315..952dad5aa656 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -1521,6 +1521,47 @@ netc_timer0: ptp-timer@0,1 {
 					status = "disabled";
 				};
 
+				netc_switch: ethernet-switch@0,2 {
+					compatible = "pci1131,eef2";
+					reg = <0x200 0 0 0 0>;
+					dsa,member = <0 1>;
+					status = "disabled";
+
+					netc_switch_ports: ethernet-ports {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						netc_switch_port0: ethernet-port@0 {
+							reg = <0>;
+							status = "disabled";
+						};
+
+						netc_switch_port1: ethernet-port@1 {
+							reg = <1>;
+							status = "disabled";
+						};
+
+						netc_switch_port2: ethernet-port@2 {
+							reg = <2>;
+							status = "disabled";
+						};
+
+						/* CPU port, a.k.a switch management port */
+						netc_switch_port3: ethernet-port@3 {
+							reg = <3>;
+							ethernet = <&enetc3>;
+							phy-mode = "internal";
+							status = "disabled";
+
+							fixed-link {
+								speed = <2500>;
+								full-duplex;
+								pause;
+							};
+						};
+					};
+				};
+
 				rcec@1,0 {
 					reg = <0x800 0 0 0 0>;
 					interrupts = <1>;
-- 
2.34.1

[PATCH 2/2] arm64: dts: imx943-evk: enable NETC switch

[wei.fang]

From: Wei Fang <wei.fang@nxp.com>

Enable the NETC switch on the i.MX943-EVK board. Configure swp0 and swp1
ports for MII mode and swp2 for RGMII mode. Add the necessary clock
assignments, PHY nodes and pinmux settings.

Note that switch port 2 and enetc 0 share a parallel interface, and they
cannot be enabled at the same time. Therefore, only switch port 2 is
enabled in imx943-evk.dts.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx943-evk.dts | 101 ++++++++++++++++++-
 1 file changed, 99 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index 39e819c536cc..1c98948d2fe7 100644
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
@@ -790,11 +790,13 @@ &mu15 {
 };
 
 &netc_blk_ctrl {
-	assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>,
+	assigned-clocks = <&scmi_clk IMX94_CLK_MAC2>,
+			  <&scmi_clk IMX94_CLK_MAC4>,
 			  <&scmi_clk IMX94_CLK_MAC5>;
 	assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>,
+				 <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>,
 				 <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>;
-	assigned-clock-rates = <250000000>, <250000000>;
+	assigned-clock-rates = <250000000>, <250000000>, <250000000>;
 	status = "okay";
 };
 
@@ -803,6 +805,19 @@ &netc_emdio {
 	pinctrl-0 = <&pinctrl_emdio>;
 	status = "okay";
 
+	ethphy0: ethernet-phy@2 {
+		reg = <0x2>;
+	};
+
+	ethphy1: ethernet-phy@3 {
+		reg = <0x3>;
+	};
+
+	ethphy2: ethernet-phy@5 {
+		reg = <0x5>;
+		realtek,clkout-disable;
+	};
+
 	ethphy3: ethernet-phy@6 {
 		reg = <0x6>;
 		realtek,clkout-disable;
@@ -814,6 +829,39 @@ ethphy4: ethernet-phy@7 {
 	};
 };
 
+&netc_switch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_switch>;
+	status = "okay";
+};
+
+&netc_switch_port0 {
+	label = "swp0";
+	phy-handle = <&ethphy0>;
+	phy-mode = "mii";
+	status = "okay";
+};
+
+&netc_switch_port1 {
+	label = "swp1";
+	phy-handle = <&ethphy1>;
+	phy-mode = "mii";
+	status = "okay";
+};
+
+&netc_switch_port2 {
+	label = "swp2";
+	clocks = <&scmi_clk IMX94_CLK_MAC2>;
+	clock-names = "ref";
+	phy-handle = <&ethphy2>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
+&netc_switch_port3 {
+	status = "okay";
+};
+
 &netc_timer0 {
 	status = "okay";
 };
@@ -996,6 +1044,55 @@ IMX94_PAD_GPIO_IO47__SAI3_TX_DATA0	0x31e
 		>;
 	};
 
+	pinctrl_switch: switchgrp {
+		fsl,pins = <
+			IMX94_PAD_ETH0_RX_CLK__NETC_PINMUX_ETH0_RX_CLK		0x58e
+			IMX94_PAD_ETH0_RX_DV__NETC_PINMUX_ETH0_RX_DV		0x50e
+			IMX94_PAD_ETH0_RX_ER__NETC_PINMUX_ETH0_RX_ER		0x50e
+			IMX94_PAD_ETH0_RXD0__NETC_PINMUX_ETH0_RXD0		0x50e
+			IMX94_PAD_ETH0_RXD1__NETC_PINMUX_ETH0_RXD1		0x50e
+			IMX94_PAD_ETH0_RXD2__NETC_PINMUX_ETH0_RXD2		0x50e
+			IMX94_PAD_ETH0_RXD3__NETC_PINMUX_ETH0_RXD3		0x50e
+			IMX94_PAD_ETH0_TX_CLK__NETC_PINMUX_ETH0_TX_CLK		0x58e
+			IMX94_PAD_ETH0_TX_EN__NETC_PINMUX_ETH0_TX_EN		0x50e
+			IMX94_PAD_ETH0_TX_ER__NETC_PINMUX_ETH0_TX_ER		0x50e
+			IMX94_PAD_ETH0_TXD0__NETC_PINMUX_ETH0_TXD0		0x50e
+			IMX94_PAD_ETH0_TXD1__NETC_PINMUX_ETH0_TXD1		0x50e
+			IMX94_PAD_ETH0_TXD2__NETC_PINMUX_ETH0_TXD2		0x50e
+			IMX94_PAD_ETH0_TXD3__NETC_PINMUX_ETH0_TXD3		0x50e
+			IMX94_PAD_ETH0_CRS__NETC_PINMUX_ETH0_CRS		0x50e
+			IMX94_PAD_ETH0_COL__NETC_PINMUX_ETH0_COL		0x50e
+			IMX94_PAD_ETH1_RX_CLK__NETC_PINMUX_ETH1_RX_CLK		0x58e
+			IMX94_PAD_ETH1_RX_DV__NETC_PINMUX_ETH1_RX_DV		0x50e
+			IMX94_PAD_ETH1_RX_ER__NETC_PINMUX_ETH1_RX_ER		0x50e
+			IMX94_PAD_ETH1_RXD0__NETC_PINMUX_ETH1_RXD0		0x50e
+			IMX94_PAD_ETH1_RXD1__NETC_PINMUX_ETH1_RXD1		0x50e
+			IMX94_PAD_ETH1_RXD2__NETC_PINMUX_ETH1_RXD2		0x50e
+			IMX94_PAD_ETH1_RXD3__NETC_PINMUX_ETH1_RXD3		0x50e
+			IMX94_PAD_ETH1_TX_CLK__NETC_PINMUX_ETH1_TX_CLK		0x58e
+			IMX94_PAD_ETH1_TX_EN__NETC_PINMUX_ETH1_TX_EN		0x50e
+			IMX94_PAD_ETH1_TX_ER__NETC_PINMUX_ETH1_TX_ER		0x50e
+			IMX94_PAD_ETH1_TXD0__NETC_PINMUX_ETH1_TXD0		0x50e
+			IMX94_PAD_ETH1_TXD1__NETC_PINMUX_ETH1_TXD1		0x50e
+			IMX94_PAD_ETH1_TXD2__NETC_PINMUX_ETH1_TXD2		0x50e
+			IMX94_PAD_ETH1_TXD3__NETC_PINMUX_ETH1_TXD3		0x50e
+			IMX94_PAD_ETH1_CRS__NETC_PINMUX_ETH1_CRS		0x50e
+			IMX94_PAD_ETH1_COL__NETC_PINMUX_ETH1_COL		0x50e
+			IMX94_PAD_ETH2_TXD3__NETC_PINMUX_ETH2_TXD3		0x50e
+			IMX94_PAD_ETH2_TXD2__NETC_PINMUX_ETH2_TXD2		0x50e
+			IMX94_PAD_ETH2_TXD1__NETC_PINMUX_ETH2_TXD1		0x50e
+			IMX94_PAD_ETH2_TXD0__NETC_PINMUX_ETH2_TXD0		0x50e
+			IMX94_PAD_ETH2_TX_CTL__NETC_PINMUX_ETH2_TX_CTL		0x51e
+			IMX94_PAD_ETH2_TX_CLK__NETC_PINMUX_ETH2_TX_CLK		0x59e
+			IMX94_PAD_ETH2_RX_CTL__NETC_PINMUX_ETH2_RX_CTL		0x51e
+			IMX94_PAD_ETH2_RX_CLK__NETC_PINMUX_ETH2_RX_CLK		0x59e
+			IMX94_PAD_ETH2_RXD0__NETC_PINMUX_ETH2_RXD0		0x51e
+			IMX94_PAD_ETH2_RXD1__NETC_PINMUX_ETH2_RXD1		0x51e
+			IMX94_PAD_ETH2_RXD2__NETC_PINMUX_ETH2_RXD2		0x51e
+			IMX94_PAD_ETH2_RXD3__NETC_PINMUX_ETH2_RXD3		0x51e
+		>;
+	};
+
 	pinctrl_typec: typecgrp {
 		fsl,pins = <
 			IMX94_PAD_GPIO_IO44__GPIO3_IO12		0x30e
-- 
2.34.1