[PATCH] dt-bindings: ufs: amd,versal2-ufs: Add ref_clk clock property

[Ajay Neeli <ajay.neeli@amd.com>]

Add ref_clk clock property to specify the reference clock frequency
supplied to the UFS device.

The AMD Versal2 UFS controller operates with a 26 MHz reference clock.
UFS 3.x devices default their bRefClkFreq attribute to 26 MHz, matching
the controller, so no explicit configuration is needed. However, UFS 4.0
and later devices default bRefClkFreq to 52 MHz, expecting a 52 MHz
reference clock. This mismatch causes timing violations and link
instability.

Adding the ref_clk property allows the UFS driver to read the actual
reference clock frequency from the devicetree and program the device
bRefClkFreq attribute accordingly during initialization.

Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>
---
 .../devicetree/bindings/ufs/amd,versal2-ufs.yaml         | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml b/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml
index c00ec342d574..e294c0f1b0ce 100644
--- a/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml
@@ -20,11 +20,12 @@ properties:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    maxItems: 2
 
   clock-names:
     items:
       - const: core
+      - const: ref_clk
 
   power-domains:
     maxItems: 1
@@ -52,10 +53,10 @@ examples:
     ufs@f10b0000 {
         compatible = "amd,versal2-ufs";
         reg = <0xf10b0000 0x1000>;
-        clocks = <&ufs_core_clk>;
-        clock-names = "core";
+        clocks = <&ufs_core_clk>, <&ufs_ref_clk>;
+        clock-names = "core", "ref_clk";
         resets = <&scmi_reset 4>, <&scmi_reset 35>;
         reset-names = "host", "phy";
         interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
-        freq-table-hz = <0 0>;
+        freq-table-hz = <0 0>, <26000000 26000000>;
     };
-- 
2.43.7