[PATCH v2 0/2] dt-bindings: arm: omap-l3-noc: Convert to DT schema

[PATCH v2 0/2] dt-bindings: arm: omap-l3-noc: Convert to DT schema

[Bhargav Joshi]

This series converts the TI OMAP L3 NoC binding from text to DT schema.

On OMAP3 the ti,omap3-l3-smx node is deliberately modelled as a flat
simple-bus for the whole SoC,so  schema allows child nodes for that
compatible only. The NoC variants AM437x have no child nodes.

Patch 1 is a DTS change and patch 2 is the binding change. Patch 2
depends on patch 1 only to avoid a dtbs_check warning on omap36xx
boards.

Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
---
Changes in v2:
- Move binding to bindings/bus/
- Rebase to latest mainline rc
- Add unit address to regulator-abb-mpu node
- Link to v1: https://lore.kernel.org/r/20261003-ti-l3-noc-v1-1-9bd18cac33e9@gmail.com

---
Bhargav Joshi (2):
      ARM: dts: omap36xx: Add unit address to ABB regulator node
      dt-bindings: arm: omap-l3-noc: Convert to DT schema

 .../devicetree/bindings/arm/omap/l3-noc.txt        |  23 ----
 .../devicetree/bindings/bus/ti,omap-l3-noc.yaml    | 153 +++++++++++++++++++++
 arch/arm/boot/dts/ti/omap/omap36xx.dtsi            |   2 +-
 3 files changed, 154 insertions(+), 24 deletions(-)
---
base-commit: fa4ad798f6f681031775266044ba1b0cf3c670bd
change-id: 20261002-ti-l3-noc-28dfca81fdc5

Best regards,
-- 
Bhargav

[PATCH v2 1/2] ARM: dts: omap36xx: Add unit address to ABB regulator node

[Bhargav Joshi]

The ti,abb-v1 node abb_mpu_iva has a reg property but no unit address,
which violates the devicetree rule that the unit address must match
the first reg entry.

Add unit address to the ABB node in omap3.

Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
---
 arch/arm/boot/dts/ti/omap/omap36xx.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/ti/omap/omap36xx.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi
index c217094b50abc..6df66eb7e7eeb 100644
--- a/arch/arm/boot/dts/ti/omap/omap36xx.dtsi
+++ b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi
@@ -92,7 +92,7 @@ uart4: serial@49042000 {
 			clock-frequency = <48000000>;
 		};
 
-		abb_mpu_iva: regulator-abb-mpu {
+		abb_mpu_iva: regulator-abb-mpu@483072f0 {
 			compatible = "ti,abb-v1";
 			regulator-name = "abb_mpu_iva";
 			#address-cells = <0>;

-- 
2.56.0

[PATCH v2 2/2] dt-bindings: arm: omap-l3-noc: Convert to DT schema

[Bhargav Joshi]

Convert TI L3 NoC binding from text to DT schema format. Older OMAP3
uses the SMX variant which also acts as a bus parent with simple-bus
compatible so child nodes are allowed using patternproperties. Mark
ti,hwmods deprecated as it is no longer needed and only used by older
omap3-l3-smx. Move binding from /arm/omap to /bus/

Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
---
 .../devicetree/bindings/arm/omap/l3-noc.txt        |  23 ----
 .../devicetree/bindings/bus/ti,omap-l3-noc.yaml    | 153 +++++++++++++++++++++
 2 files changed, 153 insertions(+), 23 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
deleted file mode 100644
index 161448da959d2..0000000000000
--- a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* TI - L3 Network On Chip (NoC)
-
-This version is an implementation of the generic NoC IP
-provided by Arteris.
-
-Required properties:
-- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
-               Should be "ti,omap4-l3-noc" for OMAP4 family
-               Should be "ti,omap5-l3-noc" for OMAP5 family
-	       Should be "ti,dra7-l3-noc" for DRA7 family
-               Should be "ti,am4372-l3-noc" for AM43 family
-- reg:	Contains L3 register address range for each noc domain.
-- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
-
-Examples:
-
-ocp {
-	compatible = "ti,omap4-l3-noc", "simple-bus";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	ranges;
-	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
-};
diff --git a/Documentation/devicetree/bindings/bus/ti,omap-l3-noc.yaml b/Documentation/devicetree/bindings/bus/ti,omap-l3-noc.yaml
new file mode 100644
index 0000000000000..7dab336347b2c
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/ti,omap-l3-noc.yaml
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/ti,omap-l3-noc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI OMAP L3 Network On Chip (NoC) Interconnect
+
+maintainers:
+  - Santosh Shilimkar <santosh.shilimkar@ti.com>
+  - Sricharan R <r.sricharan@ti.com>
+
+description:
+  The L3 interconnect is an implementation of the generic NoC IP provided by
+  Arteris. OMAP3 uses the SMX variant while OMAP4/5, DRA7, and AM4372 use the
+  NoC variant.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: ti,omap3-l3-smx
+          - const: simple-bus
+      - enum:
+          - ti,omap4-l3-noc
+          - ti,omap5-l3-noc
+          - ti,dra7-l3-noc
+          - ti,am4372-l3-noc
+
+  reg:
+    minItems: 1
+    items:
+      - description: L3_MAIN_1 / L3F / SMX domain
+      - description: L3_MAIN_2 / L3S domain
+      - description: L3_MAIN_3 domain
+
+  interrupts:
+    items:
+      - description: l3-dbg-irq
+      - description: l3-app-irq
+
+  ti,hwmods:
+    description: hwmod names for each NoC domain.
+    $ref: /schemas/types.yaml#/definitions/string-array
+    deprecated: true
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  ranges: true
+
+patternProperties:
+  "^.*@[0-9a-f]+$":
+    type: object
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,omap3-l3-smx
+    then:
+      properties:
+        reg:
+          maxItems: 1
+        ti,hwmods:
+          maxItems: 1
+      required:
+        - "#address-cells"
+        - "#size-cells"
+        - ranges
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ti,omap4-l3-noc
+              - ti,omap5-l3-noc
+    then:
+      properties:
+        reg:
+          minItems: 3
+        "#address-cells": false
+        "#size-cells": false
+        ranges: false
+      patternProperties:
+        "^.*@[0-9a-f]+$": false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,dra7-l3-noc
+    then:
+      properties:
+        reg:
+          minItems: 2
+          maxItems: 3
+        "#address-cells": false
+        "#size-cells": false
+        ranges: false
+      patternProperties:
+        "^.*@[0-9a-f]+$": false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,am4372-l3-noc
+    then:
+      properties:
+        reg:
+          minItems: 2
+          maxItems: 2
+        "#address-cells": false
+        "#size-cells": false
+        ranges: false
+      patternProperties:
+        "^.*@[0-9a-f]+$": false
+
+additionalProperties: false
+
+examples:
+  - |
+    l3-noc@68000000 {
+        compatible = "ti,omap3-l3-smx", "simple-bus";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        reg = <0x68000000 0x10000>;
+        interrupts = <9>, <10>;
+        ti,hwmods = "l3_main";
+    };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    l3-noc@44000000 {
+        compatible = "ti,omap4-l3-noc";
+        reg = <0x44000000 0x1000>,
+              <0x44800000 0x2000>,
+              <0x45000000 0x1000>;
+        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+    };

-- 
2.56.0

Re: [PATCH v2 2/2] dt-bindings: arm: omap-l3-noc: Convert to DT schema

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential
issues to consider:
- [Low] dt-bindings: bus: ti,omap-l3-noc: split omap3-l3-smx into
  separate schema
- [Low] dt-bindings: bus: ti,omap-l3-noc: restrict ti,dra7-l3-noc reg to
  2 items
- [Low] dt-bindings: bus: ti,omap-l3-noc: fix property ordering in
  schema and example
--

commit 4bcc6989fce18ef0d819b57aac84df28a2100f89
Author: Bhargav Joshi <j.bhargav.u@gmail.com>

dt-bindings: arm: omap-l3-noc: Convert to DT schema

This commit converts the TI OMAP L3 Network On Chip (NoC) binding from text
to YAML DT schema format and moves it to Documentation/devicetree/bindings/bus/.

> diff --git a/Documentation/devicetree/bindings/bus/ti,omap-l3-noc.yaml b/Documentation/devicetree/bindings/bus/ti,omap-l3-noc.yaml
> new file mode 100644
> index 0000000000000..7dab336347b2c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/ti,omap-l3-noc.yaml

[ ... ]

> +  ti,hwmods:
> +    description: hwmod names for each NoC domain.
> +    $ref: /schemas/types.yaml#/definitions/string-array
> +    deprecated: true
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 1
> +
> +  ranges: true
> +
> +patternProperties:
> +  "^.*@[0-9a-f]+$":
> +    type: object
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: ti,omap3-l3-smx
> +    then:
> +      properties:
> +        reg:
> +          maxItems: 1
> +        ti,hwmods:
> +          maxItems: 1
> +      required:
> +        - "#address-cells"
> +        - "#size-cells"
> +        - ranges
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - ti,omap4-l3-noc
> +              - ti,omap5-l3-noc
> +    then:
> +      properties:
> +        reg:
> +          minItems: 3
> +        "#address-cells": false
> +        "#size-cells": false
> +        ranges: false
> +      patternProperties:
> +        "^.*@[0-9a-f]+$": false

[Severity: Low]
Should ti,omap3-l3-smx be split into a separate binding schema rather than
combined with the Arteris NoC variants?

On OMAP3, the SonicsMX interconnect (handled by drivers/bus/omap_l3_smx.c) is
modeled as a simple-bus parent node requiring #address-cells, #size-cells,
ranges, child device nodes, a single reg entry, and the legacy ti,hwmods
property.  The OMAP4/5, DRA7, and AM4372 NoC nodes (handled by
drivers/bus/omap_l3_noc.c) are leaf device nodes with multiple reg entries
and no child nodes.  Combining both into one schema requires declaring the
bus properties and patternProperties at the top level and repeating the same
exclusions across three separate allOf blocks, while still leaving ti,hwmods
allowed on the NoC compatibles.

> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: ti,dra7-l3-noc
> +    then:
> +      properties:
> +        reg:
> +          minItems: 2
> +          maxItems: 3

[Severity: Low]
Does ti,dra7-l3-noc support 3 reg entries, or should this be fixed at 2 items
like ti,am4372-l3-noc?

In drivers/bus/omap_l3_noc.h, dra_l3_data defines module 1 as
L3_BASE_IS_SUBMODULE sharing module 0's base address:

drivers/bus/omap_l3_noc.h:
static const struct omap_l3 dra_l3_data = {
	.l3_base = { [1] = L3_BASE_IS_SUBMODULE },
	.l3_flagmux = dra_l3_flagmux,
	.num_modules = ARRAY_SIZE(dra_l3_flagmux),

drivers/bus/omap_l3_noc.c:omap_l3_probe() {
	...
		if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) {
			/* First entry cannot be submodule */
			BUG_ON(i == 0);
			l3->l3_base[i] = l3->l3_base[i - 1];
			continue;
		}
		res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx);
	...
}

Because omap_l3_probe() skips platform_get_resource() and does not advance
res_idx for L3_BASE_IS_SUBMODULE, the driver only ever consumes 2 memory
resources on DRA7, and a 3rd reg entry would be ignored.

[ ... ]

> +examples:
> +  - |
> +    l3-noc@68000000 {
> +        compatible = "ti,omap3-l3-smx", "simple-bus";
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges;
> +        reg = <0x68000000 0x10000>;
> +        interrupts = <9>, <10>;
> +        ti,hwmods = "l3_main";
> +    };

[Severity: Low]
This isn't a bug, but per Documentation/devicetree/bindings/dts-coding-style.rst,
reg should come right after compatible, followed by ranges, standard
properties (#address-cells, #size-cells, interrupts), and vendor-specific
properties (ti,hwmods) last.  In the top-level properties block above,
ti,hwmods is also placed before #address-cells, #size-cells, and ranges.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261109-ti-l3-noc-v2-0-509e8485a1f3@gmail.com?part=2

Re: [PATCH v2 2/2] dt-bindings: arm: omap-l3-noc: Convert to DT schema

[Rob Herring]

On Sun, Nov 08, 2026 at 07:40:41PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 3 potential
> issues to consider:
> - [Low] dt-bindings: bus: ti,omap-l3-noc: split omap3-l3-smx into
>   separate schema
> - [Low] dt-bindings: bus: ti,omap-l3-noc: restrict ti,dra7-l3-noc reg to
>   2 items
> - [Low] dt-bindings: bus: ti,omap-l3-noc: fix property ordering in
>   schema and example

These all appear valid to me.

Rob