[PATCH v2 0/9] arm64: mediatek: Add initial MT6895 and Xiaomi Poco X4 GT support

[PATCH v2 0/9] arm64: mediatek: Add initial MT6895 and Xiaomi Poco X4 GT support

[Alexander Letuchiy]

This series adds initial support for the MediaTek MT6895 (Dimensity
8000/8100) SoC and the Xiaomi xaga board, sold as Xiaomi Poco X4 GT, Redmi
Note 11T Pro/Pro+ and Redmi K50i. It is enough to boot to an initramfs
with a serial console, CPU idle, the CPU and DSU PMUs and the volume down
key.

Dependencies
------------
The SoC DT describes the pin controller and the board DT uses its pinmux
macros, so this series depends on the MT6895 pinctrl series:
https://lore.kernel.org/r/20261108-pinctrl-mt6895-v1-0-f704c443b31a@gmail.com

Bootloader dependency
---------------------
This was tested with a modified LK bootloader that is not public.
The stock LK cannot boot this DT, as its Android fixups expect nodes
that are not present here.

The DT relies on the bootloader to:

 - update the /memory node
 - add all firmware carveouts to /reserved-memory
 - pass the command line from the boot image

The carveout addresses are therefore not listed in the DT, as the
bootloader allocates some of them dynamically. I can describe the
fixed ones in the DT if that is preferred.

Firmware behaviour
------------------
Two things in the stock TF-A affect what the DT describes, but not the
DT itself:

 - TF-A rejects CPU_SUSPEND for about the first 40 seconds after boot.
   The vendor kernel lifts this earlier with a SiP call, so with this
   series the idle states only start to be used after that time.
 - The DSU PMU registers are lost when the cluster powers down. TF-A
   can preserve them (PRESERVE_DSU_PMU_REGS), but the MediaTek firmware
   does not, so DSU PMU counts are only reliable while the cluster stays
   powered up.

Testing
-------
Tested on a Poco X4 GT with 8 GiB of RAM, using a minimal config and a
script in the initramfs. The results were:

 - All 8 CPUs come up and match the DT (A55 on 0-3, A78 on 4-7), and
   CPUs 1-7 can be taken offline and brought back through PSCI.
 - The cache sizes and geometry in sysfs match the CCSIDR registers on
   every CPU.
 - The redistributor is found for each CPU, and timer interrupts reach
   every CPU.
 - Once TF-A accepts CPU_SUSPEND, every CPU enters the CPU and cluster
   power down states, and the system timer wakes them up as the
   broadcast timer.
 - Each core PMU counts only on its own CPUs, and its overflow interrupt
   arrives on the right CPU through its PPI partition.
 - The DSU PMU counts, and its overflow interrupt arrives on SPI 18.
 - The pin configuration of the UART0 and keypad pins matches the DT.
 - The volume down key reports presses and releases, with no bounce
   through the 32 ms debounce.
 - UART0 output works at 921600 baud, and its TX interrupt fires on the
   expected line.
 - About 7 GiB of RAM was written and verified with no errors, with the
   carveouts added by the bootloader.
 - The watchdog resets the board once it is no longer pinged, and the
   ramoops console log survives that reset.

UART1 is disabled and was not tested. Only a minimal config was tested
on the device, not defconfig.

Tool use
--------
The commit messages, this cover letter and the test script were
drafted with Claude Code (Claude Opus 5.5). I reviewed them
and tested the result on the device.

Based on next-20261113.

---
Changes in v2:
- Describe MT6895 as Dimensity 8000/8100 in the commit messages.
- watchdog binding: drop the mediatek,mt6589-wdt fallback, as the
  MT6895 reset layout is not known, and drop Conor's Acked-by.
- New patch: add the MT6895 compatible to the mtk_wdt driver.
- New patches: system timer and keypad bindings, pinmux header.
- SoC DT: add the cache nodes, CPU capacities and idle states, the CPU
  PMUs with PPI partitions, the DSU PMU, the system timer with a 13 MHz
  clock, the pin controller and the keypad.
- SoC DT: use IRQ_TYPE_LEVEL_HIGH for the architected timer PPIs.
- SoC DT: order the nodes as required by dt-check-style.
- Board DT: add the UART0 pins and the volume down key.
- The series now depends on the MT6895 pinctrl series.
- Link to v1: https://patch.msgid.link/20261105210622.523747-1-asalde.le1@gmail.com

---
Alexander Letuchiy (9):
      dt-bindings: arm: mediatek: Add MT6895 and Xiaomi Poco X4 GT
      dt-bindings: serial: mediatek,uart: Add compatible for MT6895
      dt-bindings: watchdog: mediatek,mtk-wdt: Add compatible for MT6895
      watchdog: mediatek: Add support for MT6895
      dt-bindings: timer: mediatek,timer: Add compatible for MT6895
      dt-bindings: input: mediatek,mt6779-keypad: Add compatible for MT6895
      arm64: dts: mediatek: Add MT6895 pinmux macro header file
      arm64: dts: mediatek: Add MT6895 SoC
      arm64: dts: mediatek: Add Xiaomi Poco X4 GT

 .../devicetree/bindings/arm/mediatek.yaml          |    4 +
 .../bindings/input/mediatek,mt6779-keypad.yaml     |    1 +
 .../devicetree/bindings/serial/mediatek,uart.yaml  |    1 +
 .../devicetree/bindings/timer/mediatek,timer.yaml  |    1 +
 .../bindings/watchdog/mediatek,mtk-wdt.yaml        |    1 +
 arch/arm64/boot/dts/mediatek/Makefile              |    1 +
 arch/arm64/boot/dts/mediatek/mt6895-pinfunc.h      | 1524 ++++++++++++++++++++
 .../arm64/boot/dts/mediatek/mt6895-xiaomi-xaga.dts |   87 ++
 arch/arm64/boot/dts/mediatek/mt6895.dtsi           |  461 ++++++
 drivers/watchdog/mtk_wdt.c                         |    1 +
 10 files changed, 2082 insertions(+)
---
base-commit: 84abb955b1015477aa11a96e2f3ac1b938b77f48
change-id: 20261110-initial-mt6895-16ef1b1aef55
prerequisite-message-id: <20261108-pinctrl-mt6895-v1-0-f704c443b31a@gmail.com>
prerequisite-patch-id: 68c077b6ff907e42d02115ed9b95bb5349eae7ef
prerequisite-patch-id: 09c2602edc0cdb6ca34ecbae12f608ab530da477

Best regards,
--  
Alexander Letuchiy <asalde.le1@gmail.com>

[PATCH v2 1/9] dt-bindings: arm: mediatek: Add MT6895 and Xiaomi Poco X4 GT

[Alexander Letuchiy]

Add the compatible for the MediaTek MT6895 (Dimensity 8000/8100) SoC,
along with the Xiaomi xaga board based on it, which is sold as Xiaomi
Poco X4 GT, Redmi Note 11T Pro/Pro+ and Redmi K50i.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Alexander Letuchiy <asalde.le1@gmail.com>
---
 Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 180e6e4948e7..28180ed0e815 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -72,6 +72,10 @@ properties:
               - archermind,mt6797-x20-dev
               - mediatek,mt6797-evb
           - const: mediatek,mt6797
+      - items:
+          - enum:
+              - xiaomi,xaga
+          - const: mediatek,mt6895
       - items:
           - enum:
               - bananapi,bpi-r64

-- 
2.56.0

[PATCH v2 2/9] dt-bindings: serial: mediatek,uart: Add compatible for MT6895

[Alexander Letuchiy]

Add a compatible string for the UART of the MediaTek MT6895 (Dimensity
8000/8100) SoC. It works with the existing driver through the
mediatek,mt6577-uart fallback.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Alexander Letuchiy <asalde.le1@gmail.com>
---
 Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
index 5bd8a8853ae0..a3969cfdea7e 100644
--- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
+++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
@@ -35,6 +35,7 @@ properties:
               - mediatek,mt6795-uart
               - mediatek,mt6797-uart
               - mediatek,mt6893-uart
+              - mediatek,mt6895-uart
               - mediatek,mt7622-uart
               - mediatek,mt7623-uart
               - mediatek,mt7629-uart

-- 
2.56.0

[PATCH v2 3/9] dt-bindings: watchdog: mediatek,mtk-wdt: Add compatible for MT6895

[Alexander Letuchiy]

Add a compatible string for the watchdog of the MediaTek MT6895
(Dimensity 8000/8100) SoC. It does not fall back to mediatek,mt6589-wdt,
which implies the MT6589 TOPRGU reset layout, as the MT6895 one is not
known yet.

Signed-off-by: Alexander Letuchiy <asalde.le1@gmail.com>
---
 Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
index 8e8991ac95ea..d0a73b9c81d6 100644
--- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml
@@ -24,6 +24,7 @@ properties:
           - mediatek,mt6589-wdt
           - mediatek,mt6735-wdt
           - mediatek,mt6795-wdt
+          - mediatek,mt6895-wdt
           - mediatek,mt7986-wdt
           - mediatek,mt7988-wdt
           - mediatek,mt8163-wdt

-- 
2.56.0

[PATCH v2 4/9] watchdog: mediatek: Add support for MT6895

[Alexander Letuchiy]

Add the compatible for the watchdog of the MediaTek MT6895 (Dimensity
8000/8100) SoC. Its watchdog registers are the same as on the other
supported SoCs.

The TOPRGU reset layout of MT6895 is not known yet, so the entry has no
match data and no reset controller is registered.

Signed-off-by: Alexander Letuchiy <asalde.le1@gmail.com>
---
 drivers/watchdog/mtk_wdt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index a210fe1569e4..d8755979021b 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -607,6 +607,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = {
 	{ .compatible = "mediatek,mt6589-wdt", .data = &mt6589_data },
 	{ .compatible = "mediatek,mt6735-wdt", .data = &mt6735_data },
 	{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
+	{ .compatible = "mediatek,mt6895-wdt" },
 	{ .compatible = "mediatek,mt7629-wdt", .data = &mt7629_data },
 	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
 	{ .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },

-- 
2.56.0

[PATCH v2 5/9] dt-bindings: timer: mediatek,timer: Add compatible for MT6895

[Alexander Letuchiy]

Add a compatible string for the system timer (SYST) of the MediaTek
MT6895 (Dimensity 8000/8100) SoC. It works with the existing driver
through the mediatek,mt6765-timer fallback.

Signed-off-by: Alexander Letuchiy <asalde.le1@gmail.com>
---
 Documentation/devicetree/bindings/timer/mediatek,timer.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml
index 337580dc77d8..ee4af54c29b5 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml
+++ b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml
@@ -40,6 +40,7 @@ properties:
       # SYST Timers
       - items:
           - enum:
+              - mediatek,mt6895-timer
               - mediatek,mt7629-timer
               - mediatek,mt8183-timer
               - mediatek,mt8186-timer

-- 
2.56.0

[PATCH v2 6/9] dt-bindings: input: mediatek,mt6779-keypad: Add compatible for MT6895

[Alexander Letuchiy]

Add a compatible string for the keypad of the MediaTek MT6895 (Dimensity
8000/8100) SoC. Its registers are the same as on MT6779, so it works
with the existing driver through the mediatek,mt6779-keypad fallback.

Signed-off-by: Alexander Letuchiy <asalde.le1@gmail.com>
---
 Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml
index 9f0da1240187..9a1369c9ff4c 100644
--- a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml
+++ b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml
@@ -29,6 +29,7 @@ properties:
               - mediatek,mt6572-keypad
               - mediatek,mt6595-keypad
               - mediatek,mt6873-keypad
+              - mediatek,mt6895-keypad
               - mediatek,mt8173-keypad
               - mediatek,mt8183-keypad
               - mediatek,mt8365-keypad

-- 
2.56.0

[PATCH v2 7/9] arm64: dts: mediatek: Add MT6895 pinmux macro header file

[Alexander Letuchiy]

Add the pinmux macro header for the MediaTek MT6895 (Dimensity
8000/8100) SoC. It defines the PINMUX_GPIOx__FUNC_* macros used to
select the function of each pin in the device trees.

Signed-off-by: Alexander Letuchiy <asalde.le1@gmail.com>
---
 arch/arm64/boot/dts/mediatek/mt6895-pinfunc.h | 1524 +++++++++++++++++++++++++
 1 file changed, 1524 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6895-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt6895-pinfunc.h
new file mode 100644
index 000000000000..b395f0079466
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6895-pinfunc.h
@@ -0,0 +1,1524 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ *
+ * Author: Light Hsieh <light.hsieh@mediatek.com>
+ */
+#ifndef __MT6895_PINFUNC_H
+#define __MT6895_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define PINMUX_GPIO0__FUNC_VOW_CLK_MISO (MTK_PIN_NO(0) | 3)
+#define PINMUX_GPIO0__FUNC_SRCLKENAI1 (MTK_PIN_NO(0) | 5)
+#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6)
+#define PINMUX_GPIO0__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(0) | 7)
+
+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define PINMUX_GPIO1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(1) | 3)
+#define PINMUX_GPIO1__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(1) | 4)
+#define PINMUX_GPIO1__FUNC_SRCLKENAI0 (MTK_PIN_NO(1) | 5)
+#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6)
+#define PINMUX_GPIO1__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(1) | 7)
+
+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define PINMUX_GPIO2__FUNC_PWM_VLP (MTK_PIN_NO(2) | 1)
+#define PINMUX_GPIO2__FUNC_AGPS_SYNC (MTK_PIN_NO(2) | 3)
+#define PINMUX_GPIO2__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(2) | 4)
+#define PINMUX_GPIO2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 5)
+#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6)
+#define PINMUX_GPIO2__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(2) | 7)
+
+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define PINMUX_GPIO3__FUNC_PWM_VLP (MTK_PIN_NO(3) | 1)
+#define PINMUX_GPIO3__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(3) | 2)
+#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 4)
+#define PINMUX_GPIO3__FUNC_KPCOL2 (MTK_PIN_NO(3) | 5)
+#define PINMUX_GPIO3__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(3) | 6)
+#define PINMUX_GPIO3__FUNC_TP_UCTS2_VLP (MTK_PIN_NO(3) | 7)
+
+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define PINMUX_GPIO4__FUNC_SPI7_A_MI (MTK_PIN_NO(4) | 1)
+#define PINMUX_GPIO4__FUNC_ANT_SEL16 (MTK_PIN_NO(4) | 2)
+#define PINMUX_GPIO4__FUNC_PTA_EXT_FREQ (MTK_PIN_NO(4) | 3)
+#define PINMUX_GPIO4__FUNC_UTXD2 (MTK_PIN_NO(4) | 4)
+#define PINMUX_GPIO4__FUNC_I2S2_DI (MTK_PIN_NO(4) | 5)
+#define PINMUX_GPIO4__FUNC_DBG_MON_B25 (MTK_PIN_NO(4) | 7)
+
+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define PINMUX_GPIO5__FUNC_SPI7_A_CSB (MTK_PIN_NO(5) | 1)
+#define PINMUX_GPIO5__FUNC_ANT_SEL17 (MTK_PIN_NO(5) | 2)
+#define PINMUX_GPIO5__FUNC_PTA_EXT_ACT (MTK_PIN_NO(5) | 3)
+#define PINMUX_GPIO5__FUNC_URXD2 (MTK_PIN_NO(5) | 4)
+#define PINMUX_GPIO5__FUNC_I2S2_MCK (MTK_PIN_NO(5) | 5)
+#define PINMUX_GPIO5__FUNC_DBG_MON_B26 (MTK_PIN_NO(5) | 7)
+
+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define PINMUX_GPIO6__FUNC_SCL0 (MTK_PIN_NO(6) | 1)
+#define PINMUX_GPIO6__FUNC_IDDIG_1P (MTK_PIN_NO(6) | 2)
+#define PINMUX_GPIO6__FUNC_SPI4_B_CLK (MTK_PIN_NO(6) | 3)
+
+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define PINMUX_GPIO7__FUNC_SDA0 (MTK_PIN_NO(7) | 1)
+#define PINMUX_GPIO7__FUNC_IDDIG (MTK_PIN_NO(7) | 2)
+#define PINMUX_GPIO7__FUNC_SPI4_B_CSB (MTK_PIN_NO(7) | 3)
+
+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define PINMUX_GPIO8__FUNC_SCL1 (MTK_PIN_NO(8) | 1)
+#define PINMUX_GPIO8__FUNC_SCP_SCL5 (MTK_PIN_NO(8) | 3)
+#define PINMUX_GPIO8__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(8) | 4)
+
+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define PINMUX_GPIO9__FUNC_SDA1 (MTK_PIN_NO(9) | 1)
+#define PINMUX_GPIO9__FUNC_SCP_SDA5 (MTK_PIN_NO(9) | 3)
+#define PINMUX_GPIO9__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(9) | 4)
+
+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define PINMUX_GPIO10__FUNC_DMIC1_CLK (MTK_PIN_NO(10) | 1)
+#define PINMUX_GPIO10__FUNC_AGPS_SYNC (MTK_PIN_NO(10) | 2)
+#define PINMUX_GPIO10__FUNC_ANT_SEL3 (MTK_PIN_NO(10) | 3)
+#define PINMUX_GPIO10__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(10) | 4)
+#define PINMUX_GPIO10__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(10) | 5)
+#define PINMUX_GPIO10__FUNC_IDDIG (MTK_PIN_NO(10) | 6)
+#define PINMUX_GPIO10__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(10) | 7)
+
+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define PINMUX_GPIO11__FUNC_DMIC1_DAT (MTK_PIN_NO(11) | 1)
+#define PINMUX_GPIO11__FUNC_ANT_SEL4 (MTK_PIN_NO(11) | 3)
+#define PINMUX_GPIO11__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(11) | 4)
+#define PINMUX_GPIO11__FUNC_AGPS_SYNC (MTK_PIN_NO(11) | 5)
+#define PINMUX_GPIO11__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6)
+#define PINMUX_GPIO11__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(11) | 7)
+
+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define PINMUX_GPIO12__FUNC_KPROW2 (MTK_PIN_NO(12) | 1)
+#define PINMUX_GPIO12__FUNC_TP_GPIO4_AO (MTK_PIN_NO(12) | 3)
+#define PINMUX_GPIO12__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(12) | 4)
+#define PINMUX_GPIO12__FUNC_SCP_SCL5 (MTK_PIN_NO(12) | 5)
+#define PINMUX_GPIO12__FUNC_DP_TX_HPD (MTK_PIN_NO(12) | 6)
+
+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define PINMUX_GPIO13__FUNC_MD_INT4 (MTK_PIN_NO(13) | 1)
+#define PINMUX_GPIO13__FUNC_TP_GPIO5_AO (MTK_PIN_NO(13) | 3)
+#define PINMUX_GPIO13__FUNC_TP_URXD1_VLP (MTK_PIN_NO(13) | 4)
+#define PINMUX_GPIO13__FUNC_SCP_SDA5 (MTK_PIN_NO(13) | 5)
+#define PINMUX_GPIO13__FUNC_DP_OC_EN (MTK_PIN_NO(13) | 6)
+
+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define PINMUX_GPIO14__FUNC_MD_INT3 (MTK_PIN_NO(14) | 1)
+#define PINMUX_GPIO14__FUNC_TP_GPIO6_AO (MTK_PIN_NO(14) | 3)
+#define PINMUX_GPIO14__FUNC_TP_URTS1_VLP (MTK_PIN_NO(14) | 4)
+#define PINMUX_GPIO14__FUNC_SCP_SCL6 (MTK_PIN_NO(14) | 5)
+#define PINMUX_GPIO14__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(14) | 6)
+
+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define PINMUX_GPIO15__FUNC_MD_INT0 (MTK_PIN_NO(15) | 1)
+#define PINMUX_GPIO15__FUNC_TP_GPIO7_AO (MTK_PIN_NO(15) | 3)
+#define PINMUX_GPIO15__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(15) | 4)
+#define PINMUX_GPIO15__FUNC_SCP_SDA6 (MTK_PIN_NO(15) | 5)
+#define PINMUX_GPIO15__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(15) | 6)
+
+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define PINMUX_GPIO16__FUNC_SRCLKENAI1 (MTK_PIN_NO(16) | 1)
+#define PINMUX_GPIO16__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(16) | 2)
+#define PINMUX_GPIO16__FUNC_TP_GPIO8_AO (MTK_PIN_NO(16) | 3)
+#define PINMUX_GPIO16__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(16) | 4)
+#define PINMUX_GPIO16__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(16) | 6)
+
+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define PINMUX_GPIO17__FUNC_SRCLKENAI0 (MTK_PIN_NO(17) | 1)
+#define PINMUX_GPIO17__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(17) | 2)
+#define PINMUX_GPIO17__FUNC_TP_GPIO9_AO (MTK_PIN_NO(17) | 3)
+#define PINMUX_GPIO17__FUNC_TP_URXD2_VLP (MTK_PIN_NO(17) | 4)
+#define PINMUX_GPIO17__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(17) | 6)
+
+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define PINMUX_GPIO18__FUNC_KPCOL2 (MTK_PIN_NO(18) | 1)
+#define PINMUX_GPIO18__FUNC_SRCLKENAI0 (MTK_PIN_NO(18) | 2)
+#define PINMUX_GPIO18__FUNC_TP_GPIO10_AO (MTK_PIN_NO(18) | 3)
+#define PINMUX_GPIO18__FUNC_TP_URTS2_VLP (MTK_PIN_NO(18) | 4)
+#define PINMUX_GPIO18__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(18) | 5)
+#define PINMUX_GPIO18__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(18) | 6)
+#define PINMUX_GPIO18__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(18) | 7)
+
+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define PINMUX_GPIO19__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(19) | 2)
+#define PINMUX_GPIO19__FUNC_ANT_SEL15 (MTK_PIN_NO(19) | 4)
+#define PINMUX_GPIO19__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(19) | 6)
+
+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define PINMUX_GPIO20__FUNC_I2S3_MCK (MTK_PIN_NO(20) | 1)
+#define PINMUX_GPIO20__FUNC_IDDIG (MTK_PIN_NO(20) | 2)
+#define PINMUX_GPIO20__FUNC_SPI5_B_MO (MTK_PIN_NO(20) | 3)
+#define PINMUX_GPIO20__FUNC_GPS_PPS (MTK_PIN_NO(20) | 4)
+#define PINMUX_GPIO20__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(20) | 5)
+#define PINMUX_GPIO20__FUNC_I2S0_MCK (MTK_PIN_NO(20) | 6)
+#define PINMUX_GPIO20__FUNC_IDDIG_1P (MTK_PIN_NO(20) | 7)
+
+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define PINMUX_GPIO21__FUNC_I2S3_BCK (MTK_PIN_NO(21) | 1)
+#define PINMUX_GPIO21__FUNC_USB_DRVVBUS (MTK_PIN_NO(21) | 2)
+#define PINMUX_GPIO21__FUNC_SPI5_B_MI (MTK_PIN_NO(21) | 3)
+#define PINMUX_GPIO21__FUNC_PCM0_CLK (MTK_PIN_NO(21) | 4)
+#define PINMUX_GPIO21__FUNC_PCM1_CLK (MTK_PIN_NO(21) | 5)
+#define PINMUX_GPIO21__FUNC_I2S0_BCK (MTK_PIN_NO(21) | 6)
+#define PINMUX_GPIO21__FUNC_IDDIG (MTK_PIN_NO(21) | 7)
+
+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define PINMUX_GPIO22__FUNC_I2S3_LRCK (MTK_PIN_NO(22) | 1)
+#define PINMUX_GPIO22__FUNC_SPI5_B_CSB (MTK_PIN_NO(22) | 3)
+#define PINMUX_GPIO22__FUNC_PCM0_SYNC (MTK_PIN_NO(22) | 4)
+#define PINMUX_GPIO22__FUNC_PCM1_SYNC (MTK_PIN_NO(22) | 5)
+#define PINMUX_GPIO22__FUNC_I2S0_LRCK (MTK_PIN_NO(22) | 6)
+
+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define PINMUX_GPIO23__FUNC_I2S0_DI (MTK_PIN_NO(23) | 1)
+#define PINMUX_GPIO23__FUNC_ANT_SEL14 (MTK_PIN_NO(23) | 2)
+#define PINMUX_GPIO23__FUNC_PCM0_DI (MTK_PIN_NO(23) | 4)
+#define PINMUX_GPIO23__FUNC_PCM1_DI (MTK_PIN_NO(23) | 5)
+#define PINMUX_GPIO23__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(23) | 6)
+#define PINMUX_GPIO23__FUNC_UDI_TDO_0 (MTK_PIN_NO(23) | 7)
+
+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define PINMUX_GPIO24__FUNC_I2S3_DO (MTK_PIN_NO(24) | 1)
+#define PINMUX_GPIO24__FUNC_SPI5_B_CLK (MTK_PIN_NO(24) | 3)
+#define PINMUX_GPIO24__FUNC_PCM0_DO (MTK_PIN_NO(24) | 4)
+#define PINMUX_GPIO24__FUNC_PCM1_DO0 (MTK_PIN_NO(24) | 5)
+#define PINMUX_GPIO24__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(24) | 6)
+#define PINMUX_GPIO24__FUNC_UDI_TDI_0 (MTK_PIN_NO(24) | 7)
+
+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define PINMUX_GPIO25__FUNC_SPI1_A_CLK (MTK_PIN_NO(25) | 1)
+#define PINMUX_GPIO25__FUNC_IDDIG_1P (MTK_PIN_NO(25) | 3)
+#define PINMUX_GPIO25__FUNC_DP_TX_HPD (MTK_PIN_NO(25) | 4)
+#define PINMUX_GPIO25__FUNC_DMIC1_CLK (MTK_PIN_NO(25) | 7)
+
+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define PINMUX_GPIO26__FUNC_SPI1_A_CSB (MTK_PIN_NO(26) | 1)
+#define PINMUX_GPIO26__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(26) | 3)
+#define PINMUX_GPIO26__FUNC_DP_OC_EN (MTK_PIN_NO(26) | 4)
+#define PINMUX_GPIO26__FUNC_DMIC1_DAT (MTK_PIN_NO(26) | 7)
+
+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define PINMUX_GPIO27__FUNC_SPI1_A_MI (MTK_PIN_NO(27) | 1)
+#define PINMUX_GPIO27__FUNC_VBUSVALID_1P (MTK_PIN_NO(27) | 3)
+#define PINMUX_GPIO27__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(27) | 4)
+
+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define PINMUX_GPIO28__FUNC_SPI1_A_MO (MTK_PIN_NO(28) | 1)
+#define PINMUX_GPIO28__FUNC_VBUSVALID (MTK_PIN_NO(28) | 2)
+#define PINMUX_GPIO28__FUNC_PWM_0 (MTK_PIN_NO(28) | 3)
+#define PINMUX_GPIO28__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(28) | 4)
+
+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define PINMUX_GPIO29__FUNC_SCL7 (MTK_PIN_NO(29) | 1)
+#define PINMUX_GPIO29__FUNC_SCP_SCL4 (MTK_PIN_NO(29) | 2)
+
+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define PINMUX_GPIO30__FUNC_SDA7 (MTK_PIN_NO(30) | 1)
+#define PINMUX_GPIO30__FUNC_SCP_SDA4 (MTK_PIN_NO(30) | 2)
+#define PINMUX_GPIO30__FUNC_ANT_SEL19 (MTK_PIN_NO(30) | 3)
+
+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define PINMUX_GPIO31__FUNC_SCL6 (MTK_PIN_NO(31) | 1)
+#define PINMUX_GPIO31__FUNC_SPI4_B_MI (MTK_PIN_NO(31) | 3)
+
+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define PINMUX_GPIO32__FUNC_SDA6 (MTK_PIN_NO(32) | 1)
+#define PINMUX_GPIO32__FUNC_SPI4_B_MO (MTK_PIN_NO(32) | 3)
+
+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define PINMUX_GPIO33__FUNC_SCL5 (MTK_PIN_NO(33) | 1)
+#define PINMUX_GPIO33__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(33) | 2)
+#define PINMUX_GPIO33__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(33) | 3)
+
+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define PINMUX_GPIO34__FUNC_SDA5 (MTK_PIN_NO(34) | 1)
+#define PINMUX_GPIO34__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(34) | 2)
+#define PINMUX_GPIO34__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(34) | 3)
+
+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define PINMUX_GPIO35__FUNC_SCP_SCL0 (MTK_PIN_NO(35) | 1)
+
+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define PINMUX_GPIO36__FUNC_SCP_SDA0 (MTK_PIN_NO(36) | 1)
+
+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define PINMUX_GPIO37__FUNC_SCP_SCL2 (MTK_PIN_NO(37) | 1)
+#define PINMUX_GPIO37__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(37) | 2)
+
+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define PINMUX_GPIO38__FUNC_SCP_SDA2 (MTK_PIN_NO(38) | 1)
+#define PINMUX_GPIO38__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(38) | 2)
+
+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define PINMUX_GPIO39__FUNC_DISP_PWM (MTK_PIN_NO(39) | 1)
+#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 3)
+#define PINMUX_GPIO39__FUNC_ANT_SEL16 (MTK_PIN_NO(39) | 4)
+#define PINMUX_GPIO39__FUNC_GPS_PPS (MTK_PIN_NO(39) | 5)
+#define PINMUX_GPIO39__FUNC_UDI_NTRST (MTK_PIN_NO(39) | 7)
+
+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define PINMUX_GPIO40__FUNC_DSI_TE (MTK_PIN_NO(40) | 1)
+#define PINMUX_GPIO40__FUNC_UDI_TMS (MTK_PIN_NO(40) | 7)
+
+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define PINMUX_GPIO41__FUNC_LCM_RST (MTK_PIN_NO(41) | 1)
+#define PINMUX_GPIO41__FUNC_UDI_TCK (MTK_PIN_NO(41) | 7)
+
+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define PINMUX_GPIO42__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(42) | 1)
+#define PINMUX_GPIO42__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(42) | 2)
+#define PINMUX_GPIO42__FUNC_TP_GPIO0_AO (MTK_PIN_NO(42) | 3)
+#define PINMUX_GPIO42__FUNC_PTA_RXD (MTK_PIN_NO(42) | 4)
+#define PINMUX_GPIO42__FUNC_SRCLKENAI0 (MTK_PIN_NO(42) | 6)
+
+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define PINMUX_GPIO43__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(43) | 1)
+#define PINMUX_GPIO43__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(43) | 2)
+#define PINMUX_GPIO43__FUNC_TP_GPIO1_AO (MTK_PIN_NO(43) | 3)
+#define PINMUX_GPIO43__FUNC_PTA_TXD (MTK_PIN_NO(43) | 4)
+#define PINMUX_GPIO43__FUNC_CLKM2 (MTK_PIN_NO(43) | 5)
+#define PINMUX_GPIO43__FUNC_SRCLKENAI1 (MTK_PIN_NO(43) | 6)
+
+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define PINMUX_GPIO44__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(44) | 1)
+#define PINMUX_GPIO44__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(44) | 2)
+#define PINMUX_GPIO44__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(44) | 3)
+#define PINMUX_GPIO44__FUNC_CCU0_JTAG_TDI (MTK_PIN_NO(44) | 5)
+#define PINMUX_GPIO44__FUNC_LVTS_SCK (MTK_PIN_NO(44) | 6)
+#define PINMUX_GPIO44__FUNC_CONN_BGF_DSP_L5_JDI (MTK_PIN_NO(44) | 7)
+
+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define PINMUX_GPIO45__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(45) | 1)
+#define PINMUX_GPIO45__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(45) | 2)
+#define PINMUX_GPIO45__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(45) | 3)
+#define PINMUX_GPIO45__FUNC_CCU0_JTAG_TMS (MTK_PIN_NO(45) | 5)
+#define PINMUX_GPIO45__FUNC_LVTS_SDI (MTK_PIN_NO(45) | 6)
+#define PINMUX_GPIO45__FUNC_CONN_BGF_DSP_L5_JMS (MTK_PIN_NO(45) | 7)
+
+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define PINMUX_GPIO46__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(46) | 1)
+#define PINMUX_GPIO46__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(46) | 2)
+#define PINMUX_GPIO46__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(46) | 3)
+#define PINMUX_GPIO46__FUNC_CCU0_JTAG_TDO (MTK_PIN_NO(46) | 5)
+#define PINMUX_GPIO46__FUNC_LVTS_SCF (MTK_PIN_NO(46) | 6)
+#define PINMUX_GPIO46__FUNC_CONN_BGF_DSP_L5_JDO (MTK_PIN_NO(46) | 7)
+
+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define PINMUX_GPIO47__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(47) | 1)
+#define PINMUX_GPIO47__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(47) | 2)
+#define PINMUX_GPIO47__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(47) | 3)
+#define PINMUX_GPIO47__FUNC_CCU0_JTAG_TRST (MTK_PIN_NO(47) | 5)
+#define PINMUX_GPIO47__FUNC_LVTS_FOUT (MTK_PIN_NO(47) | 6)
+#define PINMUX_GPIO47__FUNC_CONN_BGF_DSP_L5_JINTP (MTK_PIN_NO(47) | 7)
+
+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define PINMUX_GPIO48__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(48) | 1)
+#define PINMUX_GPIO48__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(48) | 2)
+#define PINMUX_GPIO48__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(48) | 3)
+#define PINMUX_GPIO48__FUNC_CCU0_JTAG_TCK (MTK_PIN_NO(48) | 5)
+#define PINMUX_GPIO48__FUNC_LVTS_SDO (MTK_PIN_NO(48) | 6)
+#define PINMUX_GPIO48__FUNC_CONN_BGF_DSP_L5_JCK (MTK_PIN_NO(48) | 7)
+
+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define PINMUX_GPIO49__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(49) | 1)
+#define PINMUX_GPIO49__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(49) | 2)
+#define PINMUX_GPIO49__FUNC_LVTS_26M (MTK_PIN_NO(49) | 6)
+
+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define PINMUX_GPIO50__FUNC_MSDC1_CLK (MTK_PIN_NO(50) | 1)
+#define PINMUX_GPIO50__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(50) | 2)
+#define PINMUX_GPIO50__FUNC_UDI_TCK (MTK_PIN_NO(50) | 4)
+#define PINMUX_GPIO50__FUNC_CONN_BGF_DSP_L1_JCK (MTK_PIN_NO(50) | 5)
+#define PINMUX_GPIO50__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(50) | 6)
+#define PINMUX_GPIO50__FUNC_JTCK_SEL3 (MTK_PIN_NO(50) | 7)
+
+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define PINMUX_GPIO51__FUNC_MSDC1_CMD (MTK_PIN_NO(51) | 1)
+#define PINMUX_GPIO51__FUNC_UDI_TMS (MTK_PIN_NO(51) | 4)
+#define PINMUX_GPIO51__FUNC_CONN_BGF_DSP_L1_JMS (MTK_PIN_NO(51) | 5)
+#define PINMUX_GPIO51__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(51) | 6)
+#define PINMUX_GPIO51__FUNC_JTMS_SEL3 (MTK_PIN_NO(51) | 7)
+
+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define PINMUX_GPIO52__FUNC_MSDC1_DAT3 (MTK_PIN_NO(52) | 1)
+#define PINMUX_GPIO52__FUNC_TP_GPIO2_AO (MTK_PIN_NO(52) | 3)
+#define PINMUX_GPIO52__FUNC_CONN_BGF_DSP_L1_JINTP (MTK_PIN_NO(52) | 5)
+
+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define PINMUX_GPIO53__FUNC_MSDC1_DAT0 (MTK_PIN_NO(53) | 1)
+#define PINMUX_GPIO53__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(53) | 2)
+#define PINMUX_GPIO53__FUNC_UDI_TDI_0 (MTK_PIN_NO(53) | 4)
+#define PINMUX_GPIO53__FUNC_CONN_BGF_DSP_L1_JDI (MTK_PIN_NO(53) | 5)
+#define PINMUX_GPIO53__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(53) | 6)
+#define PINMUX_GPIO53__FUNC_JTDI_SEL3 (MTK_PIN_NO(53) | 7)
+
+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define PINMUX_GPIO54__FUNC_MSDC1_DAT2 (MTK_PIN_NO(54) | 1)
+#define PINMUX_GPIO54__FUNC_UDI_NTRST (MTK_PIN_NO(54) | 4)
+#define PINMUX_GPIO54__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(54) | 6)
+#define PINMUX_GPIO54__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(54) | 7)
+
+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define PINMUX_GPIO55__FUNC_MSDC1_DAT1 (MTK_PIN_NO(55) | 1)
+#define PINMUX_GPIO55__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(55) | 2)
+#define PINMUX_GPIO55__FUNC_UDI_TDO_0 (MTK_PIN_NO(55) | 4)
+#define PINMUX_GPIO55__FUNC_CONN_BGF_DSP_L1_JDO (MTK_PIN_NO(55) | 5)
+#define PINMUX_GPIO55__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(55) | 6)
+#define PINMUX_GPIO55__FUNC_JTDO_SEL3 (MTK_PIN_NO(55) | 7)
+
+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define PINMUX_GPIO56__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(56) | 1)
+
+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define PINMUX_GPIO57__FUNC_DIGRF_IRQ (MTK_PIN_NO(57) | 1)
+
+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define PINMUX_GPIO58__FUNC_BPI_BUS0 (MTK_PIN_NO(58) | 1)
+#define PINMUX_GPIO58__FUNC_ANT_SEL0 (MTK_PIN_NO(58) | 4)
+#define PINMUX_GPIO58__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(58) | 6)
+#define PINMUX_GPIO58__FUNC_DBG_MON_A0 (MTK_PIN_NO(58) | 7)
+
+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define PINMUX_GPIO59__FUNC_BPI_BUS1 (MTK_PIN_NO(59) | 1)
+#define PINMUX_GPIO59__FUNC_ANT_SEL1 (MTK_PIN_NO(59) | 4)
+#define PINMUX_GPIO59__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(59) | 6)
+#define PINMUX_GPIO59__FUNC_DBG_MON_A1 (MTK_PIN_NO(59) | 7)
+
+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define PINMUX_GPIO60__FUNC_BPI_BUS2 (MTK_PIN_NO(60) | 1)
+#define PINMUX_GPIO60__FUNC_ANT_SEL2 (MTK_PIN_NO(60) | 4)
+#define PINMUX_GPIO60__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(60) | 6)
+#define PINMUX_GPIO60__FUNC_DBG_MON_A2 (MTK_PIN_NO(60) | 7)
+
+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define PINMUX_GPIO61__FUNC_BPI_BUS3 (MTK_PIN_NO(61) | 1)
+#define PINMUX_GPIO61__FUNC_ANT_SEL3 (MTK_PIN_NO(61) | 4)
+#define PINMUX_GPIO61__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(61) | 6)
+#define PINMUX_GPIO61__FUNC_DBG_MON_A3 (MTK_PIN_NO(61) | 7)
+
+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define PINMUX_GPIO62__FUNC_BPI_BUS4 (MTK_PIN_NO(62) | 1)
+#define PINMUX_GPIO62__FUNC_ANT_SEL4 (MTK_PIN_NO(62) | 4)
+#define PINMUX_GPIO62__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(62) | 6)
+#define PINMUX_GPIO62__FUNC_DBG_MON_A4 (MTK_PIN_NO(62) | 7)
+
+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define PINMUX_GPIO63__FUNC_BPI_BUS5 (MTK_PIN_NO(63) | 1)
+#define PINMUX_GPIO63__FUNC_ANT_SEL5 (MTK_PIN_NO(63) | 4)
+#define PINMUX_GPIO63__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(63) | 6)
+#define PINMUX_GPIO63__FUNC_DBG_MON_A5 (MTK_PIN_NO(63) | 7)
+
+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define PINMUX_GPIO64__FUNC_BPI_BUS6 (MTK_PIN_NO(64) | 1)
+#define PINMUX_GPIO64__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(64) | 2)
+#define PINMUX_GPIO64__FUNC_ANT_SEL6 (MTK_PIN_NO(64) | 4)
+#define PINMUX_GPIO64__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(64) | 6)
+#define PINMUX_GPIO64__FUNC_DBG_MON_A6 (MTK_PIN_NO(64) | 7)
+
+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define PINMUX_GPIO65__FUNC_BPI_BUS7 (MTK_PIN_NO(65) | 1)
+#define PINMUX_GPIO65__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(65) | 2)
+#define PINMUX_GPIO65__FUNC_ANT_SEL7 (MTK_PIN_NO(65) | 4)
+#define PINMUX_GPIO65__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(65) | 6)
+#define PINMUX_GPIO65__FUNC_DBG_MON_A7 (MTK_PIN_NO(65) | 7)
+
+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define PINMUX_GPIO66__FUNC_BPI_BUS8 (MTK_PIN_NO(66) | 1)
+#define PINMUX_GPIO66__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(66) | 2)
+#define PINMUX_GPIO66__FUNC_ANT_SEL8 (MTK_PIN_NO(66) | 4)
+#define PINMUX_GPIO66__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(66) | 6)
+#define PINMUX_GPIO66__FUNC_DBG_MON_A8 (MTK_PIN_NO(66) | 7)
+
+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define PINMUX_GPIO67__FUNC_BPI_BUS9 (MTK_PIN_NO(67) | 1)
+#define PINMUX_GPIO67__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(67) | 2)
+#define PINMUX_GPIO67__FUNC_ANT_SEL9 (MTK_PIN_NO(67) | 4)
+#define PINMUX_GPIO67__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(67) | 6)
+#define PINMUX_GPIO67__FUNC_DBG_MON_A9 (MTK_PIN_NO(67) | 7)
+
+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define PINMUX_GPIO68__FUNC_BPI_BUS10 (MTK_PIN_NO(68) | 1)
+#define PINMUX_GPIO68__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(68) | 2)
+#define PINMUX_GPIO68__FUNC_ANT_SEL10 (MTK_PIN_NO(68) | 4)
+#define PINMUX_GPIO68__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(68) | 6)
+#define PINMUX_GPIO68__FUNC_DBG_MON_A10 (MTK_PIN_NO(68) | 7)
+
+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define PINMUX_GPIO69__FUNC_BPI_BUS11_OLAT0 (MTK_PIN_NO(69) | 1)
+#define PINMUX_GPIO69__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(69) | 2)
+#define PINMUX_GPIO69__FUNC_ANT_SEL11 (MTK_PIN_NO(69) | 4)
+#define PINMUX_GPIO69__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(69) | 6)
+#define PINMUX_GPIO69__FUNC_DBG_MON_A11 (MTK_PIN_NO(69) | 7)
+
+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define PINMUX_GPIO70__FUNC_BPI_BUS12_OLAT1 (MTK_PIN_NO(70) | 1)
+#define PINMUX_GPIO70__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(70) | 2)
+#define PINMUX_GPIO70__FUNC_ANT_SEL12 (MTK_PIN_NO(70) | 4)
+#define PINMUX_GPIO70__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(70) | 6)
+#define PINMUX_GPIO70__FUNC_DBG_MON_A12 (MTK_PIN_NO(70) | 7)
+
+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define PINMUX_GPIO71__FUNC_BPI_BUS13_OLAT2 (MTK_PIN_NO(71) | 1)
+#define PINMUX_GPIO71__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(71) | 2)
+#define PINMUX_GPIO71__FUNC_ANT_SEL13 (MTK_PIN_NO(71) | 4)
+#define PINMUX_GPIO71__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(71) | 6)
+#define PINMUX_GPIO71__FUNC_DBG_MON_A13 (MTK_PIN_NO(71) | 7)
+
+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define PINMUX_GPIO72__FUNC_BPI_BUS14_OLAT3 (MTK_PIN_NO(72) | 1)
+#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(72) | 2)
+#define PINMUX_GPIO72__FUNC_ANT_SEL14 (MTK_PIN_NO(72) | 4)
+#define PINMUX_GPIO72__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(72) | 6)
+#define PINMUX_GPIO72__FUNC_DBG_MON_A14 (MTK_PIN_NO(72) | 7)
+
+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define PINMUX_GPIO73__FUNC_BPI_BUS15_OLAT4 (MTK_PIN_NO(73) | 1)
+#define PINMUX_GPIO73__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(73) | 2)
+#define PINMUX_GPIO73__FUNC_MIPI4_D_SCLK (MTK_PIN_NO(73) | 3)
+#define PINMUX_GPIO73__FUNC_ANT_SEL15 (MTK_PIN_NO(73) | 4)
+#define PINMUX_GPIO73__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(73) | 6)
+#define PINMUX_GPIO73__FUNC_DBG_MON_A15 (MTK_PIN_NO(73) | 7)
+
+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define PINMUX_GPIO74__FUNC_BPI_BUS16_OLAT5 (MTK_PIN_NO(74) | 1)
+#define PINMUX_GPIO74__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(74) | 2)
+#define PINMUX_GPIO74__FUNC_MIPI4_D_SDATA (MTK_PIN_NO(74) | 3)
+#define PINMUX_GPIO74__FUNC_ANT_SEL16 (MTK_PIN_NO(74) | 4)
+#define PINMUX_GPIO74__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(74) | 6)
+#define PINMUX_GPIO74__FUNC_DBG_MON_A16 (MTK_PIN_NO(74) | 7)
+
+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define PINMUX_GPIO75__FUNC_BPI_BUS17_ANT0 (MTK_PIN_NO(75) | 1)
+#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(75) | 2)
+#define PINMUX_GPIO75__FUNC_ANT_SEL17 (MTK_PIN_NO(75) | 4)
+#define PINMUX_GPIO75__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(75) | 6)
+#define PINMUX_GPIO75__FUNC_DBG_MON_A17 (MTK_PIN_NO(75) | 7)
+
+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define PINMUX_GPIO76__FUNC_BPI_BUS18_ANT1 (MTK_PIN_NO(76) | 1)
+#define PINMUX_GPIO76__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(76) | 2)
+#define PINMUX_GPIO76__FUNC_BPI_BUS20_ANT3 (MTK_PIN_NO(76) | 3)
+#define PINMUX_GPIO76__FUNC_ANT_SEL20 (MTK_PIN_NO(76) | 4)
+#define PINMUX_GPIO76__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(76) | 5)
+#define PINMUX_GPIO76__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(76) | 6)
+
+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define PINMUX_GPIO77__FUNC_BPI_BUS19_ANT2 (MTK_PIN_NO(77) | 1)
+#define PINMUX_GPIO77__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(77) | 2)
+#define PINMUX_GPIO77__FUNC_BPI_BUS21_ANT4 (MTK_PIN_NO(77) | 3)
+#define PINMUX_GPIO77__FUNC_ANT_SEL21 (MTK_PIN_NO(77) | 4)
+#define PINMUX_GPIO77__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(77) | 5)
+#define PINMUX_GPIO77__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(77) | 6)
+
+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define PINMUX_GPIO78__FUNC_MIPI3_D_SCLK (MTK_PIN_NO(78) | 1)
+#define PINMUX_GPIO78__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(78) | 2)
+#define PINMUX_GPIO78__FUNC_BPI_BUS20_ANT3 (MTK_PIN_NO(78) | 3)
+#define PINMUX_GPIO78__FUNC_ANT_SEL18 (MTK_PIN_NO(78) | 4)
+#define PINMUX_GPIO78__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(78) | 6)
+#define PINMUX_GPIO78__FUNC_DBG_MON_A18 (MTK_PIN_NO(78) | 7)
+
+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define PINMUX_GPIO79__FUNC_MIPI3_D_SDATA (MTK_PIN_NO(79) | 1)
+#define PINMUX_GPIO79__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(79) | 2)
+#define PINMUX_GPIO79__FUNC_BPI_BUS21_ANT4 (MTK_PIN_NO(79) | 3)
+#define PINMUX_GPIO79__FUNC_ANT_SEL19 (MTK_PIN_NO(79) | 4)
+#define PINMUX_GPIO79__FUNC_DBG_MON_A19 (MTK_PIN_NO(79) | 7)
+
+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define PINMUX_GPIO80__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(80) | 1)
+#define PINMUX_GPIO80__FUNC_DBG_MON_A20 (MTK_PIN_NO(80) | 7)
+
+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define PINMUX_GPIO81__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(81) | 1)
+#define PINMUX_GPIO81__FUNC_DBG_MON_A21 (MTK_PIN_NO(81) | 7)
+
+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define PINMUX_GPIO82__FUNC_MIPI_M_SCLK (MTK_PIN_NO(82) | 1)
+#define PINMUX_GPIO82__FUNC_DBG_MON_A22 (MTK_PIN_NO(82) | 7)
+
+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define PINMUX_GPIO83__FUNC_MIPI_M_SDATA (MTK_PIN_NO(83) | 1)
+#define PINMUX_GPIO83__FUNC_DBG_MON_A23 (MTK_PIN_NO(83) | 7)
+
+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define PINMUX_GPIO84__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(84) | 1)
+#define PINMUX_GPIO84__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(84) | 2)
+#define PINMUX_GPIO84__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(84) | 7)
+
+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define PINMUX_GPIO85__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(85) | 1)
+#define PINMUX_GPIO85__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(85) | 2)
+#define PINMUX_GPIO85__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(85) | 7)
+
+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define PINMUX_GPIO86__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(86) | 1)
+#define PINMUX_GPIO86__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(86) | 2)
+#define PINMUX_GPIO86__FUNC_BPI_BUS20_ANT3 (MTK_PIN_NO(86) | 3)
+#define PINMUX_GPIO86__FUNC_TP_URTS2_VCORE (MTK_PIN_NO(86) | 7)
+
+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define PINMUX_GPIO87__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(87) | 1)
+#define PINMUX_GPIO87__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(87) | 2)
+#define PINMUX_GPIO87__FUNC_BPI_BUS21_ANT4 (MTK_PIN_NO(87) | 3)
+#define PINMUX_GPIO87__FUNC_TP_UCTS2_VCORE (MTK_PIN_NO(87) | 7)
+
+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define PINMUX_GPIO88__FUNC_URXD0 (MTK_PIN_NO(88) | 1)
+#define PINMUX_GPIO88__FUNC_MD_URXD0 (MTK_PIN_NO(88) | 2)
+#define PINMUX_GPIO88__FUNC_MD_URXD1 (MTK_PIN_NO(88) | 3)
+#define PINMUX_GPIO88__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(88) | 4)
+#define PINMUX_GPIO88__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(88) | 5)
+#define PINMUX_GPIO88__FUNC_ANT_SEL19 (MTK_PIN_NO(88) | 6)
+
+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define PINMUX_GPIO89__FUNC_UTXD0 (MTK_PIN_NO(89) | 1)
+#define PINMUX_GPIO89__FUNC_MD_UTXD0 (MTK_PIN_NO(89) | 2)
+#define PINMUX_GPIO89__FUNC_MD_UTXD1 (MTK_PIN_NO(89) | 3)
+#define PINMUX_GPIO89__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(89) | 4)
+#define PINMUX_GPIO89__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(89) | 5)
+#define PINMUX_GPIO89__FUNC_WIFI_TXD (MTK_PIN_NO(89) | 6)
+#define PINMUX_GPIO89__FUNC_CONN_BT_TXD (MTK_PIN_NO(89) | 7)
+
+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define PINMUX_GPIO90__FUNC_URXD1 (MTK_PIN_NO(90) | 1)
+#define PINMUX_GPIO90__FUNC_ADSP_URXD0 (MTK_PIN_NO(90) | 2)
+#define PINMUX_GPIO90__FUNC_MD32_0_RXD (MTK_PIN_NO(90) | 3)
+#define PINMUX_GPIO90__FUNC_MD_URXD0 (MTK_PIN_NO(90) | 4)
+#define PINMUX_GPIO90__FUNC_TP_URXD1_VLP (MTK_PIN_NO(90) | 5)
+#define PINMUX_GPIO90__FUNC_MD32_2_RXD (MTK_PIN_NO(90) | 6)
+#define PINMUX_GPIO90__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(90) | 7)
+
+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define PINMUX_GPIO91__FUNC_UTXD1 (MTK_PIN_NO(91) | 1)
+#define PINMUX_GPIO91__FUNC_ADSP_UTXD0 (MTK_PIN_NO(91) | 2)
+#define PINMUX_GPIO91__FUNC_MD32_0_TXD (MTK_PIN_NO(91) | 3)
+#define PINMUX_GPIO91__FUNC_MD_UTXD0 (MTK_PIN_NO(91) | 4)
+#define PINMUX_GPIO91__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(91) | 5)
+#define PINMUX_GPIO91__FUNC_MD32_2_TXD (MTK_PIN_NO(91) | 6)
+#define PINMUX_GPIO91__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(91) | 7)
+
+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define PINMUX_GPIO92__FUNC_TDMOUT1_LRCK (MTK_PIN_NO(92) | 1)
+#define PINMUX_GPIO92__FUNC_DP_TX_HPD (MTK_PIN_NO(92) | 2)
+#define PINMUX_GPIO92__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(92) | 4)
+#define PINMUX_GPIO92__FUNC_ADSP_JTAG0_TDI (MTK_PIN_NO(92) | 5)
+#define PINMUX_GPIO92__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(92) | 6)
+#define PINMUX_GPIO92__FUNC_IO_JTAG_TDI (MTK_PIN_NO(92) | 7)
+
+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define PINMUX_GPIO93__FUNC_TDMOUT1_BCK (MTK_PIN_NO(93) | 1)
+#define PINMUX_GPIO93__FUNC_DP_OC_EN (MTK_PIN_NO(93) | 2)
+#define PINMUX_GPIO93__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(93) | 4)
+#define PINMUX_GPIO93__FUNC_ADSP_JTAG0_TRSTN (MTK_PIN_NO(93) | 5)
+#define PINMUX_GPIO93__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(93) | 6)
+#define PINMUX_GPIO93__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(93) | 7)
+
+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define PINMUX_GPIO94__FUNC_TDMOUT1_MCK (MTK_PIN_NO(94) | 1)
+#define PINMUX_GPIO94__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(94) | 2)
+#define PINMUX_GPIO94__FUNC_ADSP_JTAG0_TCK (MTK_PIN_NO(94) | 5)
+#define PINMUX_GPIO94__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(94) | 6)
+#define PINMUX_GPIO94__FUNC_IO_JTAG_TCK (MTK_PIN_NO(94) | 7)
+
+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define PINMUX_GPIO95__FUNC_TDMOUT1_DATA0 (MTK_PIN_NO(95) | 1)
+#define PINMUX_GPIO95__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(95) | 2)
+#define PINMUX_GPIO95__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(95) | 3)
+#define PINMUX_GPIO95__FUNC_ADSP_JTAG0_TDO (MTK_PIN_NO(95) | 5)
+#define PINMUX_GPIO95__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(95) | 6)
+#define PINMUX_GPIO95__FUNC_IO_JTAG_TDO (MTK_PIN_NO(95) | 7)
+
+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define PINMUX_GPIO96__FUNC_TDMOUT1_DATA1 (MTK_PIN_NO(96) | 1)
+#define PINMUX_GPIO96__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(96) | 2)
+#define PINMUX_GPIO96__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(96) | 3)
+#define PINMUX_GPIO96__FUNC_ADSP_JTAG0_TMS (MTK_PIN_NO(96) | 5)
+#define PINMUX_GPIO96__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(96) | 6)
+#define PINMUX_GPIO96__FUNC_IO_JTAG_TMS (MTK_PIN_NO(96) | 7)
+
+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define PINMUX_GPIO97__FUNC_TDMOUT1_DATA2 (MTK_PIN_NO(97) | 1)
+#define PINMUX_GPIO97__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(97) | 2)
+#define PINMUX_GPIO97__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(97) | 3)
+#define PINMUX_GPIO97__FUNC_TDMIN1_DATA0 (MTK_PIN_NO(97) | 4)
+#define PINMUX_GPIO97__FUNC_TP_URTS1_VLP (MTK_PIN_NO(97) | 5)
+#define PINMUX_GPIO97__FUNC_TP_GPIO15_AO (MTK_PIN_NO(97) | 6)
+#define PINMUX_GPIO97__FUNC_DAP_MD32_SWD (MTK_PIN_NO(97) | 7)
+
+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define PINMUX_GPIO98__FUNC_TDMOUT1_DATA3 (MTK_PIN_NO(98) | 1)
+#define PINMUX_GPIO98__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(98) | 2)
+#define PINMUX_GPIO98__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(98) | 3)
+#define PINMUX_GPIO98__FUNC_TDMIN1_DATA1 (MTK_PIN_NO(98) | 4)
+#define PINMUX_GPIO98__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(98) | 5)
+#define PINMUX_GPIO98__FUNC_TP_GPIO14_AO (MTK_PIN_NO(98) | 6)
+#define PINMUX_GPIO98__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(98) | 7)
+
+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define PINMUX_GPIO99__FUNC_SPI0_A_MI (MTK_PIN_NO(99) | 1)
+#define PINMUX_GPIO99__FUNC_KPROW1 (MTK_PIN_NO(99) | 2)
+#define PINMUX_GPIO99__FUNC_TDMIN1_BCK (MTK_PIN_NO(99) | 3)
+#define PINMUX_GPIO99__FUNC_TP_GPIO10_AO (MTK_PIN_NO(99) | 4)
+#define PINMUX_GPIO99__FUNC_SPM_JTAG_TDO_VLP (MTK_PIN_NO(99) | 6)
+#define PINMUX_GPIO99__FUNC_JTDO_SEL1 (MTK_PIN_NO(99) | 7)
+
+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define PINMUX_GPIO100__FUNC_SPI0_A_CSB (MTK_PIN_NO(100) | 1)
+#define PINMUX_GPIO100__FUNC_KPROW2 (MTK_PIN_NO(100) | 2)
+#define PINMUX_GPIO100__FUNC_TDMIN1_LRCK (MTK_PIN_NO(100) | 3)
+#define PINMUX_GPIO100__FUNC_TP_GPIO11_AO (MTK_PIN_NO(100) | 4)
+#define PINMUX_GPIO100__FUNC_SPM_JTAG_TMS_VLP (MTK_PIN_NO(100) | 6)
+#define PINMUX_GPIO100__FUNC_JTMS_SEL1 (MTK_PIN_NO(100) | 7)
+
+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define PINMUX_GPIO101__FUNC_SPI0_A_MO (MTK_PIN_NO(101) | 1)
+#define PINMUX_GPIO101__FUNC_KPCOL1 (MTK_PIN_NO(101) | 2)
+#define PINMUX_GPIO101__FUNC_TDMIN1_DATA0 (MTK_PIN_NO(101) | 3)
+#define PINMUX_GPIO101__FUNC_TP_GPIO12_AO (MTK_PIN_NO(101) | 4)
+#define PINMUX_GPIO101__FUNC_SPM_JTAG_TDI_VLP (MTK_PIN_NO(101) | 6)
+#define PINMUX_GPIO101__FUNC_JTDI_SEL1 (MTK_PIN_NO(101) | 7)
+
+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define PINMUX_GPIO102__FUNC_SPI0_A_CLK (MTK_PIN_NO(102) | 1)
+#define PINMUX_GPIO102__FUNC_KPCOL2 (MTK_PIN_NO(102) | 2)
+#define PINMUX_GPIO102__FUNC_TDMIN1_DATA1 (MTK_PIN_NO(102) | 3)
+#define PINMUX_GPIO102__FUNC_TP_GPIO13_AO (MTK_PIN_NO(102) | 4)
+#define PINMUX_GPIO102__FUNC_SPM_JTAG_TCK_VLP (MTK_PIN_NO(102) | 6)
+#define PINMUX_GPIO102__FUNC_JTCK_SEL1 (MTK_PIN_NO(102) | 7)
+
+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define PINMUX_GPIO103__FUNC_DMIC_CLK (MTK_PIN_NO(103) | 1)
+#define PINMUX_GPIO103__FUNC_SPI0_A_WP (MTK_PIN_NO(103) | 2)
+#define PINMUX_GPIO103__FUNC_TDMIN1_DATA2 (MTK_PIN_NO(103) | 3)
+#define PINMUX_GPIO103__FUNC_TP_GPIO10_AO (MTK_PIN_NO(103) | 4)
+#define PINMUX_GPIO103__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(103) | 5)
+#define PINMUX_GPIO103__FUNC_SPM_JTAG_TRSTN_VLP (MTK_PIN_NO(103) | 6)
+#define PINMUX_GPIO103__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(103) | 7)
+
+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define PINMUX_GPIO104__FUNC_DMIC_DAT (MTK_PIN_NO(104) | 1)
+#define PINMUX_GPIO104__FUNC_SPI0_A_HOLD (MTK_PIN_NO(104) | 2)
+#define PINMUX_GPIO104__FUNC_TDMIN1_DATA3 (MTK_PIN_NO(104) | 3)
+#define PINMUX_GPIO104__FUNC_TP_GPIO9_AO (MTK_PIN_NO(104) | 4)
+#define PINMUX_GPIO104__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(104) | 5)
+#define PINMUX_GPIO104__FUNC_ANT_SEL20 (MTK_PIN_NO(104) | 6)
+#define PINMUX_GPIO104__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(104) | 7)
+
+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define PINMUX_GPIO105__FUNC_KPROW1 (MTK_PIN_NO(105) | 1)
+#define PINMUX_GPIO105__FUNC_TP_GPIO11_AO (MTK_PIN_NO(105) | 2)
+#define PINMUX_GPIO105__FUNC_TDMIN1_MCK (MTK_PIN_NO(105) | 3)
+#define PINMUX_GPIO105__FUNC_TP_GPIO8_AO (MTK_PIN_NO(105) | 4)
+#define PINMUX_GPIO105__FUNC_SRCLKENAI1 (MTK_PIN_NO(105) | 5)
+#define PINMUX_GPIO105__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(105) | 6)
+#define PINMUX_GPIO105__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(105) | 7)
+
+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define PINMUX_GPIO106__FUNC_KPROW0 (MTK_PIN_NO(106) | 1)
+
+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define PINMUX_GPIO107__FUNC_KPCOL0 (MTK_PIN_NO(107) | 1)
+
+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define PINMUX_GPIO108__FUNC_KPCOL1 (MTK_PIN_NO(108) | 1)
+#define PINMUX_GPIO108__FUNC_TP_GPIO10_AO (MTK_PIN_NO(108) | 2)
+#define PINMUX_GPIO108__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(108) | 3)
+#define PINMUX_GPIO108__FUNC_TP_GPIO7_AO (MTK_PIN_NO(108) | 4)
+#define PINMUX_GPIO108__FUNC_SRCLKENAI0 (MTK_PIN_NO(108) | 5)
+#define PINMUX_GPIO108__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(108) | 6)
+#define PINMUX_GPIO108__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(108) | 7)
+
+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define PINMUX_GPIO109__FUNC_SPI2_A_MI (MTK_PIN_NO(109) | 1)
+#define PINMUX_GPIO109__FUNC_SCP_SPI2_A_MI (MTK_PIN_NO(109) | 2)
+#define PINMUX_GPIO109__FUNC_TP_GPIO6_AO (MTK_PIN_NO(109) | 4)
+#define PINMUX_GPIO109__FUNC_SCP_SDA6 (MTK_PIN_NO(109) | 5)
+#define PINMUX_GPIO109__FUNC_MD_URXD0 (MTK_PIN_NO(109) | 6)
+
+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define PINMUX_GPIO110__FUNC_SPI2_A_CSB (MTK_PIN_NO(110) | 1)
+#define PINMUX_GPIO110__FUNC_SCP_SPI2_A_CS (MTK_PIN_NO(110) | 2)
+#define PINMUX_GPIO110__FUNC_TP_GPIO5_AO (MTK_PIN_NO(110) | 4)
+#define PINMUX_GPIO110__FUNC_SCP_SCL6 (MTK_PIN_NO(110) | 5)
+#define PINMUX_GPIO110__FUNC_MD_UTXD0 (MTK_PIN_NO(110) | 6)
+
+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define PINMUX_GPIO111__FUNC_SPI2_A_MO (MTK_PIN_NO(111) | 1)
+#define PINMUX_GPIO111__FUNC_SCP_SPI2_A_MO (MTK_PIN_NO(111) | 2)
+#define PINMUX_GPIO111__FUNC_PWM_VLP (MTK_PIN_NO(111) | 3)
+#define PINMUX_GPIO111__FUNC_TP_GPIO4_AO (MTK_PIN_NO(111) | 4)
+#define PINMUX_GPIO111__FUNC_SCP_SDA5 (MTK_PIN_NO(111) | 5)
+
+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define PINMUX_GPIO112__FUNC_SPI2_A_CLK (MTK_PIN_NO(112) | 1)
+#define PINMUX_GPIO112__FUNC_SCP_SPI2_A_CK (MTK_PIN_NO(112) | 2)
+#define PINMUX_GPIO112__FUNC_TP_GPIO3_AO (MTK_PIN_NO(112) | 4)
+#define PINMUX_GPIO112__FUNC_SCP_SCL5 (MTK_PIN_NO(112) | 5)
+
+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define PINMUX_GPIO113__FUNC_AP_GOOD (MTK_PIN_NO(113) | 1)
+#define PINMUX_GPIO113__FUNC_CLKM1 (MTK_PIN_NO(113) | 2)
+#define PINMUX_GPIO113__FUNC_ANT_SEL19 (MTK_PIN_NO(113) | 3)
+#define PINMUX_GPIO113__FUNC_AGPS_SYNC (MTK_PIN_NO(113) | 4)
+#define PINMUX_GPIO113__FUNC_GPS_PPS (MTK_PIN_NO(113) | 5)
+#define PINMUX_GPIO113__FUNC_IDDIG (MTK_PIN_NO(113) | 6)
+#define PINMUX_GPIO113__FUNC_ANT_SEL4 (MTK_PIN_NO(113) | 7)
+
+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define PINMUX_GPIO114__FUNC_I2S1_MCK (MTK_PIN_NO(114) | 1)
+#define PINMUX_GPIO114__FUNC_I2S3_MCK (MTK_PIN_NO(114) | 2)
+#define PINMUX_GPIO114__FUNC_MFG_EB_JTAG_TRSTN (MTK_PIN_NO(114) | 3)
+#define PINMUX_GPIO114__FUNC_MFG_UDI_NTRST (MTK_PIN_NO(114) | 4)
+#define PINMUX_GPIO114__FUNC_HFRP_JTAG0_TRSTN (MTK_PIN_NO(114) | 5)
+#define PINMUX_GPIO114__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(114) | 6)
+
+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define PINMUX_GPIO115__FUNC_I2S1_BCK (MTK_PIN_NO(115) | 1)
+#define PINMUX_GPIO115__FUNC_I2S3_BCK (MTK_PIN_NO(115) | 2)
+#define PINMUX_GPIO115__FUNC_MFG_EB_JTAG_TMS (MTK_PIN_NO(115) | 3)
+#define PINMUX_GPIO115__FUNC_MFG_UDI_TMS (MTK_PIN_NO(115) | 4)
+#define PINMUX_GPIO115__FUNC_HFRP_JTAG0_TMS (MTK_PIN_NO(115) | 5)
+#define PINMUX_GPIO115__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(115) | 6)
+#define PINMUX_GPIO115__FUNC_PCM1_CLK (MTK_PIN_NO(115) | 7)
+
+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define PINMUX_GPIO116__FUNC_I2S1_LRCK (MTK_PIN_NO(116) | 1)
+#define PINMUX_GPIO116__FUNC_I2S3_LRCK (MTK_PIN_NO(116) | 2)
+#define PINMUX_GPIO116__FUNC_MFG_EB_JTAG_TCK (MTK_PIN_NO(116) | 3)
+#define PINMUX_GPIO116__FUNC_MFG_UDI_TCK (MTK_PIN_NO(116) | 4)
+#define PINMUX_GPIO116__FUNC_HFRP_JTAG0_TCK (MTK_PIN_NO(116) | 5)
+#define PINMUX_GPIO116__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(116) | 6)
+#define PINMUX_GPIO116__FUNC_PCM1_SYNC (MTK_PIN_NO(116) | 7)
+
+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define PINMUX_GPIO117__FUNC_I2S2_DI (MTK_PIN_NO(117) | 1)
+#define PINMUX_GPIO117__FUNC_I2S0_DI (MTK_PIN_NO(117) | 2)
+#define PINMUX_GPIO117__FUNC_MFG_EB_JTAG_TDI (MTK_PIN_NO(117) | 3)
+#define PINMUX_GPIO117__FUNC_MFG_UDI_TDI (MTK_PIN_NO(117) | 4)
+#define PINMUX_GPIO117__FUNC_HFRP_JTAG0_TDI (MTK_PIN_NO(117) | 5)
+#define PINMUX_GPIO117__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(117) | 6)
+#define PINMUX_GPIO117__FUNC_PCM1_DI (MTK_PIN_NO(117) | 7)
+
+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define PINMUX_GPIO118__FUNC_I2S1_DO (MTK_PIN_NO(118) | 1)
+#define PINMUX_GPIO118__FUNC_I2S3_DO (MTK_PIN_NO(118) | 2)
+#define PINMUX_GPIO118__FUNC_MFG_EB_JTAG_TDO (MTK_PIN_NO(118) | 3)
+#define PINMUX_GPIO118__FUNC_MFG_UDI_TDO (MTK_PIN_NO(118) | 4)
+#define PINMUX_GPIO118__FUNC_HFRP_JTAG0_TDO (MTK_PIN_NO(118) | 5)
+#define PINMUX_GPIO118__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(118) | 6)
+#define PINMUX_GPIO118__FUNC_PCM1_DO0 (MTK_PIN_NO(118) | 7)
+
+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define PINMUX_GPIO119__FUNC_CMFLASH0 (MTK_PIN_NO(119) | 1)
+#define PINMUX_GPIO119__FUNC_UCTS0 (MTK_PIN_NO(119) | 2)
+#define PINMUX_GPIO119__FUNC_CLKM0 (MTK_PIN_NO(119) | 3)
+#define PINMUX_GPIO119__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(119) | 4)
+#define PINMUX_GPIO119__FUNC_ANT_SEL2 (MTK_PIN_NO(119) | 5)
+#define PINMUX_GPIO119__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(119) | 6)
+#define PINMUX_GPIO119__FUNC_PCM1_DO1 (MTK_PIN_NO(119) | 7)
+
+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define PINMUX_GPIO120__FUNC_CMFLASH1 (MTK_PIN_NO(120) | 1)
+#define PINMUX_GPIO120__FUNC_URTS0 (MTK_PIN_NO(120) | 2)
+#define PINMUX_GPIO120__FUNC_CLKM3 (MTK_PIN_NO(120) | 3)
+#define PINMUX_GPIO120__FUNC_PWM_1 (MTK_PIN_NO(120) | 4)
+#define PINMUX_GPIO120__FUNC_ANT_SEL1 (MTK_PIN_NO(120) | 5)
+#define PINMUX_GPIO120__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(120) | 6)
+#define PINMUX_GPIO120__FUNC_PCM1_DO2 (MTK_PIN_NO(120) | 7)
+
+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define PINMUX_GPIO121__FUNC_CMFLASH2 (MTK_PIN_NO(121) | 1)
+#define PINMUX_GPIO121__FUNC_UCTS1 (MTK_PIN_NO(121) | 2)
+#define PINMUX_GPIO121__FUNC_HFRP_URTS1 (MTK_PIN_NO(121) | 3)
+#define PINMUX_GPIO121__FUNC_PWM_2 (MTK_PIN_NO(121) | 4)
+#define PINMUX_GPIO121__FUNC_ANT_SEL0 (MTK_PIN_NO(121) | 5)
+#define PINMUX_GPIO121__FUNC_ANT_SEL5 (MTK_PIN_NO(121) | 6)
+
+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define PINMUX_GPIO122__FUNC_CMFLASH3 (MTK_PIN_NO(122) | 1)
+#define PINMUX_GPIO122__FUNC_URTS1 (MTK_PIN_NO(122) | 2)
+#define PINMUX_GPIO122__FUNC_HFRP_UCTS1 (MTK_PIN_NO(122) | 3)
+#define PINMUX_GPIO122__FUNC_PWM_3 (MTK_PIN_NO(122) | 4)
+#define PINMUX_GPIO122__FUNC_ANT_SEL21 (MTK_PIN_NO(122) | 5)
+#define PINMUX_GPIO122__FUNC_ANT_SEL6 (MTK_PIN_NO(122) | 6)
+
+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define PINMUX_GPIO123__FUNC_SCP_SPI0_A_CK (MTK_PIN_NO(123) | 1)
+#define PINMUX_GPIO123__FUNC_SPI6_A_CLK (MTK_PIN_NO(123) | 2)
+#define PINMUX_GPIO123__FUNC_MRG_CLK (MTK_PIN_NO(123) | 3)
+#define PINMUX_GPIO123__FUNC_ANT_SEL5 (MTK_PIN_NO(123) | 5)
+#define PINMUX_GPIO123__FUNC_PWM_0 (MTK_PIN_NO(123) | 6)
+
+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define PINMUX_GPIO124__FUNC_SCP_SPI0_A_CS (MTK_PIN_NO(124) | 1)
+#define PINMUX_GPIO124__FUNC_SPI6_A_CSB (MTK_PIN_NO(124) | 2)
+#define PINMUX_GPIO124__FUNC_MRG_SYNC (MTK_PIN_NO(124) | 3)
+#define PINMUX_GPIO124__FUNC_PWM_1 (MTK_PIN_NO(124) | 6)
+
+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define PINMUX_GPIO125__FUNC_SCP_SPI0_A_MI (MTK_PIN_NO(125) | 1)
+#define PINMUX_GPIO125__FUNC_SPI6_A_MI (MTK_PIN_NO(125) | 2)
+#define PINMUX_GPIO125__FUNC_MRG_DI (MTK_PIN_NO(125) | 3)
+#define PINMUX_GPIO125__FUNC_PWM_2 (MTK_PIN_NO(125) | 6)
+
+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define PINMUX_GPIO126__FUNC_SCP_SPI0_A_MO (MTK_PIN_NO(126) | 1)
+#define PINMUX_GPIO126__FUNC_SPI6_A_MO (MTK_PIN_NO(126) | 2)
+#define PINMUX_GPIO126__FUNC_MRG_DO (MTK_PIN_NO(126) | 3)
+#define PINMUX_GPIO126__FUNC_PWM_3 (MTK_PIN_NO(126) | 6)
+
+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define PINMUX_GPIO127__FUNC_SPI7_A_MO (MTK_PIN_NO(127) | 1)
+#define PINMUX_GPIO127__FUNC_ANT_SEL18 (MTK_PIN_NO(127) | 2)
+#define PINMUX_GPIO127__FUNC_PTA_EXT_PRI (MTK_PIN_NO(127) | 3)
+#define PINMUX_GPIO127__FUNC_SDA1 (MTK_PIN_NO(127) | 4)
+#define PINMUX_GPIO127__FUNC_I2S2_BCK (MTK_PIN_NO(127) | 5)
+#define PINMUX_GPIO127__FUNC_DBG_MON_B27 (MTK_PIN_NO(127) | 7)
+
+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define PINMUX_GPIO128__FUNC_SPI7_A_CLK (MTK_PIN_NO(128) | 1)
+#define PINMUX_GPIO128__FUNC_ANT_SEL19 (MTK_PIN_NO(128) | 2)
+#define PINMUX_GPIO128__FUNC_PTA_EXT_WLAN_ACT (MTK_PIN_NO(128) | 3)
+#define PINMUX_GPIO128__FUNC_SCL1 (MTK_PIN_NO(128) | 4)
+#define PINMUX_GPIO128__FUNC_I2S2_LRCK (MTK_PIN_NO(128) | 5)
+#define PINMUX_GPIO128__FUNC_DBG_MON_B28 (MTK_PIN_NO(128) | 7)
+
+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define PINMUX_GPIO129__FUNC_SCL3 (MTK_PIN_NO(129) | 1)
+#define PINMUX_GPIO129__FUNC_ANT_SEL9 (MTK_PIN_NO(129) | 2)
+#define PINMUX_GPIO129__FUNC_DBG_MON_A24 (MTK_PIN_NO(129) | 7)
+
+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define PINMUX_GPIO130__FUNC_SDA3 (MTK_PIN_NO(130) | 1)
+#define PINMUX_GPIO130__FUNC_ANT_SEL10 (MTK_PIN_NO(130) | 2)
+#define PINMUX_GPIO130__FUNC_DBG_MON_A25 (MTK_PIN_NO(130) | 7)
+
+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define PINMUX_GPIO131__FUNC_SCL9 (MTK_PIN_NO(131) | 1)
+#define PINMUX_GPIO131__FUNC_UDI_TDO_6 (MTK_PIN_NO(131) | 2)
+#define PINMUX_GPIO131__FUNC_DBG_MON_A26 (MTK_PIN_NO(131) | 7)
+
+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define PINMUX_GPIO132__FUNC_SDA9 (MTK_PIN_NO(132) | 1)
+#define PINMUX_GPIO132__FUNC_UDI_TDO_7 (MTK_PIN_NO(132) | 2)
+#define PINMUX_GPIO132__FUNC_DBG_MON_A27 (MTK_PIN_NO(132) | 7)
+
+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define PINMUX_GPIO133__FUNC_SCL8 (MTK_PIN_NO(133) | 1)
+#define PINMUX_GPIO133__FUNC_UDI_TDO_4 (MTK_PIN_NO(133) | 2)
+#define PINMUX_GPIO133__FUNC_DBG_MON_A28 (MTK_PIN_NO(133) | 7)
+
+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define PINMUX_GPIO134__FUNC_SDA8 (MTK_PIN_NO(134) | 1)
+#define PINMUX_GPIO134__FUNC_UDI_TDO_5 (MTK_PIN_NO(134) | 2)
+
+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define PINMUX_GPIO135__FUNC_SCL0 (MTK_PIN_NO(135) | 1)
+#define PINMUX_GPIO135__FUNC_ANT_SEL20 (MTK_PIN_NO(135) | 2)
+#define PINMUX_GPIO135__FUNC_AGPS_SYNC (MTK_PIN_NO(135) | 3)
+#define PINMUX_GPIO135__FUNC_SCL7 (MTK_PIN_NO(135) | 4)
+#define PINMUX_GPIO135__FUNC_I2S2_DI2 (MTK_PIN_NO(135) | 5)
+#define PINMUX_GPIO135__FUNC_DBG_MON_B29 (MTK_PIN_NO(135) | 7)
+
+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define PINMUX_GPIO136__FUNC_SDA0 (MTK_PIN_NO(136) | 1)
+#define PINMUX_GPIO136__FUNC_ANT_SEL21 (MTK_PIN_NO(136) | 2)
+#define PINMUX_GPIO136__FUNC_SDA7 (MTK_PIN_NO(136) | 4)
+#define PINMUX_GPIO136__FUNC_I2S5_DO (MTK_PIN_NO(136) | 5)
+#define PINMUX_GPIO136__FUNC_DBG_MON_B30 (MTK_PIN_NO(136) | 7)
+
+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define PINMUX_GPIO137__FUNC_SCL4 (MTK_PIN_NO(137) | 1)
+#define PINMUX_GPIO137__FUNC_UDI_TDO_2 (MTK_PIN_NO(137) | 2)
+#define PINMUX_GPIO137__FUNC_DBG_MON_A29 (MTK_PIN_NO(137) | 7)
+
+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define PINMUX_GPIO138__FUNC_SDA4 (MTK_PIN_NO(138) | 1)
+#define PINMUX_GPIO138__FUNC_UDI_TDO_3 (MTK_PIN_NO(138) | 2)
+#define PINMUX_GPIO138__FUNC_DBG_MON_A30 (MTK_PIN_NO(138) | 7)
+
+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define PINMUX_GPIO139__FUNC_SCL2 (MTK_PIN_NO(139) | 1)
+#define PINMUX_GPIO139__FUNC_DBG_MON_A31 (MTK_PIN_NO(139) | 7)
+
+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define PINMUX_GPIO140__FUNC_SDA2 (MTK_PIN_NO(140) | 1)
+#define PINMUX_GPIO140__FUNC_UDI_TDO_1 (MTK_PIN_NO(140) | 2)
+#define PINMUX_GPIO140__FUNC_DBG_MON_A32 (MTK_PIN_NO(140) | 7)
+
+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define PINMUX_GPIO141__FUNC_CMVREF6 (MTK_PIN_NO(141) | 1)
+#define PINMUX_GPIO141__FUNC_SPI3_B_CLK (MTK_PIN_NO(141) | 2)
+#define PINMUX_GPIO141__FUNC_DMIC1_CLK (MTK_PIN_NO(141) | 3)
+#define PINMUX_GPIO141__FUNC_ANT_SEL16 (MTK_PIN_NO(141) | 4)
+#define PINMUX_GPIO141__FUNC_APU_JTAG_TDI (MTK_PIN_NO(141) | 5)
+#define PINMUX_GPIO141__FUNC_IDDIG (MTK_PIN_NO(141) | 6)
+#define PINMUX_GPIO141__FUNC_DBG_MON_B0 (MTK_PIN_NO(141) | 7)
+
+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define PINMUX_GPIO142__FUNC_CMVREF5 (MTK_PIN_NO(142) | 1)
+#define PINMUX_GPIO142__FUNC_SPI3_B_CSB (MTK_PIN_NO(142) | 2)
+#define PINMUX_GPIO142__FUNC_DMIC1_DAT (MTK_PIN_NO(142) | 3)
+#define PINMUX_GPIO142__FUNC_ANT_SEL17 (MTK_PIN_NO(142) | 4)
+#define PINMUX_GPIO142__FUNC_APU_JTAG_TMS (MTK_PIN_NO(142) | 5)
+#define PINMUX_GPIO142__FUNC_USB_DRVVBUS (MTK_PIN_NO(142) | 6)
+#define PINMUX_GPIO142__FUNC_DBG_MON_B1 (MTK_PIN_NO(142) | 7)
+
+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define PINMUX_GPIO143__FUNC_CMVREF6 (MTK_PIN_NO(143) | 1)
+#define PINMUX_GPIO143__FUNC_SPI3_B_MI (MTK_PIN_NO(143) | 2)
+#define PINMUX_GPIO143__FUNC_CLKM0 (MTK_PIN_NO(143) | 3)
+#define PINMUX_GPIO143__FUNC_ANT_SEL18 (MTK_PIN_NO(143) | 4)
+#define PINMUX_GPIO143__FUNC_APU_JTAG_TDO (MTK_PIN_NO(143) | 5)
+#define PINMUX_GPIO143__FUNC_DBG_MON_B2 (MTK_PIN_NO(143) | 7)
+
+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define PINMUX_GPIO144__FUNC_CMVREF4 (MTK_PIN_NO(144) | 1)
+#define PINMUX_GPIO144__FUNC_SPI3_B_MO (MTK_PIN_NO(144) | 2)
+#define PINMUX_GPIO144__FUNC_PMSR_SMAP (MTK_PIN_NO(144) | 3)
+#define PINMUX_GPIO144__FUNC_ANT_SEL19 (MTK_PIN_NO(144) | 4)
+#define PINMUX_GPIO144__FUNC_APU_JTAG_TRST (MTK_PIN_NO(144) | 5)
+#define PINMUX_GPIO144__FUNC_AGPS_SYNC (MTK_PIN_NO(144) | 6)
+#define PINMUX_GPIO144__FUNC_DBG_MON_B3 (MTK_PIN_NO(144) | 7)
+
+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define PINMUX_GPIO145__FUNC_CMMCLK6 (MTK_PIN_NO(145) | 1)
+#define PINMUX_GPIO145__FUNC_CMVREF6 (MTK_PIN_NO(145) | 2)
+#define PINMUX_GPIO145__FUNC_CMVREF3 (MTK_PIN_NO(145) | 3)
+#define PINMUX_GPIO145__FUNC_ANT_SEL20 (MTK_PIN_NO(145) | 4)
+#define PINMUX_GPIO145__FUNC_APU_JTAG_TCK (MTK_PIN_NO(145) | 5)
+#define PINMUX_GPIO145__FUNC_DBG_MON_B4 (MTK_PIN_NO(145) | 7)
+
+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define PINMUX_GPIO146__FUNC_CMMCLK5 (MTK_PIN_NO(146) | 1)
+#define PINMUX_GPIO146__FUNC_CMVREF4 (MTK_PIN_NO(146) | 3)
+#define PINMUX_GPIO146__FUNC_ANT_SEL21 (MTK_PIN_NO(146) | 4)
+#define PINMUX_GPIO146__FUNC_CONN_BT_TXD (MTK_PIN_NO(146) | 5)
+#define PINMUX_GPIO146__FUNC_AGPS_SYNC (MTK_PIN_NO(146) | 6)
+#define PINMUX_GPIO146__FUNC_DBG_MON_B5 (MTK_PIN_NO(146) | 7)
+
+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define PINMUX_GPIO147__FUNC_CMVREF0 (MTK_PIN_NO(147) | 1)
+#define PINMUX_GPIO147__FUNC_ANT_SEL16 (MTK_PIN_NO(147) | 2)
+#define PINMUX_GPIO147__FUNC_ADSP_JTAG1_TCK (MTK_PIN_NO(147) | 3)
+#define PINMUX_GPIO147__FUNC_MD32_3_JTAG_TCK (MTK_PIN_NO(147) | 4)
+#define PINMUX_GPIO147__FUNC_MD32_1_JTAG_TCK (MTK_PIN_NO(147) | 5)
+#define PINMUX_GPIO147__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(147) | 6)
+#define PINMUX_GPIO147__FUNC_DBG_MON_B6 (MTK_PIN_NO(147) | 7)
+
+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define PINMUX_GPIO148__FUNC_CMVREF1 (MTK_PIN_NO(148) | 1)
+#define PINMUX_GPIO148__FUNC_ANT_SEL15 (MTK_PIN_NO(148) | 2)
+#define PINMUX_GPIO148__FUNC_ADSP_JTAG1_TMS (MTK_PIN_NO(148) | 3)
+#define PINMUX_GPIO148__FUNC_MD32_3_JTAG_TMS (MTK_PIN_NO(148) | 4)
+#define PINMUX_GPIO148__FUNC_MD32_1_JTAG_TMS (MTK_PIN_NO(148) | 5)
+#define PINMUX_GPIO148__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(148) | 6)
+#define PINMUX_GPIO148__FUNC_DBG_MON_B7 (MTK_PIN_NO(148) | 7)
+
+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define PINMUX_GPIO149__FUNC_CMVREF2 (MTK_PIN_NO(149) | 1)
+#define PINMUX_GPIO149__FUNC_ANT_SEL14 (MTK_PIN_NO(149) | 2)
+#define PINMUX_GPIO149__FUNC_ADSP_JTAG1_TRSTN (MTK_PIN_NO(149) | 3)
+#define PINMUX_GPIO149__FUNC_MD32_3_JTAG_TRST (MTK_PIN_NO(149) | 4)
+#define PINMUX_GPIO149__FUNC_MD32_1_JTAG_TRST (MTK_PIN_NO(149) | 5)
+#define PINMUX_GPIO149__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(149) | 6)
+#define PINMUX_GPIO149__FUNC_DBG_MON_B8 (MTK_PIN_NO(149) | 7)
+
+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define PINMUX_GPIO150__FUNC_CMMCLK0 (MTK_PIN_NO(150) | 1)
+#define PINMUX_GPIO150__FUNC_UDI_TDI_4 (MTK_PIN_NO(150) | 2)
+#define PINMUX_GPIO150__FUNC_ADSP_JTAG1_TDO (MTK_PIN_NO(150) | 3)
+#define PINMUX_GPIO150__FUNC_MD32_3_JTAG_TDO (MTK_PIN_NO(150) | 4)
+#define PINMUX_GPIO150__FUNC_MD32_1_JTAG_TDO (MTK_PIN_NO(150) | 5)
+#define PINMUX_GPIO150__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(150) | 6)
+#define PINMUX_GPIO150__FUNC_DBG_MON_B9 (MTK_PIN_NO(150) | 7)
+
+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define PINMUX_GPIO151__FUNC_CMMCLK1 (MTK_PIN_NO(151) | 1)
+#define PINMUX_GPIO151__FUNC_UDI_TDI_5 (MTK_PIN_NO(151) | 2)
+#define PINMUX_GPIO151__FUNC_ADSP_JTAG1_TDI (MTK_PIN_NO(151) | 3)
+#define PINMUX_GPIO151__FUNC_MD32_3_JTAG_TDI (MTK_PIN_NO(151) | 4)
+#define PINMUX_GPIO151__FUNC_MD32_1_JTAG_TDI (MTK_PIN_NO(151) | 5)
+#define PINMUX_GPIO151__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(151) | 6)
+#define PINMUX_GPIO151__FUNC_DBG_MON_B10 (MTK_PIN_NO(151) | 7)
+
+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define PINMUX_GPIO152__FUNC_CMMCLK2 (MTK_PIN_NO(152) | 1)
+#define PINMUX_GPIO152__FUNC_UDI_TDI_6 (MTK_PIN_NO(152) | 2)
+#define PINMUX_GPIO152__FUNC_SPI5_A_CLK (MTK_PIN_NO(152) | 3)
+#define PINMUX_GPIO152__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(152) | 6)
+#define PINMUX_GPIO152__FUNC_DBG_MON_B11 (MTK_PIN_NO(152) | 7)
+
+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 1)
+#define PINMUX_GPIO153__FUNC_ANT_SEL13 (MTK_PIN_NO(153) | 2)
+#define PINMUX_GPIO153__FUNC_SPI5_A_CSB (MTK_PIN_NO(153) | 3)
+#define PINMUX_GPIO153__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(153) | 4)
+#define PINMUX_GPIO153__FUNC_MD32_2_GPIO0 (MTK_PIN_NO(153) | 5)
+#define PINMUX_GPIO153__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(153) | 6)
+
+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define PINMUX_GPIO154__FUNC_CMVREF1 (MTK_PIN_NO(154) | 1)
+#define PINMUX_GPIO154__FUNC_UDI_TDI_1 (MTK_PIN_NO(154) | 2)
+#define PINMUX_GPIO154__FUNC_SPI5_A_MI (MTK_PIN_NO(154) | 3)
+#define PINMUX_GPIO154__FUNC_MD32_0_GPIO1 (MTK_PIN_NO(154) | 4)
+#define PINMUX_GPIO154__FUNC_MD32_2_GPIO1 (MTK_PIN_NO(154) | 5)
+#define PINMUX_GPIO154__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(154) | 6)
+
+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define PINMUX_GPIO155__FUNC_CMVREF2 (MTK_PIN_NO(155) | 1)
+#define PINMUX_GPIO155__FUNC_UDI_TDI_2 (MTK_PIN_NO(155) | 2)
+#define PINMUX_GPIO155__FUNC_SPI5_A_MO (MTK_PIN_NO(155) | 3)
+#define PINMUX_GPIO155__FUNC_MD32_0_GPIO2 (MTK_PIN_NO(155) | 4)
+#define PINMUX_GPIO155__FUNC_MD32_2_GPIO2 (MTK_PIN_NO(155) | 5)
+#define PINMUX_GPIO155__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(155) | 6)
+
+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define PINMUX_GPIO156__FUNC_CMVREF3 (MTK_PIN_NO(156) | 1)
+#define PINMUX_GPIO156__FUNC_UDI_TDI_3 (MTK_PIN_NO(156) | 2)
+#define PINMUX_GPIO156__FUNC_SPI7_B_CLK (MTK_PIN_NO(156) | 3)
+#define PINMUX_GPIO156__FUNC_MD32_0_JTAG_TDO (MTK_PIN_NO(156) | 4)
+#define PINMUX_GPIO156__FUNC_MD32_2_JTAG_TDO (MTK_PIN_NO(156) | 5)
+#define PINMUX_GPIO156__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(156) | 6)
+#define PINMUX_GPIO156__FUNC_MSDC1_CLK_A (MTK_PIN_NO(156) | 7)
+
+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define PINMUX_GPIO157__FUNC_CMVREF4 (MTK_PIN_NO(157) | 1)
+#define PINMUX_GPIO157__FUNC_ANT_SEL12 (MTK_PIN_NO(157) | 2)
+#define PINMUX_GPIO157__FUNC_SPI7_B_CSB (MTK_PIN_NO(157) | 3)
+#define PINMUX_GPIO157__FUNC_MD32_0_JTAG_TDI (MTK_PIN_NO(157) | 4)
+#define PINMUX_GPIO157__FUNC_MD32_2_JTAG_TDI (MTK_PIN_NO(157) | 5)
+#define PINMUX_GPIO157__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(157) | 6)
+#define PINMUX_GPIO157__FUNC_MSDC1_CMD_A (MTK_PIN_NO(157) | 7)
+
+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define PINMUX_GPIO158__FUNC_CMVREF5 (MTK_PIN_NO(158) | 1)
+#define PINMUX_GPIO158__FUNC_ANT_SEL11 (MTK_PIN_NO(158) | 2)
+#define PINMUX_GPIO158__FUNC_SPI7_B_MI (MTK_PIN_NO(158) | 3)
+#define PINMUX_GPIO158__FUNC_MD32_0_JTAG_TMS (MTK_PIN_NO(158) | 4)
+#define PINMUX_GPIO158__FUNC_MD32_2_JTAG_TMS (MTK_PIN_NO(158) | 5)
+#define PINMUX_GPIO158__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(158) | 6)
+#define PINMUX_GPIO158__FUNC_MSDC1_DAT3_A (MTK_PIN_NO(158) | 7)
+
+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define PINMUX_GPIO159__FUNC_CMVREF3 (MTK_PIN_NO(159) | 1)
+#define PINMUX_GPIO159__FUNC_ANT_SEL11 (MTK_PIN_NO(159) | 2)
+#define PINMUX_GPIO159__FUNC_SPI7_B_MO (MTK_PIN_NO(159) | 3)
+#define PINMUX_GPIO159__FUNC_MD32_0_JTAG_TCK (MTK_PIN_NO(159) | 4)
+#define PINMUX_GPIO159__FUNC_MD32_2_JTAG_TCK (MTK_PIN_NO(159) | 5)
+#define PINMUX_GPIO159__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(159) | 6)
+#define PINMUX_GPIO159__FUNC_MSDC1_DAT0_A (MTK_PIN_NO(159) | 7)
+
+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define PINMUX_GPIO160__FUNC_CMVREF4 (MTK_PIN_NO(160) | 1)
+#define PINMUX_GPIO160__FUNC_ANT_SEL12 (MTK_PIN_NO(160) | 2)
+#define PINMUX_GPIO160__FUNC_MD32_0_JTAG_TRST (MTK_PIN_NO(160) | 4)
+#define PINMUX_GPIO160__FUNC_MD32_2_JTAG_TRST (MTK_PIN_NO(160) | 5)
+#define PINMUX_GPIO160__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(160) | 6)
+#define PINMUX_GPIO160__FUNC_MSDC1_DAT2_A (MTK_PIN_NO(160) | 7)
+
+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define PINMUX_GPIO161__FUNC_CMVREF5 (MTK_PIN_NO(161) | 1)
+#define PINMUX_GPIO161__FUNC_ANT_SEL13 (MTK_PIN_NO(161) | 2)
+#define PINMUX_GPIO161__FUNC_MSDC1_DAT1_A (MTK_PIN_NO(161) | 7)
+
+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define PINMUX_GPIO162__FUNC_CMMCLK3 (MTK_PIN_NO(162) | 1)
+#define PINMUX_GPIO162__FUNC_UDI_TDI_7 (MTK_PIN_NO(162) | 2)
+#define PINMUX_GPIO162__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(162) | 4)
+#define PINMUX_GPIO162__FUNC_MD32_3_GPIO0 (MTK_PIN_NO(162) | 5)
+#define PINMUX_GPIO162__FUNC_DBG_MON_B12 (MTK_PIN_NO(162) | 7)
+
+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define PINMUX_GPIO163__FUNC_CMMCLK4 (MTK_PIN_NO(163) | 1)
+#define PINMUX_GPIO163__FUNC_ANT_SEL7 (MTK_PIN_NO(163) | 2)
+#define PINMUX_GPIO163__FUNC_MD32_1_GPIO1 (MTK_PIN_NO(163) | 4)
+#define PINMUX_GPIO163__FUNC_MD32_3_GPIO1 (MTK_PIN_NO(163) | 5)
+#define PINMUX_GPIO163__FUNC_DBG_MON_B13 (MTK_PIN_NO(163) | 7)
+
+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define PINMUX_GPIO164__FUNC_CMMCLK5 (MTK_PIN_NO(164) | 1)
+#define PINMUX_GPIO164__FUNC_ANT_SEL6 (MTK_PIN_NO(164) | 2)
+#define PINMUX_GPIO164__FUNC_MD32_1_GPIO2 (MTK_PIN_NO(164) | 4)
+#define PINMUX_GPIO164__FUNC_MD32_3_GPIO2 (MTK_PIN_NO(164) | 5)
+
+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+#define PINMUX_GPIO165__FUNC_CONN_TOP_CLK (MTK_PIN_NO(165) | 1)
+#define PINMUX_GPIO165__FUNC_MD_URXD1 (MTK_PIN_NO(165) | 4)
+#define PINMUX_GPIO165__FUNC_DBG_MON_B14 (MTK_PIN_NO(165) | 7)
+
+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+#define PINMUX_GPIO166__FUNC_CONN_TOP_DATA (MTK_PIN_NO(166) | 1)
+#define PINMUX_GPIO166__FUNC_MD_UTXD1 (MTK_PIN_NO(166) | 4)
+#define PINMUX_GPIO166__FUNC_DBG_MON_B15 (MTK_PIN_NO(166) | 7)
+
+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+#define PINMUX_GPIO167__FUNC_CONN_HRST_B (MTK_PIN_NO(167) | 1)
+#define PINMUX_GPIO167__FUNC_UTXD2 (MTK_PIN_NO(167) | 3)
+#define PINMUX_GPIO167__FUNC_DBG_MON_B16 (MTK_PIN_NO(167) | 7)
+
+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+#define PINMUX_GPIO168__FUNC_CONN_WB_PTA (MTK_PIN_NO(168) | 1)
+#define PINMUX_GPIO168__FUNC_URXD2 (MTK_PIN_NO(168) | 3)
+#define PINMUX_GPIO168__FUNC_DBG_MON_B17 (MTK_PIN_NO(168) | 7)
+
+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define PINMUX_GPIO169__FUNC_CONN_BT_CLK (MTK_PIN_NO(169) | 1)
+#define PINMUX_GPIO169__FUNC_URTS2 (MTK_PIN_NO(169) | 3)
+#define PINMUX_GPIO169__FUNC_DBG_MON_B18 (MTK_PIN_NO(169) | 7)
+
+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define PINMUX_GPIO170__FUNC_CONN_BT_DATA (MTK_PIN_NO(170) | 1)
+#define PINMUX_GPIO170__FUNC_UCTS2 (MTK_PIN_NO(170) | 3)
+#define PINMUX_GPIO170__FUNC_DBG_MON_B19 (MTK_PIN_NO(170) | 7)
+
+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define PINMUX_GPIO171__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(171) | 1)
+#define PINMUX_GPIO171__FUNC_DBG_MON_B20 (MTK_PIN_NO(171) | 7)
+
+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define PINMUX_GPIO172__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(172) | 1)
+#define PINMUX_GPIO172__FUNC_PCM1_CLK (MTK_PIN_NO(172) | 3)
+#define PINMUX_GPIO172__FUNC_DBG_MON_B21 (MTK_PIN_NO(172) | 7)
+
+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define PINMUX_GPIO173__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(173) | 1)
+#define PINMUX_GPIO173__FUNC_PCM1_SYNC (MTK_PIN_NO(173) | 3)
+#define PINMUX_GPIO173__FUNC_DBG_MON_B22 (MTK_PIN_NO(173) | 7)
+
+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define PINMUX_GPIO174__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(174) | 1)
+#define PINMUX_GPIO174__FUNC_PCM1_DI (MTK_PIN_NO(174) | 3)
+#define PINMUX_GPIO174__FUNC_DBG_MON_B23 (MTK_PIN_NO(174) | 7)
+
+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define PINMUX_GPIO175__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(175) | 1)
+#define PINMUX_GPIO175__FUNC_PCM1_DO0 (MTK_PIN_NO(175) | 3)
+#define PINMUX_GPIO175__FUNC_DBG_MON_B24 (MTK_PIN_NO(175) | 7)
+
+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define PINMUX_GPIO176__FUNC_ANT_SEL0 (MTK_PIN_NO(176) | 1)
+#define PINMUX_GPIO176__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(176) | 2)
+#define PINMUX_GPIO176__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(176) | 4)
+#define PINMUX_GPIO176__FUNC_I2S0_MCK (MTK_PIN_NO(176) | 5)
+#define PINMUX_GPIO176__FUNC_PTA_EXT_FREQ (MTK_PIN_NO(176) | 6)
+#define PINMUX_GPIO176__FUNC_PMSR_SMAP (MTK_PIN_NO(176) | 7)
+
+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define PINMUX_GPIO177__FUNC_ANT_SEL1 (MTK_PIN_NO(177) | 1)
+#define PINMUX_GPIO177__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(177) | 2)
+#define PINMUX_GPIO177__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(177) | 4)
+#define PINMUX_GPIO177__FUNC_I2S0_BCK (MTK_PIN_NO(177) | 5)
+#define PINMUX_GPIO177__FUNC_PTA_EXT_ACT (MTK_PIN_NO(177) | 6)
+#define PINMUX_GPIO177__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(177) | 7)
+
+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define PINMUX_GPIO178__FUNC_ANT_SEL2 (MTK_PIN_NO(178) | 1)
+#define PINMUX_GPIO178__FUNC_AGPS_SYNC (MTK_PIN_NO(178) | 2)
+#define PINMUX_GPIO178__FUNC_IDDIG (MTK_PIN_NO(178) | 3)
+#define PINMUX_GPIO178__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(178) | 4)
+#define PINMUX_GPIO178__FUNC_I2S0_LRCK (MTK_PIN_NO(178) | 5)
+#define PINMUX_GPIO178__FUNC_PTA_EXT_PRI (MTK_PIN_NO(178) | 6)
+#define PINMUX_GPIO178__FUNC_DP_TX_HPD (MTK_PIN_NO(178) | 7)
+
+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define PINMUX_GPIO179__FUNC_ANT_SEL3 (MTK_PIN_NO(179) | 1)
+#define PINMUX_GPIO179__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(179) | 2)
+#define PINMUX_GPIO179__FUNC_USB_DRVVBUS (MTK_PIN_NO(179) | 3)
+#define PINMUX_GPIO179__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(179) | 4)
+#define PINMUX_GPIO179__FUNC_I2S0_DI (MTK_PIN_NO(179) | 5)
+#define PINMUX_GPIO179__FUNC_PTA_EXT_WLAN_ACT (MTK_PIN_NO(179) | 6)
+#define PINMUX_GPIO179__FUNC_DP_OC_EN (MTK_PIN_NO(179) | 7)
+
+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define PINMUX_GPIO180__FUNC_ANT_SEL4 (MTK_PIN_NO(180) | 1)
+#define PINMUX_GPIO180__FUNC_GPS_PPS (MTK_PIN_NO(180) | 2)
+#define PINMUX_GPIO180__FUNC_CLKM2 (MTK_PIN_NO(180) | 3)
+#define PINMUX_GPIO180__FUNC_DMIC1_CLK (MTK_PIN_NO(180) | 4)
+#define PINMUX_GPIO180__FUNC_I2S5_DO (MTK_PIN_NO(180) | 5)
+#define PINMUX_GPIO180__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(180) | 7)
+
+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define PINMUX_GPIO181__FUNC_ANT_SEL5 (MTK_PIN_NO(181) | 1)
+#define PINMUX_GPIO181__FUNC_GPS_PPS (MTK_PIN_NO(181) | 2)
+#define PINMUX_GPIO181__FUNC_AGPS_SYNC (MTK_PIN_NO(181) | 3)
+#define PINMUX_GPIO181__FUNC_DMIC1_DAT (MTK_PIN_NO(181) | 4)
+#define PINMUX_GPIO181__FUNC_I2S5_MCK (MTK_PIN_NO(181) | 5)
+#define PINMUX_GPIO181__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(181) | 7)
+
+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define PINMUX_GPIO182__FUNC_ANT_SEL6 (MTK_PIN_NO(182) | 1)
+#define PINMUX_GPIO182__FUNC_SPI4_A_MI (MTK_PIN_NO(182) | 3)
+#define PINMUX_GPIO182__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(182) | 4)
+#define PINMUX_GPIO182__FUNC_I2S5_BCK (MTK_PIN_NO(182) | 5)
+#define PINMUX_GPIO182__FUNC_DP_TX_HPD (MTK_PIN_NO(182) | 7)
+
+#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
+#define PINMUX_GPIO183__FUNC_ANT_SEL7 (MTK_PIN_NO(183) | 1)
+#define PINMUX_GPIO183__FUNC_SPI4_A_MO (MTK_PIN_NO(183) | 3)
+#define PINMUX_GPIO183__FUNC_PWM_1 (MTK_PIN_NO(183) | 4)
+#define PINMUX_GPIO183__FUNC_I2S5_LRCK (MTK_PIN_NO(183) | 5)
+#define PINMUX_GPIO183__FUNC_DP_OC_EN (MTK_PIN_NO(183) | 7)
+
+#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
+#define PINMUX_GPIO184__FUNC_ANT_SEL8 (MTK_PIN_NO(184) | 1)
+#define PINMUX_GPIO184__FUNC_SPI4_A_CLK (MTK_PIN_NO(184) | 3)
+#define PINMUX_GPIO184__FUNC_URTS2 (MTK_PIN_NO(184) | 4)
+#define PINMUX_GPIO184__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(184) | 7)
+
+#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)
+#define PINMUX_GPIO185__FUNC_ANT_SEL9 (MTK_PIN_NO(185) | 1)
+#define PINMUX_GPIO185__FUNC_SPI4_A_CSB (MTK_PIN_NO(185) | 3)
+#define PINMUX_GPIO185__FUNC_UCTS2 (MTK_PIN_NO(185) | 4)
+#define PINMUX_GPIO185__FUNC_I2S5_DO (MTK_PIN_NO(185) | 5)
+#define PINMUX_GPIO185__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(185) | 7)
+
+#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)
+#define PINMUX_GPIO186__FUNC_CONN_MIPI_ANT_SCLK (MTK_PIN_NO(186) | 1)
+#define PINMUX_GPIO186__FUNC_MIPI4_D_SCLK (MTK_PIN_NO(186) | 2)
+#define PINMUX_GPIO186__FUNC_MD_URXD1 (MTK_PIN_NO(186) | 4)
+#define PINMUX_GPIO186__FUNC_ANT_SEL14 (MTK_PIN_NO(186) | 5)
+#define PINMUX_GPIO186__FUNC_DMIC_CLK (MTK_PIN_NO(186) | 6)
+#define PINMUX_GPIO186__FUNC_DMIC1_CLK (MTK_PIN_NO(186) | 7)
+
+#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)
+#define PINMUX_GPIO187__FUNC_CONN_MIPI_ANT_SDATA (MTK_PIN_NO(187) | 1)
+#define PINMUX_GPIO187__FUNC_MIPI4_D_SDATA (MTK_PIN_NO(187) | 2)
+#define PINMUX_GPIO187__FUNC_MD_UTXD1 (MTK_PIN_NO(187) | 4)
+#define PINMUX_GPIO187__FUNC_ANT_SEL15 (MTK_PIN_NO(187) | 5)
+#define PINMUX_GPIO187__FUNC_DMIC_DAT (MTK_PIN_NO(187) | 6)
+#define PINMUX_GPIO187__FUNC_DMIC1_DAT (MTK_PIN_NO(187) | 7)
+
+#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)
+#define PINMUX_GPIO188__FUNC_MSDC2_CLK (MTK_PIN_NO(188) | 1)
+#define PINMUX_GPIO188__FUNC_ANT_SEL10 (MTK_PIN_NO(188) | 2)
+#define PINMUX_GPIO188__FUNC_CLKM0 (MTK_PIN_NO(188) | 3)
+#define PINMUX_GPIO188__FUNC_PTA_RXD (MTK_PIN_NO(188) | 4)
+#define PINMUX_GPIO188__FUNC_VPU_UDI_TCK (MTK_PIN_NO(188) | 5)
+#define PINMUX_GPIO188__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(188) | 7)
+
+#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)
+#define PINMUX_GPIO189__FUNC_MSDC2_CMD (MTK_PIN_NO(189) | 1)
+#define PINMUX_GPIO189__FUNC_ANT_SEL11 (MTK_PIN_NO(189) | 2)
+#define PINMUX_GPIO189__FUNC_CLKM1 (MTK_PIN_NO(189) | 3)
+#define PINMUX_GPIO189__FUNC_PTA_TXD (MTK_PIN_NO(189) | 4)
+#define PINMUX_GPIO189__FUNC_VPU_UDI_TMS (MTK_PIN_NO(189) | 5)
+#define PINMUX_GPIO189__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(189) | 7)
+
+#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)
+#define PINMUX_GPIO190__FUNC_MSDC2_DAT0 (MTK_PIN_NO(190) | 1)
+#define PINMUX_GPIO190__FUNC_ANT_SEL12 (MTK_PIN_NO(190) | 2)
+#define PINMUX_GPIO190__FUNC_PTA_EXT_FREQ (MTK_PIN_NO(190) | 3)
+#define PINMUX_GPIO190__FUNC_SPI6_B_MI (MTK_PIN_NO(190) | 4)
+#define PINMUX_GPIO190__FUNC_VPU_UDI_TDI (MTK_PIN_NO(190) | 5)
+#define PINMUX_GPIO190__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(190) | 7)
+
+#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)
+#define PINMUX_GPIO191__FUNC_MSDC2_DAT1 (MTK_PIN_NO(191) | 1)
+#define PINMUX_GPIO191__FUNC_ANT_SEL13 (MTK_PIN_NO(191) | 2)
+#define PINMUX_GPIO191__FUNC_PTA_EXT_ACT (MTK_PIN_NO(191) | 3)
+#define PINMUX_GPIO191__FUNC_SPI6_B_CSB (MTK_PIN_NO(191) | 4)
+#define PINMUX_GPIO191__FUNC_VPU_UDI_NTRST (MTK_PIN_NO(191) | 5)
+#define PINMUX_GPIO191__FUNC_PMSR_SMAP (MTK_PIN_NO(191) | 6)
+
+#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)
+#define PINMUX_GPIO192__FUNC_MSDC2_DAT2 (MTK_PIN_NO(192) | 1)
+#define PINMUX_GPIO192__FUNC_ANT_SEL14 (MTK_PIN_NO(192) | 2)
+#define PINMUX_GPIO192__FUNC_PTA_EXT_PRI (MTK_PIN_NO(192) | 3)
+#define PINMUX_GPIO192__FUNC_SPI6_B_MO (MTK_PIN_NO(192) | 4)
+#define PINMUX_GPIO192__FUNC_VPU_UDI_TDO (MTK_PIN_NO(192) | 5)
+#define PINMUX_GPIO192__FUNC_DBG_MON_B31 (MTK_PIN_NO(192) | 7)
+
+#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)
+#define PINMUX_GPIO193__FUNC_MSDC2_DAT3 (MTK_PIN_NO(193) | 1)
+#define PINMUX_GPIO193__FUNC_ANT_SEL15 (MTK_PIN_NO(193) | 2)
+#define PINMUX_GPIO193__FUNC_PTA_EXT_WLAN_ACT (MTK_PIN_NO(193) | 3)
+#define PINMUX_GPIO193__FUNC_SPI6_B_CLK (MTK_PIN_NO(193) | 4)
+#define PINMUX_GPIO193__FUNC_AGPS_SYNC (MTK_PIN_NO(193) | 5)
+#define PINMUX_GPIO193__FUNC_DBG_MON_B32 (MTK_PIN_NO(193) | 7)
+
+#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)
+#define PINMUX_GPIO194__FUNC_SRCLKENAI0 (MTK_PIN_NO(194) | 1)
+#define PINMUX_GPIO194__FUNC_SRCLKENAI1 (MTK_PIN_NO(194) | 2)
+
+#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)
+#define PINMUX_GPIO195__FUNC_SRCLKENA0 (MTK_PIN_NO(195) | 1)
+#define PINMUX_GPIO195__FUNC_SRCLKENA1 (MTK_PIN_NO(195) | 2)
+
+#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0)
+#define PINMUX_GPIO196__FUNC_SRCLKENA1 (MTK_PIN_NO(196) | 1)
+#define PINMUX_GPIO196__FUNC_SRCLKENA0 (MTK_PIN_NO(196) | 2)
+
+#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0)
+#define PINMUX_GPIO197__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(197) | 1)
+#define PINMUX_GPIO197__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(197) | 2)
+
+#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0)
+#define PINMUX_GPIO198__FUNC_WATCHDOG (MTK_PIN_NO(198) | 1)
+
+#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define PINMUX_GPIO199__FUNC_RTC32K_CK (MTK_PIN_NO(199) | 1)
+
+#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define PINMUX_GPIO200__FUNC_SCP_SCL1 (MTK_PIN_NO(200) | 1)
+#define PINMUX_GPIO200__FUNC_SCL1 (MTK_PIN_NO(200) | 2)
+
+#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define PINMUX_GPIO201__FUNC_SCP_SDA1 (MTK_PIN_NO(201) | 1)
+#define PINMUX_GPIO201__FUNC_SDA1 (MTK_PIN_NO(201) | 2)
+
+#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define PINMUX_GPIO202__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(202) | 1)
+#define PINMUX_GPIO202__FUNC_AUD_CLK_MOSI_A (MTK_PIN_NO(202) | 3)
+#define PINMUX_GPIO202__FUNC_TDMIN_BCK (MTK_PIN_NO(202) | 4)
+
+#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define PINMUX_GPIO203__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(203) | 1)
+#define PINMUX_GPIO203__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(203) | 3)
+
+#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+#define PINMUX_GPIO204__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(204) | 1)
+#define PINMUX_GPIO204__FUNC_AUD_DAT_MOSI0_A (MTK_PIN_NO(204) | 3)
+#define PINMUX_GPIO204__FUNC_TDMOUT_DATA0 (MTK_PIN_NO(204) | 4)
+
+#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+#define PINMUX_GPIO205__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(205) | 1)
+#define PINMUX_GPIO205__FUNC_AUD_DAT_MOSI1_A (MTK_PIN_NO(205) | 3)
+#define PINMUX_GPIO205__FUNC_TDMOUT_DATA1 (MTK_PIN_NO(205) | 4)
+
+#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+#define PINMUX_GPIO206__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(206) | 1)
+#define PINMUX_GPIO206__FUNC_TDMOUT_LRCK (MTK_PIN_NO(206) | 4)
+
+#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+#define PINMUX_GPIO207__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(207) | 1)
+#define PINMUX_GPIO207__FUNC_AUD_CLK_MISO (MTK_PIN_NO(207) | 2)
+
+#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+#define PINMUX_GPIO208__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(208) | 1)
+#define PINMUX_GPIO208__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(208) | 2)
+
+#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+#define PINMUX_GPIO209__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(209) | 1)
+#define PINMUX_GPIO209__FUNC_VOW_DAT_MISO (MTK_PIN_NO(209) | 2)
+#define PINMUX_GPIO209__FUNC_AUD_DAT_MISO0_A (MTK_PIN_NO(209) | 3)
+#define PINMUX_GPIO209__FUNC_TDMIN_DATA0 (MTK_PIN_NO(209) | 4)
+
+#define PINMUX_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0)
+#define PINMUX_GPIO210__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(210) | 1)
+#define PINMUX_GPIO210__FUNC_VOW_CLK_MISO (MTK_PIN_NO(210) | 2)
+#define PINMUX_GPIO210__FUNC_AUD_CLK_MISO (MTK_PIN_NO(210) | 3)
+#define PINMUX_GPIO210__FUNC_TDMIN_LRCK (MTK_PIN_NO(210) | 4)
+
+#define PINMUX_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0)
+#define PINMUX_GPIO211__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(211) | 1)
+#define PINMUX_GPIO211__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(211) | 3)
+#define PINMUX_GPIO211__FUNC_TDMOUT_BCK (MTK_PIN_NO(211) | 4)
+
+#define PINMUX_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0)
+#define PINMUX_GPIO212__FUNC_CMFLASH0 (MTK_PIN_NO(212) | 1)
+#define PINMUX_GPIO212__FUNC_MD_UCTS0 (MTK_PIN_NO(212) | 2)
+#define PINMUX_GPIO212__FUNC_TP_GPIO15_AO (MTK_PIN_NO(212) | 3)
+#define PINMUX_GPIO212__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(212) | 5)
+#define PINMUX_GPIO212__FUNC_I2S3_MCK (MTK_PIN_NO(212) | 6)
+#define PINMUX_GPIO212__FUNC_DMIC_DAT (MTK_PIN_NO(212) | 7)
+
+#define PINMUX_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0)
+#define PINMUX_GPIO213__FUNC_CMFLASH1 (MTK_PIN_NO(213) | 1)
+#define PINMUX_GPIO213__FUNC_MD_URTS0 (MTK_PIN_NO(213) | 2)
+#define PINMUX_GPIO213__FUNC_TP_GPIO14_AO (MTK_PIN_NO(213) | 3)
+#define PINMUX_GPIO213__FUNC_KPCOL1 (MTK_PIN_NO(213) | 4)
+#define PINMUX_GPIO213__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(213) | 5)
+#define PINMUX_GPIO213__FUNC_I2S3_BCK (MTK_PIN_NO(213) | 6)
+#define PINMUX_GPIO213__FUNC_DP_TX_HPD (MTK_PIN_NO(213) | 7)
+
+#define PINMUX_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0)
+#define PINMUX_GPIO214__FUNC_CMFLASH2 (MTK_PIN_NO(214) | 1)
+#define PINMUX_GPIO214__FUNC_MD_UCTS1 (MTK_PIN_NO(214) | 2)
+#define PINMUX_GPIO214__FUNC_TP_GPIO13_AO (MTK_PIN_NO(214) | 3)
+#define PINMUX_GPIO214__FUNC_KPCOL2 (MTK_PIN_NO(214) | 4)
+#define PINMUX_GPIO214__FUNC_MD_INT3 (MTK_PIN_NO(214) | 5)
+#define PINMUX_GPIO214__FUNC_I2S3_LRCK (MTK_PIN_NO(214) | 6)
+#define PINMUX_GPIO214__FUNC_DP_OC_EN (MTK_PIN_NO(214) | 7)
+
+#define PINMUX_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0)
+#define PINMUX_GPIO215__FUNC_CMFLASH3 (MTK_PIN_NO(215) | 1)
+#define PINMUX_GPIO215__FUNC_MD_URTS1 (MTK_PIN_NO(215) | 2)
+#define PINMUX_GPIO215__FUNC_TP_GPIO12_AO (MTK_PIN_NO(215) | 3)
+#define PINMUX_GPIO215__FUNC_KPROW1 (MTK_PIN_NO(215) | 4)
+#define PINMUX_GPIO215__FUNC_MD_INT4 (MTK_PIN_NO(215) | 5)
+#define PINMUX_GPIO215__FUNC_I2S0_DI (MTK_PIN_NO(215) | 6)
+#define PINMUX_GPIO215__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(215) | 7)
+
+#define PINMUX_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0)
+#define PINMUX_GPIO216__FUNC_PWM_VLP (MTK_PIN_NO(216) | 1)
+#define PINMUX_GPIO216__FUNC_MD_INT0 (MTK_PIN_NO(216) | 2)
+#define PINMUX_GPIO216__FUNC_TP_GPIO11_AO (MTK_PIN_NO(216) | 3)
+#define PINMUX_GPIO216__FUNC_KPROW2 (MTK_PIN_NO(216) | 4)
+#define PINMUX_GPIO216__FUNC_DMIC_CLK (MTK_PIN_NO(216) | 5)
+#define PINMUX_GPIO216__FUNC_I2S3_DO (MTK_PIN_NO(216) | 6)
+#define PINMUX_GPIO216__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(216) | 7)
+
+#define PINMUX_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0)
+#define PINMUX_GPIO217__FUNC_SPI3_A_CLK (MTK_PIN_NO(217) | 1)
+#define PINMUX_GPIO217__FUNC_SCP_SPI3_A_CK (MTK_PIN_NO(217) | 2)
+#define PINMUX_GPIO217__FUNC_SCP_SCL4 (MTK_PIN_NO(217) | 3)
+#define PINMUX_GPIO217__FUNC_MD_URXD0 (MTK_PIN_NO(217) | 4)
+#define PINMUX_GPIO217__FUNC_TP_URXD2_VLP (MTK_PIN_NO(217) | 5)
+#define PINMUX_GPIO217__FUNC_MD32_3_RXD (MTK_PIN_NO(217) | 6)
+#define PINMUX_GPIO217__FUNC_MD32_1_RXD (MTK_PIN_NO(217) | 7)
+
+#define PINMUX_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0)
+#define PINMUX_GPIO218__FUNC_SPI3_A_CSB (MTK_PIN_NO(218) | 1)
+#define PINMUX_GPIO218__FUNC_SCP_SPI3_A_CS (MTK_PIN_NO(218) | 2)
+#define PINMUX_GPIO218__FUNC_SCP_SDA4 (MTK_PIN_NO(218) | 3)
+#define PINMUX_GPIO218__FUNC_MD_UTXD0 (MTK_PIN_NO(218) | 4)
+#define PINMUX_GPIO218__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(218) | 5)
+#define PINMUX_GPIO218__FUNC_MD32_3_TXD (MTK_PIN_NO(218) | 6)
+#define PINMUX_GPIO218__FUNC_MD32_1_TXD (MTK_PIN_NO(218) | 7)
+
+#define PINMUX_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0)
+#define PINMUX_GPIO219__FUNC_SPI3_A_MI (MTK_PIN_NO(219) | 1)
+#define PINMUX_GPIO219__FUNC_SCP_SPI3_A_MI (MTK_PIN_NO(219) | 2)
+#define PINMUX_GPIO219__FUNC_TP_URTS2_VLP (MTK_PIN_NO(219) | 3)
+#define PINMUX_GPIO219__FUNC_MD_URXD1 (MTK_PIN_NO(219) | 4)
+#define PINMUX_GPIO219__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(219) | 5)
+#define PINMUX_GPIO219__FUNC_URXD1 (MTK_PIN_NO(219) | 6)
+#define PINMUX_GPIO219__FUNC_HFRP_URXD1 (MTK_PIN_NO(219) | 7)
+
+#define PINMUX_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0)
+#define PINMUX_GPIO220__FUNC_SPI3_A_MO (MTK_PIN_NO(220) | 1)
+#define PINMUX_GPIO220__FUNC_SCP_SPI3_A_MO (MTK_PIN_NO(220) | 2)
+#define PINMUX_GPIO220__FUNC_TP_UCTS2_VLP (MTK_PIN_NO(220) | 3)
+#define PINMUX_GPIO220__FUNC_MD_UTXD1 (MTK_PIN_NO(220) | 4)
+#define PINMUX_GPIO220__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(220) | 5)
+#define PINMUX_GPIO220__FUNC_UTXD1 (MTK_PIN_NO(220) | 6)
+#define PINMUX_GPIO220__FUNC_HFRP_UTXD1 (MTK_PIN_NO(220) | 7)
+
+#define PINMUX_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0)
+#define PINMUX_GPIO221__FUNC_SPMI_M_SCL (MTK_PIN_NO(221) | 1)
+#define PINMUX_GPIO221__FUNC_SPMI_P_SCL (MTK_PIN_NO(221) | 2)
+
+#define PINMUX_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0)
+#define PINMUX_GPIO222__FUNC_SPMI_M_SDA (MTK_PIN_NO(222) | 1)
+#define PINMUX_GPIO222__FUNC_SPMI_P_SDA (MTK_PIN_NO(222) | 2)
+
+#define PINMUX_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0)
+#define PINMUX_GPIO223__FUNC_SPMI_P_SCL (MTK_PIN_NO(223) | 1)
+#define PINMUX_GPIO223__FUNC_SPMI_M_SCL (MTK_PIN_NO(223) | 2)
+
+#define PINMUX_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0)
+#define PINMUX_GPIO224__FUNC_SPMI_P_SDA (MTK_PIN_NO(224) | 1)
+#define PINMUX_GPIO224__FUNC_SPMI_M_SDA (MTK_PIN_NO(224) | 2)
+
+#define PINMUX_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0)
+#define PINMUX_GPIO225__FUNC_SCP_SCL3 (MTK_PIN_NO(225) | 1)
+
+#define PINMUX_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0)
+#define PINMUX_GPIO226__FUNC_SCP_SDA3 (MTK_PIN_NO(226) | 1)
+
+#endif /* __MT6895_PINFUNC_H */

-- 
2.56.0

[PATCH v2 8/9] arm64: dts: mediatek: Add MT6895 SoC

[Alexander Letuchiy]

Add initial support for the MediaTek MT6895 (Dimensity 8000/8100) SoC,
which has four Cortex-A55 and four Cortex-A78 cores sharing a DynamIQ
cluster with 4 MiB of L3 cache.

Describe the CPUs with their caches, PSCI, the GICv3 interrupt
controller, the CPU and DSU PMUs, the architected timer, the system
timer, the pin controller, two UARTs, the watchdog and the keypad.
There is no clock controller driver for this SoC yet, so the UARTs and
the keypad use a fixed 26 MHz clock, and the system timer a fixed
13 MHz clock derived from it.

Only the CPU and cluster power down idle states are described. The
deeper states that also power down the MCUSYS or the whole system need
the SPM and the vendor low power driver, which aren't supported yet.
The system timer serves as the broadcast timer while the CPUs are in
these states.

The cache geometry was checked against the CCSIDR registers of each
core.

Signed-off-by: Alexander Letuchiy <asalde.le1@gmail.com>
---
 arch/arm64/boot/dts/mediatek/mt6895.dtsi | 461 +++++++++++++++++++++++++++++++
 1 file changed, 461 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6895.dtsi b/arch/arm64/boot/dts/mediatek/mt6895.dtsi
new file mode 100644
index 000000000000..62584cec0f4f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6895.dtsi
@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2026 Alexander Letuchiy <asalde.le1@gmail.com>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "mt6895-pinfunc.h"
+
+/ {
+	compatible = "mediatek,mt6895";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	clk13m: clock-13m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk26m>;
+		clock-div = <2>;
+		clock-mult = <1>;
+		clock-output-names = "clk13m";
+	};
+
+	clk26m: clock-26m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "clk26m";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+
+				core4 {
+					cpu = <&cpu4>;
+				};
+
+				core5 {
+					cpu = <&cpu5>;
+				};
+
+				core6 {
+					cpu = <&cpu6>;
+				};
+
+				core7 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <380>;
+			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <380>;
+			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_1>;
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <380>;
+			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_2>;
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <380>;
+			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+			i-cache-size = <32768>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_3>;
+		};
+
+		cpu4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0x400>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+			i-cache-size = <65536>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_4>;
+		};
+
+		cpu5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0x500>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+			i-cache-size = <65536>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_5>;
+		};
+
+		cpu6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0x600>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+			i-cache-size = <65536>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_6>;
+		};
+
+		cpu7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0x700>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+			i-cache-size = <65536>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&l2_7>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cluster_off_b: cluster-off-b {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				entry-latency-us = <100>;
+				exit-latency-us = <250>;
+				min-residency-us = <1900>;
+				arm,psci-suspend-param = <0x01010102>;
+			};
+
+			cluster_off_l: cluster-off-l {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				entry-latency-us = <100>;
+				exit-latency-us = <250>;
+				min-residency-us = <2100>;
+				arm,psci-suspend-param = <0x01010101>;
+			};
+
+			cpu_off_b: cpu-off-b {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				entry-latency-us = <50>;
+				exit-latency-us = <100>;
+				min-residency-us = <1400>;
+				arm,psci-suspend-param = <0x00010002>;
+			};
+
+			cpu_off_l: cpu-off-l {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				entry-latency-us = <50>;
+				exit-latency-us = <100>;
+				min-residency-us = <1600>;
+				arm,psci-suspend-param = <0x00010001>;
+			};
+		};
+
+		l2_0: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <131072>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l2_1: l2-cache1 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <131072>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l2_2: l2-cache2 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <131072>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l2_3: l2-cache3 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <131072>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l2_4: l2-cache4 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <524288>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l2_5: l2-cache5 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <524288>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l2_6: l2-cache6 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <524288>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l2_7: l2-cache7 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <524288>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			next-level-cache = <&l3_0>;
+			cache-unified;
+		};
+
+		l3_0: l3-cache {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-size = <4194304>;
+			cache-line-size = <64>;
+			cache-sets = <4096>;
+			cache-unified;
+		};
+	};
+
+	dsu-pmu {
+		compatible = "arm,dsu-pmu";
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
+		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+		       <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+	};
+
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+	};
+
+	pmu-a78 {
+		compatible = "arm,cortex-a78-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		gic: interrupt-controller@c000000 {
+			compatible = "arm,gic-v3";
+			reg = <0 0x0c000000 0 0x40000>,
+			      <0 0x0c040000 0 0x200000>;
+			#interrupt-cells = <4>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			ppi-partitions {
+				ppi_cluster0: interrupt-partition-0 {
+					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+				};
+
+				ppi_cluster1: interrupt-partition-1 {
+					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+				};
+			};
+		};
+
+		pio: pinctrl@10005000 {
+			compatible = "mediatek,mt6895-pinctrl";
+			reg = <0 0x10005000 0 0x1000>,
+			      <0 0x11c20000 0 0x1000>,
+			      <0 0x11c30000 0 0x1000>,
+			      <0 0x11c40000 0 0x1000>,
+			      <0 0x11d10000 0 0x1000>,
+			      <0 0x11d30000 0 0x1000>,
+			      <0 0x11d40000 0 0x1000>,
+			      <0 0x11d50000 0 0x1000>,
+			      <0 0x11d60000 0 0x1000>,
+			      <0 0x11e10000 0 0x1000>,
+			      <0 0x11ea0000 0 0x1000>,
+			      <0 0x11eb0000 0 0x1000>,
+			      <0 0x11f20000 0 0x1000>,
+			      <0 0x11f30000 0 0x1000>,
+			      <0 0x11e50000 0 0x1000>,
+			      <0 0x11ce0000 0 0x1000>,
+			      <0 0x11de0000 0 0x1000>,
+			      <0 0x11fe0000 0 0x1000>,
+			      <0 0x1c01e000 0 0x1000>;
+			reg-names = "base", "rm", "rt", "rmm", "bl", "bm", "br",
+				    "brr", "lb", "lm", "rtt", "tr", "tl", "lt",
+				    "eint-w", "eint-e", "eint-s", "eint-n", "eint-c";
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pio 0 0 227>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+			#interrupt-cells = <2>;
+		};
+
+		uart0: serial@11001000 {
+			compatible = "mediatek,mt6895-uart", "mediatek,mt6577-uart";
+			reg = <0 0x11001000 0 0x1000>;
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&clk26m>, <&clk26m>;
+			clock-names = "baud", "bus";
+
+			status = "disabled";
+		};
+
+		uart1: serial@11002000 {
+			compatible = "mediatek,mt6895-uart", "mediatek,mt6577-uart";
+			reg = <0 0x11002000 0 0x1000>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&clk26m>, <&clk26m>;
+			clock-names = "baud", "bus";
+
+			status = "disabled";
+		};
+
+		watchdog: watchdog@1c007000 {
+			compatible = "mediatek,mt6895-wdt";
+			reg = <0 0x1c007000 0 0x100>;
+		};
+
+		keypad: keypad@1c00e000 {
+			compatible = "mediatek,mt6895-keypad",
+				     "mediatek,mt6779-keypad";
+			reg = <0 0x1c00e000 0 0x1000>;
+			wakeup-source;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING 0>;
+			clocks = <&clk26m>;
+			clock-names = "kpd";
+
+			status = "disabled";
+		};
+
+		systimer: timer@1c011000 {
+			compatible = "mediatek,mt6895-timer",
+				     "mediatek,mt6765-timer";
+			reg = <0 0x1c011000 0 0x1000>;
+			interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&clk13m>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+	};
+};

-- 
2.56.0

[PATCH v2 9/9] arm64: dts: mediatek: Add Xiaomi Poco X4 GT

[Alexander Letuchiy]

Add a device tree for the Xiaomi xaga board, which is sold as Xiaomi
Poco X4 GT, Redmi Note 11T Pro/Pro+ and Redmi K50i. It enables a serial
console on UART0 and the volume down key on the SoC keypad. The power
and volume up keys are connected to the MT6363 PMIC, which isn't
supported yet.

The DT only describes the memory that Linux itself uses, which is the
ramoops region. The bootloader updates the /memory node and adds the
firmware carveouts to /reserved-memory, so their addresses are not
hardcoded here. This DT must not be booted with a bootloader that does
not do this, as Linux would then use memory owned by the firmware.

The ramoops zone sizes place the console zone at the offset where the
bootloader expects to find it.

Signed-off-by: Alexander Letuchiy <asalde.le1@gmail.com>
---
 arch/arm64/boot/dts/mediatek/Makefile              |  1 +
 .../arm64/boot/dts/mediatek/mt6895-xiaomi-xaga.dts | 87 ++++++++++++++++++++++
 2 files changed, 88 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index a86fb313b1a9..d73489149ab5 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6895-xiaomi-xaga.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6895-xiaomi-xaga.dts b/arch/arm64/boot/dts/mediatek/mt6895-xiaomi-xaga.dts
new file mode 100644
index 000000000000..8d529062eea1
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6895-xiaomi-xaga.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2026 Alexander Letuchiy <asalde.le1@gmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+
+#include "mt6895.dtsi"
+
+/ {
+	model = "Xiaomi Poco X4 GT";
+	compatible = "xiaomi,xaga", "mediatek,mt6895";
+	chassis-type = "handset";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:921600n8";
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		/* The size is updated by the bootloader. */
+		reg = <0x0 0x40000000 0x2 0x0>;
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		/* The firmware carveouts are added by the bootloader. */
+
+		ramoops@48090000 {
+			compatible = "ramoops";
+			reg = <0 0x48090000 0 0xe0000>;
+			no-map;
+			record-size = <0x10000>;
+			console-size = <0x40000>;
+			ftrace-size = <0x10000>;
+			pmsg-size = <0x10000>;
+		};
+	};
+};
+
+&keypad {
+	pinctrl-0 = <&keypad_pins>;
+	pinctrl-names = "default";
+	debounce-delay-ms = <32>;
+	keypad,num-columns = <1>;
+	keypad,num-rows = <1>;
+	linux,keymap = <MATRIX_KEY(0, 0, KEY_VOLUMEDOWN)>;
+
+	status = "okay";
+};
+
+&pio {
+	keypad_pins: keypad-pins {
+		pins-col {
+			pinmux = <PINMUX_GPIO107__FUNC_KPCOL0>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+			input-enable;
+		};
+	};
+
+	uart0_pins: uart0-pins {
+		pins-rx {
+			pinmux = <PINMUX_GPIO88__FUNC_URXD0>;
+			bias-pull-up;
+			input-enable;
+		};
+
+		pins-tx {
+			pinmux = <PINMUX_GPIO89__FUNC_UTXD0>;
+		};
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};

-- 
2.56.0