Re: [PATCH v7 1/2] arm64: dts: intel: agilex5: add USB3.1 controller node

["Ng, Adrian Ho Yin" <adrian.ho.yin.ng@altera.com>]

On 9/11/2026 5:19 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] Missing fallback compatible string prevents the DWC3 controller from probing.
> - [Medium] Devicetree Topology / Address Space Overflow in DMA ranges mapping.
> --
> 
> commit f5eee55ab58207528984fe03c0204fcdede698dd
> Author: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> Date:   Fri Sep 11 09:09:24 2026 +0000
> 
> arm64: dts: intel: agilex5: add USB3.1 controller node
> 
> This commit adds a devicetree node for the Synopsys DWC3 USB3.1 controller on
> the Agilex5 SoC. It places the controller under a simple-bus with a 40-bit
> dma-ranges window to match the interconnect's DMA address width. The
> controller is also enabled in host mode for the SoCDK board.
> 
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index f54767d1526e1..523f722a2a642 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -493,6 +493,41 @@ usb0: usb@10b00000 {
>>   			status = "disabled";
>>   		};
>>   
>> +		usb31_bus: usb-bus@11000000 {
>> +			compatible = "simple-bus";
>> +			#address-cells = <2>;
>> +			#size-cells = <2>;
>> +			ranges = <0x0 0x0 0x11000000 0x0 0x100000>;
>> +			/*
>> +			 * USB interconnect DMA is limited to 40-bit addresses
>> +			 * (1 TiB window from 0).
>> +			 */
>> +			dma-ranges = <0x0 0x0 0x0 0x100 0x0>;
> 
> [Severity: Medium]
> Does this dma-ranges mapping structurally overflow the parent bus?
> 
> This property specifies a 1 TiB window (0x100 0x0) and maps it into the parent
> bus which only has 32-bit address capacity. Since a 32-bit bus can
> mathematically only address up to 4 GB, could this cause DMA configuration
> failures or silent truncations depending on how the OF core parses the tree?
Disagree because: the entry matches DT cell rules for this bus, and the 
size describes the DMA interconnect aperture, not soc MMIO capacity.

usb31_bus: #address-cells=<2>,#size-cells=<2>; parent soc: 
#address-cells=<1> => dma-ranges cells = 2 + 1 + 2:
<0x0 0x0   0x0   0x100 0x0>  /* child DMA, parent CPU, 1 TiB size */

OF parses this by cell counts (of_dma_get_range); it does not truncate 
the size to the parent's 32-bit MMIO window. Same 40-bit dma-ranges 
pattern is already used by dma-bus@10db0000 in this dtsi.
> 
>> +
>> +			usb31: usb@0 {
>> +				compatible = "altr,agilex5-dwc3";
> 
> [Severity: High]
> Will the USB subsystem fail to bind to this device without a generic fallback?
> 
> This node specifies a SoC-specific compatible string but does not include a
> generic fallback string like "snps,dwc3". Because there is no matching driver
> in the kernel for "altr,agilex5-dwc3", won't the DWC3 core driver silently
> ignore this node and leave the controller unprobed?
> 
Disagree because: Agilex5 uses the dwc3-generic-plat path with a 
dedicated compatible, not a glue parent + child "snps,dwc3" node.

Adding "snps,dwc3" would violate the binding and could make 
drivers/usb/dwc3 core match the same node. Probe does not require a 
generic fallback here.
> [ ... ]
>