Re: [PATCH RFC v4 6/7] drm/msm/adreno: add Adreno 810 GPU support

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 4/16/26 1:05 PM, Alexander Koskovich wrote:
> Add catalog entry and register configuration for the Adreno 810
> found in Qualcomm SM7635 (Milos) based devices.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---

[...]

> +static const uint32_t a810_pwrup_reglist_regs[] = {
> +	REG_A6XX_UCHE_MODE_CNTL,
> +	REG_A8XX_UCHE_VARB_IDLE_TIMEOUT,
> +	REG_A8XX_UCHE_GBIF_GX_CONFIG,
> +	REG_A8XX_UCHE_CACHE_WAYS,
> +	REG_A8XX_UCHE_CCHE_MODE_CNTL,
> +	REG_A8XX_UCHE_CCHE_CACHE_WAYS,
> +	REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN,
> +	REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1,
> +	REG_A8XX_UCHE_CCHE_TRAP_BASE,
> +	REG_A8XX_UCHE_CCHE_TRAP_BASE + 1,
> +	REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE,
> +	REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1,
> +	REG_A8XX_UCHE_WRITE_THRU_BASE,
> +	REG_A8XX_UCHE_WRITE_THRU_BASE + 1,
> +	REG_A8XX_UCHE_TRAP_BASE,
> +	REG_A8XX_UCHE_TRAP_BASE + 1,
> +	REG_A8XX_UCHE_CLIENT_PF,
> +	REG_A8XX_VSC_BIN_SIZE,

This REG_A8XX_VSC_BIN_SIZE is removed from all lists for all chips
in newer kgsl

> +	REG_A8XX_RB_CMP_NC_MODE_CNTL,
> +	REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP,
> +	REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN,
> +	REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1,
> +	REG_A7XX_SP_READ_SEL,

Somewhat similarly,

TPL1_NC_MODE_CNTL
TPL1_DBG_ECO_CNTL
TPL1_DBG_ECO_CNTL1

should be preempt+ifpc for all targets, it seems

[...]

> +static const u32 a810_ifpc_reglist_regs[] = {
> +	REG_A8XX_RBBM_NC_MODE_CNTL,
> +	REG_A8XX_RBBM_PERFCTR_CNTL,

This list matches the expectations, modulo this RBBM_PERFCTR_CNTL
and the registers I mentioned above that should be moved to the
first list

[...]
> +static const struct adreno_reglist_pipe a810_dyn_pwrup_reglist_regs[] = {
> +	{ REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> +	{ REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> +	{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> +	{ REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> +	{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> +	{ REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) },

+ RB_CCU_DBG_ECO_CNTL to BR

[...]

> +		.speedbins = ADRENO_SPEEDBINS(
> +			{ 0,   0 },
> +			{ 242, 1 },
> +			{ 221, 2 },
> +		),

The DTs I have all point to SMEM-based SKU checks. Did you find these 
numbers empirically?

Konrad