* [PATCH] arm: dts: rk3288: Enable Cortex-A12 HW PMU events
@ 2015-04-07 17:52 Sonny Rao
2015-04-07 18:28 ` Doug Anderson
[not found] ` <1428429159-24102-1-git-send-email-sonnyrao-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
0 siblings, 2 replies; 3+ messages in thread
From: Sonny Rao @ 2015-04-07 17:52 UTC (permalink / raw)
To: Heiko Stuebner
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
dianders-F7+t8E8rja9g9hUCZPvPmw, Kever Yang,
devicetree-u79uwXL29TY76Z2rM5mHXA, Sonny Rao
This adds the dts node for the PMU with the correct PMUIRQ interrupts
for each core.
Signed-off-by: Sonny Rao <sonnyrao-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
arch/arm/boot/dts/rk3288.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 165968d..8253abb 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -44,6 +44,14 @@
spi2 = &spi2;
};
+ arm-pmu {
+ compatible = "arm,cortex-a12-pmu";
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.2.0.rc0.207.ga3a616c
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] arm: dts: rk3288: Enable Cortex-A12 HW PMU events
2015-04-07 17:52 [PATCH] arm: dts: rk3288: Enable Cortex-A12 HW PMU events Sonny Rao
@ 2015-04-07 18:28 ` Doug Anderson
[not found] ` <1428429159-24102-1-git-send-email-sonnyrao-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
1 sibling, 0 replies; 3+ messages in thread
From: Doug Anderson @ 2015-04-07 18:28 UTC (permalink / raw)
To: Sonny Rao
Cc: Heiko Stuebner, linux-kernel@vger.kernel.org,
open list:ARM/Rockchip SoC...,
linux-arm-kernel@lists.infradead.org, Kever Yang,
devicetree@vger.kernel.org
Hi,
On Tue, Apr 7, 2015 at 10:52 AM, Sonny Rao <sonnyrao@chromium.org> wrote:
> This adds the dts node for the PMU with the correct PMUIRQ interrupts
> for each core.
>
> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
> ---
> arch/arm/boot/dts/rk3288.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 165968d..8253abb 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -44,6 +44,14 @@
> spi2 = &spi2;
> };
>
> + arm-pmu {
> + compatible = "arm,cortex-a12-pmu";
> + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
As per discussion with Rockchip: these numbers don't actually match
the TRM, but apparently the TRM is wrong.
Since these numbers work and the numbers came from Rockchip:
Reviewed-by: Doug Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 3+ messages in thread[parent not found: <1428429159-24102-1-git-send-email-sonnyrao-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>]
end of thread, other threads:[~2015-04-07 21:38 UTC | newest]
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2015-04-07 17:52 [PATCH] arm: dts: rk3288: Enable Cortex-A12 HW PMU events Sonny Rao
2015-04-07 18:28 ` Doug Anderson
[not found] ` <1428429159-24102-1-git-send-email-sonnyrao-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2015-04-07 21:38 ` Heiko Stübner
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