[PATCH 0/2] Remove gold/silver_cpu_sleep idle states for lemans and monaco

[PATCH 0/2] Remove gold/silver_cpu_sleep idle states for lemans and monaco

[Navya Malempati]

Firmware supports both CPU power collapse and CPU PLL/rail power collapse
idle states. However, CPU power collapse mode is often not utilized in 
favor of performance. Remove CPU power collapse modes for lemans and 
monaco as well aligning with SM8350/SM8450/SM8550/SM8650.

---
Navya Malempati (2):
      arm64: dts: qcom: monaco: Remove the little/big_cpu_sleep_0 idle states
      arm64: dts: qcom: lemans: Remove the gold_cpu_sleep idle state

 arch/arm64/boot/dts/qcom/lemans.dtsi | 36 +++++++++---------------------------
 arch/arm64/boot/dts/qcom/monaco.dtsi | 36 ++++++++----------------------------
 2 files changed, 17 insertions(+), 55 deletions(-)
---
base-commit: 550604d6c9b9efc8d068aff94dc301694a7afdee
change-id: 20260522-ml_cpuidle-da0377956dc0

Best regards,
--  
Navya Malempati <navya.malempati@oss.qualcomm.com>

[PATCH 1/2] arm64: dts: qcom: monaco: Remove the little/big_cpu_sleep_0 idle states

[Navya Malempati]

Firmware supports both CPU power collapse (little/big_cpu_sleep_0) and
CPU PLL/rail power collapse (little/big_cpu_sleep_1) idle states.
However, CPU power collapse modes are often not utilized in favor of
performance, so remove the CPU power collapse modes for monaco,
aligning with SM8350/SM8450/SM8550/SM8650.

Rename little/big_cpu_sleep_1 as little/big_cpu_sleep_0 since it is now
the only CPU idle state in use.

Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco.dtsi | 36 ++++++++----------------------------
 1 file changed, 8 insertions(+), 28 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index ce6ff259cb4a..fed94cdbe41d 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -309,16 +309,6 @@ idle-states {
 			entry-method = "psci";
 
 			little_cpu_sleep_0: cpu-sleep-0-0 {
-				compatible = "arm,idle-state";
-				idle-state-name = "silver-power-collapse";
-				arm,psci-suspend-param = <0x40000003>;
-				entry-latency-us = <449>;
-				exit-latency-us = <801>;
-				min-residency-us = <1574>;
-				local-timer-stop;
-			};
-
-			little_cpu_sleep_1: cpu-sleep-0-1 {
 				compatible = "arm,idle-state";
 				idle-state-name = "silver-rail-power-collapse";
 				arm,psci-suspend-param = <0x40000004>;
@@ -329,16 +319,6 @@ little_cpu_sleep_1: cpu-sleep-0-1 {
 			};
 
 			big_cpu_sleep_0: cpu-sleep-1-0 {
-				compatible = "arm,idle-state";
-				idle-state-name = "gold-power-collapse";
-				arm,psci-suspend-param = <0x40000003>;
-				entry-latency-us = <549>;
-				exit-latency-us = <901>;
-				min-residency-us = <1774>;
-				local-timer-stop;
-			};
-
-			big_cpu_sleep_1: cpu-sleep-1-1 {
 				compatible = "arm,idle-state";
 				idle-state-name = "gold-rail-power-collapse";
 				arm,psci-suspend-param = <0x40000004>;
@@ -681,49 +661,49 @@ psci {
 		cpu_pd0: power-domain-cpu0 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd0>;
-			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+			domain-idle-states = <&big_cpu_sleep_0>;
 		};
 
 		cpu_pd1: power-domain-cpu1 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd0>;
-			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+			domain-idle-states = <&big_cpu_sleep_0>;
 		};
 
 		cpu_pd2: power-domain-cpu2 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd0>;
-			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+			domain-idle-states = <&big_cpu_sleep_0>;
 		};
 
 		cpu_pd3: power-domain-cpu3 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd0>;
-			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+			domain-idle-states = <&big_cpu_sleep_0>;
 		};
 
 		cpu_pd4: power-domain-cpu4 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd1>;
-			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+			domain-idle-states = <&little_cpu_sleep_0>;
 		};
 
 		cpu_pd5: power-domain-cpu5 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd1>;
-			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+			domain-idle-states = <&little_cpu_sleep_0>;
 		};
 
 		cpu_pd6: power-domain-cpu6 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd1>;
-			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+			domain-idle-states = <&little_cpu_sleep_0>;
 		};
 
 		cpu_pd7: power-domain-cpu7 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd1>;
-			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+			domain-idle-states = <&little_cpu_sleep_0>;
 		};
 
 		cluster_pd0: power-domain-cluster0 {

-- 
2.34.1

Re: [PATCH 1/2] arm64: dts: qcom: monaco: Remove the little/big_cpu_sleep_0 idle states

[Maulik Shah (mkshah)]

On 5/22/2026 4:40 PM, Navya Malempati wrote:
> Firmware supports both CPU power collapse (little/big_cpu_sleep_0) and
> CPU PLL/rail power collapse (little/big_cpu_sleep_1) idle states.
> However, CPU power collapse modes are often not utilized in favor of
> performance, so remove the CPU power collapse modes for monaco,
> aligning with SM8350/SM8450/SM8550/SM8650.
> 
> Rename little/big_cpu_sleep_1 as little/big_cpu_sleep_0 since it is now
> the only CPU idle state in use.
> 
> Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com>

Reviewed-by: Maulik Shah <maulik.shah@oss.qualcomm.com>

Thanks,
Maulik

Re: [PATCH 1/2] arm64: dts: qcom: monaco: Remove the little/big_cpu_sleep_0 idle states

[Dmitry Baryshkov]

On Fri, May 22, 2026 at 04:40:13PM +0530, Navya Malempati wrote:
> Firmware supports both CPU power collapse (little/big_cpu_sleep_0) and
> CPU PLL/rail power collapse (little/big_cpu_sleep_1) idle states.
> However, CPU power collapse modes are often not utilized in favor of
> performance, so remove the CPU power collapse modes for monaco,

They are not used now. Will they be used if the cpuidle governor is
changed? If they are valid from the hardware point of view, why do you
want to remove them?

> aligning with SM8350/SM8450/SM8550/SM8650.
> 
> Rename little/big_cpu_sleep_1 as little/big_cpu_sleep_0 since it is now
> the only CPU idle state in use.
> 
> Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/monaco.dtsi | 36 ++++++++----------------------------
>  1 file changed, 8 insertions(+), 28 deletions(-)
> 

-- 
With best wishes
Dmitry

Re: [PATCH 1/2] arm64: dts: qcom: monaco: Remove the little/big_cpu_sleep_0 idle states

[Navya Malempati]

On 6/8/2026 12:54 AM, Dmitry Baryshkov wrote:
> On Fri, May 22, 2026 at 04:40:13PM +0530, Navya Malempati wrote:
>> Firmware supports both CPU power collapse (little/big_cpu_sleep_0) and
>> CPU PLL/rail power collapse (little/big_cpu_sleep_1) idle states.
>> However, CPU power collapse modes are often not utilized in favor of
>> performance, so remove the CPU power collapse modes for monaco,
> 
> They are not used now. Will they be used if the cpuidle governor is
> changed? If they are valid from the hardware point of view, why do you
> want to remove them?
> 

Even though they are valid from hardware and can be used, they do not 
seem to be benefiting power/performance, hence removing them. This is 
irrespective of cpuidle governor menu/teo making use of them.

Thanks,
Navya

[PATCH 2/2] arm64: dts: qcom: lemans: Remove the gold_cpu_sleep idle state

[Navya Malempati]

Firmware supports both CPU power collapse (gold_cpu_sleep_0) and
CPU PLL/rail power collapse (gold_rail_cpu_sleep_0) idle states.
However, CPU power collapse mode is not utilized in favor of performance,
so remove it for lemans, aligning with SM8350/SM8450/SM8550/SM8650.

Rename gold_rail_cpu_sleep_0 from cpu-sleep-1 to cpu-sleep-0 since it is
now the only CPU idle state in use.

Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/lemans.dtsi | 36 +++++++++---------------------------
 1 file changed, 9 insertions(+), 27 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index bc7b4f65ad5e..cfca4895e9ec 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -297,17 +297,7 @@ core3 {
 		idle-states {
 			entry-method = "psci";
 
-			gold_cpu_sleep_0: cpu-sleep-0 {
-				compatible = "arm,idle-state";
-				idle-state-name = "gold-power-collapse";
-				arm,psci-suspend-param = <0x40000003>;
-				entry-latency-us = <549>;
-				exit-latency-us = <901>;
-				min-residency-us = <1774>;
-				local-timer-stop;
-			};
-
-			gold_rail_cpu_sleep_0: cpu-sleep-1 {
+			gold_rail_cpu_sleep_0: cpu-sleep-0 {
 				compatible = "arm,idle-state";
 				idle-state-name = "gold-rail-power-collapse";
 				arm,psci-suspend-param = <0x40000004>;
@@ -566,57 +556,49 @@ psci {
 		cpu_pd0: power-domain-cpu0 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_0_pd>;
-			domain-idle-states = <&gold_cpu_sleep_0>,
-					     <&gold_rail_cpu_sleep_0>;
+			domain-idle-states = <&gold_rail_cpu_sleep_0>;
 		};
 
 		cpu_pd1: power-domain-cpu1 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_0_pd>;
-			domain-idle-states = <&gold_cpu_sleep_0>,
-					     <&gold_rail_cpu_sleep_0>;
+			domain-idle-states = <&gold_rail_cpu_sleep_0>;
 		};
 
 		cpu_pd2: power-domain-cpu2 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_0_pd>;
-			domain-idle-states = <&gold_cpu_sleep_0>,
-					     <&gold_rail_cpu_sleep_0>;
+			domain-idle-states = <&gold_rail_cpu_sleep_0>;
 		};
 
 		cpu_pd3: power-domain-cpu3 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_0_pd>;
-			domain-idle-states = <&gold_cpu_sleep_0>,
-					     <&gold_rail_cpu_sleep_0>;
+			domain-idle-states = <&gold_rail_cpu_sleep_0>;
 		};
 
 		cpu_pd4: power-domain-cpu4 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_1_pd>;
-			domain-idle-states = <&gold_cpu_sleep_0>,
-					     <&gold_rail_cpu_sleep_0>;
+			domain-idle-states = <&gold_rail_cpu_sleep_0>;
 		};
 
 		cpu_pd5: power-domain-cpu5 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_1_pd>;
-			domain-idle-states = <&gold_cpu_sleep_0>,
-					     <&gold_rail_cpu_sleep_0>;
+			domain-idle-states = <&gold_rail_cpu_sleep_0>;
 		};
 
 		cpu_pd6: power-domain-cpu6 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_1_pd>;
-			domain-idle-states = <&gold_cpu_sleep_0>,
-					     <&gold_rail_cpu_sleep_0>;
+			domain-idle-states = <&gold_rail_cpu_sleep_0>;
 		};
 
 		cpu_pd7: power-domain-cpu7 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_1_pd>;
-			domain-idle-states = <&gold_cpu_sleep_0>,
-					     <&gold_rail_cpu_sleep_0>;
+			domain-idle-states = <&gold_rail_cpu_sleep_0>;
 		};
 
 		cluster_0_pd: power-domain-cluster0 {

-- 
2.34.1

Re: [PATCH 2/2] arm64: dts: qcom: lemans: Remove the gold_cpu_sleep idle state

[Maulik Shah (mkshah)]

On 5/22/2026 4:40 PM, Navya Malempati wrote:
> Firmware supports both CPU power collapse (gold_cpu_sleep_0) and
> CPU PLL/rail power collapse (gold_rail_cpu_sleep_0) idle states.
> However, CPU power collapse mode is not utilized in favor of performance,
> so remove it for lemans, aligning with SM8350/SM8450/SM8550/SM8650.
> 
> Rename gold_rail_cpu_sleep_0 from cpu-sleep-1 to cpu-sleep-0 since it is
> now the only CPU idle state in use.
> 
> Signed-off-by: Navya Malempati <navya.malempati@oss.qualcomm.com>

Reviewed-by: Maulik Shah <maulik.shah@oss.qualcomm.com>

Thanks,
Maulik

Re: [PATCH 0/2] Remove gold/silver_cpu_sleep idle states for lemans and monaco

[Bjorn Andersson]

On Fri, 22 May 2026 16:40:12 +0530, Navya Malempati wrote:
> Firmware supports both CPU power collapse and CPU PLL/rail power collapse
> idle states. However, CPU power collapse mode is often not utilized in
> favor of performance. Remove CPU power collapse modes for lemans and
> monaco as well aligning with SM8350/SM8450/SM8550/SM8650.
> 

Applied, thanks!

[1/2] arm64: dts: qcom: monaco: Remove the little/big_cpu_sleep_0 idle states
      commit: 00dd037fc31452962eba38cdb46feafb0b70d96e
[2/2] arm64: dts: qcom: lemans: Remove the gold_cpu_sleep idle state
      commit: f212c011af87e65c5147bfd61d786d681be91d40

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>