Re: [PATCH v2] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 6/10/26 5:10 AM, Jie Luo wrote:
> 
> 
> On 6/10/2026 12:59 AM, Kathiravan Thirumoorthy wrote:
>>
>> On 6/9/2026 8:42 PM, Konrad Dybcio wrote:
>>> On 5/21/26 9:55 AM, George Moussalem via B4 Relay wrote:
>>>> From: George Moussalem <george.moussalem@outlook.com>
>>>>
>>>> The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.
>>>>
>>>> The CMN PLL driver did not account for the ref clock divider which is 2
>>>> for IPQ5018. Therefore, the computed rate was twice the actual output.
>>>>
>>>> With the driver now accounting for the CMN PLL reference clock
>>>> divider (commit: 88c543fff756), set the correct reference clock rate.
>>>>
>>>> Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")
>>>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>>>> ---
>>>> Changes in v2:
>>>> - Removed line break in commit message between Fixes and SOB tags
>>>> - Link to v1: https://patch.msgid.link/20260519-ipq5018-cmn-pll-rate-
>>>> fix-v1-1-3c83a173c27f@outlook.com
>>>> ---
>>> I have no reference for this, but I trust you.. maybe +Kathiravan
>>> could double-check
>>
>> Thanks Konrad. As per the HW doc and the commit 88c543fff756 ("clk:
>> qcom: cmnpll: Account for reference clock divider"), default ref clock
>> divider is 1 in IPQ5018.
>>
>> @Jie, Can you help here?
>>
> 
> Hello Konrad, Kathiravan,
> As confirmed on the IPQ5018 RDP board, the ref clock divider is set to 2.

Thanks

Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad